arch/arm/dts/imx6ul-phycore-segin.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Collabora Ltd.
   4  *
   5  * Based on dts[i] from Phytec barebox port:
   6  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
   7  * Author: Christian Hemp <c.hemp@phytec.de>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 /dts-v1/;
  18
  19 #include "imx6ul.dtsi"
  20 #include "pcl063-common.dtsi"
  21
  22 / {
  23         model = "Phytec phyBOARD-i.MX6UL-Segin SBC";
  24         compatible = "phytec,phyboard-imx6ul-segin", "phytec,imx6ul-pcl063",
  25                      "fsl,imx6ul";
  26 };
  27
  28 &gpmi {
  29         status = "okay";
  30 };
  31
  32 &i2c1 {
  33         i2c_rtc: rtc@68 {
  34                 compatible = "microcrystal,rv4162";
  35                 reg = <0x68>;
  36                 status = "okay";
  37         };
  38 };
  39
  40 &uart5 {
  41         pinctrl-names = "default";
  42         pinctrl-0 = <&pinctrl_uart5>;
  43         uart-has-rtscts;
  44         status = "okay";
  45 };
  46
  47 &usbotg1 {
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&pinctrl_usb_otg1_id>;
  50         dr_mode = "otg";
  51         srp-disable;
  52         hnp-disable;
  53         adp-disable;
  54         status = "okay";
  55 };
  56
  57 &usbotg2 {
  58         dr_mode = "host";
  59         disable-over-current;
  60         status = "okay";
  61 };
  62
  63 &iomuxc {
  64         pinctrl-names = "default";
  65
  66         pinctrl_uart5: uart5grp {
  67                 fsl,pins = <
  68                         MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX   0x1b0b1
  69                         MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX   0x1b0b1
  70                         MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS     0x1b0b1
  71                         MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS     0x1b0b1
  72                 >;
  73         };
  74
  75         pinctrl_usb_otg1_id: usbotg1idgrp {
  76                 fsl,pins = <
  77                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
  78                 >;
  79         };
  80
  81 };