arch/arm/include/asm/arch-bcm63146/misc.h

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  *
   3  *  Copyright 2019 Broadcom Ltd.
   4  */
   5
   6 #ifndef _63146_MISC_H
   7 #define _63146_MISC_H
   8
   9 #define MISC_BASE          0xff802600
  10
  11 /*
  12  * Misc Register Set Definitions.
  13  */
  14 typedef struct Misc {
  15    uint32_t miscStrapBus; /* 0x00 */
  16
  17     /* boot select bits 3-5 */
  18 #define BOOT_SEL_STRAP_NAND_2K_PAGE             0x00
  19 #define BOOT_SEL_STRAP_NAND_4K_PAGE             0x08
  20 #define BOOT_SEL_STRAP_NAND_8K_PAGE             0x10
  21 #define BOOT_SEL_STRAP_NAND_512B_PAGE           0x18
  22 #define BOOT_SEL_STRAP_SPI_NOR                  0x38
  23 #define BOOT_SEL_STRAP_EMMC                     0x30
  24 #define BOOT_SEL_STRAP_SPI_NAND                 0x28
  25
  26 #define BOOT_SEL_STRAP_BOOT_SEL_MASK            (0x38)
  27 #define BOOT_SEL_STRAP_PAGE_SIZE_MASK           (0x7)
  28
  29 #define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
  30 #define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  31 #define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  32 #define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  33 #define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  34 #define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  35 #define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  36 #define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  37 #define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  38 #define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  39 #define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  40 #define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  41 #define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  42 #define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  43 #define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  44 #define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  45 #define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  46 #define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  47 #define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  48 #define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  49 #define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  50 #define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 6)
  51 #define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE     (0x1 << 7)
  52 #define MISC_STRAP_BUS_B53_BOOT_N               (0x1 << 8)
  53 /* When ROM BOOT OTP bits are 2b'11, always boot rom secure boot, this strap bit is don't care.
  54    When ROM BOOT OTP bits are are not 2b'11, this trap bit determine the following:
  55    1: boot rom non-secure boot
  56    0: XIP boot
  57 */
  58 #define MISC_STRAP_BUS_BOOTROM_BOOT             (0x1 << 12)
  59 #define MISC_STRAP_BUS_SW_RESERVE_MASK          (0x3 << 14)
  60 #define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      16
  61 #define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
  62    uint32_t miscStrapOverride;     /* 0x04 */
  63    uint32_t miscMaskUBUSErr;       /* 0x08 */
  64    uint32_t miscPeriphCtrl;        /* 0x0c */
  65    uint32_t miscSpiMasterCtrl;     /* 0x10 */
  66    uint32_t reserved0;             /* 0x14 */
  67    uint32_t miscPeriphMiscCtrl;    /* 0x18 */
  68    uint32_t miscPeriphMiscStat;    /* 0x1c */
  69    uint32_t miscSoftResetB;        /* 0x20 */
  70    uint32_t miscSpare0;            /* 0x24 */
  71    uint32_t miscSWdebugNW[2];      /* 0x28 */
  72    uint32_t miscWDResetCtrl;       /* 0x30 */
  73 } Misc;
  74
  75 #define MISC ((volatile Misc * const) MISC_BASE)
  76
  77
  78 /*
  79  * Gpio Controller
  80  */
  81 typedef struct GpioControl {
  82         uint32_t GPIODir[8];             /* 0x00-0x1f */
  83         uint32_t GPIOio[8];              /* 0x20-0x3f */
  84         uint32_t PadCtrl;                 /* 0x40 */
  85         uint32_t SpiSlaveCfg;             /* 0x44 */
  86         uint32_t TestControl;             /* 0x48 */
  87         uint32_t TestPortBlockEnMSB;      /* 0x4c */
  88         uint32_t TestPortBlockEnLSB;      /* 0x50 */
  89         uint32_t TestPortBlockDataMSB;    /* 0x54 */
  90         uint32_t TestPortBlockDataLSB;    /* 0x58 */
  91         uint32_t TestPortCmd;             /* 0x5c */
  92         uint32_t DiagReadBack;            /* 0x60 */
  93         uint32_t DiagReadBackHi;          /* 0x64 */
  94         uint32_t GeneralPurpose;          /* 0x68 */
  95         uint32_t spare[3];
  96 } GpioControl;
  97
  98 #define GPIO_BASE              0xff800500
  99 #define GPIO ((volatile GpioControl * const) GPIO_BASE)
 100 #define PINCTRL_BASE           (GPIO_BASE + 0x54)
 101
 102 // PERF
 103 typedef struct PerfControl { /* GenInt */
 104      uint32_t        RevID;             /* (00) word 0 */
 105 #define CHIP_ID_SHIFT   12
 106 #define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
 107 #define REV_ID_MASK     0xfff
 108 } PerfControl;
 109
 110 #define PERF_BASE              0xff800000
 111 #define PERF ((volatile PerfControl * const) PERF_BASE)
 112
 113 #define BCM_WDT_SOFT_RESET (PERF_BASE+0x48c)
 114 #define BCM_LOWLEVEL_RESET() { *((volatile uint32_t *)BCM_WDT_SOFT_RESET) = 1; }
 115
 116 #endif