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Add Broadcom / Netgear changes from RAXE 1.0.0.48
[project/bcm63xx/u-boot.git] / arch / arm / include / asm / arch-bcm63158 / BPCM.h
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2013 Broadcom
4 */
5 /*
6
7 */
8 #ifndef BPCM_H
9 #define BPCM_H
10
11 typedef union {
12 struct {
13 uint32_t pmb_Addr:8;
14 uint32_t hw_rev:8;
15 uint32_t sw_strap:16;
16 } Bits;
17 uint32_t Reg32;
18 } BPCM_ID_REG;
19
20 // types of PMB devices
21 enum {
22 kPMB_BPCM = 0,
23 kPMB_MIPS_PLL = 1,
24 kPMB_GEN_PLL = 2,
25 kPMB_LC_PLL = 3,
26 // 4..15 reserved
27 };
28
29 typedef union {
30 struct {
31 uint32_t num_zones:8;
32 uint32_t num_sr_bits:8;
33 uint32_t devType:4; // see enum above
34 uint32_t reserved1:12;
35 } Bits;
36 uint32_t Reg32;
37 } BPCM_CAPABILITES_REG;
38
39 typedef union {
40 struct {
41 uint32_t pwd_alert:1;
42 uint32_t reserved:31;
43 } Bits;
44 uint32_t Reg32;
45 } BPCM_STATUS_REG;
46
47 typedef union {
48 struct {
49 uint32_t ro_en_s:1;
50 uint32_t ro_en_h:1;
51 uint32_t ectr_en_s:1;
52 uint32_t ectr_en_h:1;
53 uint32_t thresh_en_s:1;
54 uint32_t thresh_en_h:1;
55 uint32_t continuous_s:1;
56 uint32_t continuous_h:1;
57 uint32_t reserved:4;
58 uint32_t valid_s:1;
59 uint32_t alert_s:1;
60 uint32_t valid_h:1;
61 uint32_t alert_h:1;
62 uint32_t interval:16;
63 } Bits;
64 uint32_t Reg32;
65 } BPCM_AVS_ROSC_CONTROL_REG;
66
67 typedef union {
68 struct {
69 uint32_t thresh_lo:16;
70 uint32_t thresh_hi:16;
71 } Bits;
72 uint32_t Reg32;
73 } BPCM_AVS_ROSC_THRESHOLD;
74
75 typedef union {
76 struct {
77 uint32_t count_s:16;
78 uint32_t count_h:16;
79 } Bits;
80 uint32_t Reg32;
81 } BPCM_AVS_ROSC_COUNT;
82
83 typedef union {
84 struct {
85 uint32_t pwd_en:1;
86 uint32_t pwd_alert_sel:1;
87 uint32_t start:6;
88 uint32_t pwd_tm_en:1;
89 uint32_t reserved2:6;
90 uint32_t alert:1;
91 uint32_t ccfg:8;
92 uint32_t rsel:3;
93 uint32_t clr_cfg:3;
94 uint32_t reserved1:2;
95 } Bits;
96 uint32_t Reg32;
97 } BPCM_AVS_PWD_CONTROL;
98
99 typedef union {
100 struct {
101 uint32_t tbd:32;
102 } Bits;
103 uint32_t Reg32;
104 } BPCM_PWD_ACCUM_CONTROL;
105
106 typedef union {
107 struct {
108 uint32_t sr:8;
109 uint32_t gp:24;
110 } Bits;
111 struct {
112 uint32_t wan_main_rst_n:1;
113 uint32_t wan_top_bb_rst_n:1;
114 uint32_t rbus_rst_n:1;
115 uint32_t reserved1:2;
116 uint32_t core_soft_rst_n:1;
117 uint32_t i_zn_sw_init:1;
118 uint32_t reserved2:1;
119 uint32_t epon_main_rst_n:1;
120 uint32_t epon_rx_rst_n:1;
121 uint32_t epon_tx_rst_n:1;
122 uint32_t epon_core_rst_n:1;
123 uint32_t ae_rx_rclk16_sw_reset_n:1;
124 uint32_t ae_rx_rbc125_sw_reset_n:1; /* for B0 */
125 uint32_t ae_tx_tclk16_sw_reset_n:1; /* for B0 */
126 uint32_t ae_tx_clk125_sw_reset_n:1;
127 uint32_t gpon_main_rst_n:1;
128 uint32_t gpon_rx_rst_n:1;
129 uint32_t gpon_tx_rst_n:1;
130 uint32_t gpon_8khz_rst_n:1;
131 uint32_t ngpon_main_rst_n:1;
132 uint32_t ngpon_rx_rst_n:1;
133 uint32_t ngpon_tx_rst_n:1;
134 uint32_t ngpon_8khz_rst_n:1;
135 uint32_t reserved3:2;
136 uint32_t gpon_nco_rst_n:1;
137 uint32_t epon_rx_rclk16_sw_reset_n:1; /* for B0 */
138 uint32_t epon_rx_rbc125_sw_reset_n:1; /* for B0 */
139 uint32_t epon_tx_tclk16_sw_reset_n:1; /* for B0 */
140 uint32_t epon_tx_clk125_sw_reset_n:1; /* for B0 */
141 uint32_t reserved4:1;
142 } Bits_Wantop;
143 struct {
144 uint32_t vdsl_bpcm_early_reset:1;
145 uint32_t vdsl_bpcm_reset:1;
146 uint32_t mips_ubus_soft_reset_bpcm_reset:1;
147 uint32_t qproc_1_bpcm_reset:1;
148 uint32_t qproc_2_bpcm_reset:1;
149 uint32_t sar_bpcm_soft_reset:1;
150 uint32_t vdsl_ubus_soft_bpcm_reset:1;
151 uint32_t reserved1:1;
152 uint32_t gp:24;
153 } Bits_vdsl;
154 uint32_t Reg32;
155 } BPCM_SR_CONTROL;
156
157 typedef union{
158 struct {
159 uint32_t tbd:32;
160 } Bits;
161 uint32_t Reg32;
162 struct {
163 uint32_t vdsl_arm_por_reset_n:1;
164 uint32_t vdsl_arm_reset_n:1;
165 uint32_t vdsl_arm_debug_reset_n:1;
166 uint32_t vdsl_arm_l2_reset_n:1;
167 uint32_t vdsl_arm_cdbgrstreq_en:1;
168 uint32_t vdsl_arm_niden_a7_b0:1;
169 uint32_t vdsl_arm_spniden_a7_b0:1;
170 uint32_t vdsl_arm_nsocdbgreset_a7:1;
171 uint32_t axi4_ubus4_pass_through_disable:1;
172 uint32_t vdsl_arm_dbgen_a7_b0:1;
173 uint32_t vdsl_arm_spiden_a7_b0:1;
174 uint32_t vdsl_arm_scratch_reg:21;
175 } Bits_vdsl;
176 } BPCM_VDSL_ARM_RST_CTL;
177
178 typedef union {
179 struct {
180 uint32_t z2_p_wan_phy_sel:3; /* 0-2 */
181 uint32_t reserved0:1; /* 3 */
182 uint32_t z2_switch_p3_phy_sel:3; /* 4-6 */
183 uint32_t reserved1:1; /* 7 */
184 uint32_t z2_switch_p4_phy_sel:3; /* 8-10 */
185 uint32_t reserved2:1; /* 11 */
186 uint32_t z0_mux_sel:1; /* 12 */
187 uint32_t z1_gphy_mux_sel:1; /* 13 */
188 uint32_t z2_gphy_mux_sel:1; /* 14 */
189 uint32_t z2_crossbar_mux_sel:1; /* 15 */
190 uint32_t reserved3:1; /* 16 */
191 uint32_t z1_pda_en:1; /* 17 */
192 uint32_t z1_ck250_clk_en:1; /* 18 */
193 uint32_t z1_ck25_clk_dis:1; /* 19 */
194 uint32_t reserved4:2; /* 20-21 */
195 uint32_t z2_ck250_clk_en:1; /* 22 */
196 uint32_t z2_ck25_clk_dis:1; /* 23 */
197 uint32_t z2_serdes_clk_en:1; /* 24 */
198 uint32_t z2_serdes_reset_mdioregs:1; /* 25 */
199 uint32_t z2_sedes_reset_pll:1; /* 26 */
200 uint32_t z2_serdes_reset:1; /* 27 */
201 uint32_t z2_serdes_mux_sel:1; /* 28 */
202 uint32_t reserved5:1; /* 29 */
203 uint32_t z1_gphy_reset:1; /* 30 */
204 uint32_t z2_gphy_reset:1; /* 31 */
205 } Bits;
206 uint32_t Reg32;
207 } BPCM_GLOBAL_CNTL;
208
209 typedef union {
210 struct {
211 uint32_t z0_mux_sel:1; // = r_Z0_GLOBAL_CNTL[0];
212 uint32_t reserverd_1:1; // unused
213 uint32_t z3_pda_en:1; // = r_Z0_GLOBAL_CNTL[2];
214 uint32_t rx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[3];
215 uint32_t tx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[4];
216 uint32_t gmii_rx_clk_en:1; // = r_Z0_GLOBAL_CNTL[5];
217 uint32_t gmii_tx_clk_en:1; // = r_Z0_GLOBAL_CNTL[6];
218 uint32_t rsrvd:25;
219 } Bits;
220 uint32_t Reg32;
221
222 } BPCM_GLOBAL_CNTL_0;
223
224 typedef union {
225 struct {
226 uint32_t z1_pda_en:1; //= r_Z1_GLOBAL_CNTL[0];
227 uint32_t reserved:2;
228 uint32_t z1_ck250_clk_en:1; //= r_Z1_GLOBAL_CNTL[3];
229 uint32_t z1_ref_clk_dis:1; //= r_Z1_GLOBAL_CNTL[4];
230 uint32_t z1_mux_sel:1; //= r_Z1_GLOBAL_CNTL[5];
231 uint32_t z1_gphy_reset:1; //= r_Z1_GLOBAL_CNTL[6];
232 uint32_t z1_gphy_iddq_global_pwr:1; //= r_Z1_GLOBAL_CNTL[7];
233 uint32_t z1_gphy_force_dll_en:1; //= r_Z1_GLOBAL_CNTL[8];
234 uint32_t z1_gphy_ext_pwr_down:4; //= r_Z1_GLOBAL_CNTL[12:9];
235 uint32_t z1_gphy_iddq_bias:1; //= r_Z1_GLOBAL_CNTL[13];
236 uint32_t z1_switch_p3_phy_sel:1; //= r_Z1_GLOBAL_CNTL[14];
237 uint32_t z1_switch_p8_sel:1; //= r_Z1_GLOBAL_CNTL[15];
238 uint32_t rsrvd:16;
239 } Bits;
240 uint32_t Reg32;
241
242 } BPCM_GLOBAL_CNTL_1;
243
244 typedef union {
245 struct {
246 uint32_t z2_pda_en:1; //= r_Z2_GLOBAL_CNTL[0];
247 uint32_t reserved:1;
248 uint32_t z2_ck250_clk_en:1; //= r_Z2_GLOBAL_CNTL[2];
249 uint32_t z2_ref_clk_dis:1; //= r_Z2_GLOBAL_CNTL[3];
250 uint32_t z2_serdes_clk_en:1; //= r_Z2_GLOBAL_CNTL[4];
251 uint32_t z2_gphy_mux_sel:1; //= r_Z2_GLOBAL_CNTL[5];
252 uint32_t z2_gphy_reset:1; //= r_Z2_GLOBAL_CNTL[6];
253 uint32_t z2_gphy_iddq_global_pwr:1; //= r_Z2_GLOBAL_CNTL[7];
254 uint32_t z2_gphy_force_dll_en:1; //= r_Z2_GLOBAL_CNTL[8];
255 uint32_t z2_gphy_ext_pwr_down:1; //= r_Z2_GLOBAL_CNTL[9];
256 uint32_t z2_gphy_iddq_bias:1; //= r_Z2_GLOBAL_CNTL[10];
257 uint32_t z2_crossbar_mux_sel:1; //= r_Z2_GLOBAL_CNTL[11];
258 uint32_t z2_p_wan_phy_sel:2; //= r_Z2_GLOBAL_CNTL[13:12];
259 uint32_t z2_switch_p4_phy_sel:2; //= r_Z2_GLOBAL_CNTL[15:14];
260 uint32_t z2_switch_p6_phy_sel:2; //= r_Z2_GLOBAL_CNTL[17:16];
261 uint32_t z2_serdes_mux_sel:1; //= r_Z2_GLOBAL_CNTL[18];
262 uint32_t z2_serdes_iddq:1; //= r_Z2_GLOBAL_CNTL[19];
263 uint32_t z2_serdes_pwrdwn:1; //= r_Z2_GLOBAL_CNTL[20];
264 uint32_t z2_serdes_reset:1; //= r_Z2_GLOBAL_CNTL[21];
265 uint32_t z2_serdes_reset_mdioregs:1; //= r_Z2_GLOBAL_CNTL[22];
266 uint32_t z2_serdes_reset_pll:1; //= r_Z2_GLOBAL_CNTL[23];
267 uint32_t z2_serdes_refclk_sel:3; //= r_Z2_GLOBAL_CNTL[26:24];
268 uint32_t z2_pll_clk125_250_sel:1; //= r_Z2_GLOBAL_CNTL[27];
269 uint32_t z2_pll_mux_clk250_sel:1; //= r_Z2_GLOBAL_CNTL[28];
270 uint32_t rsrvd:3;
271 } Bits;
272 uint32_t Reg32;
273
274 } BPCM_GLOBAL_CNTL_2;
275
276 typedef union {
277 struct {
278 uint32_t ctl;
279 } Bits_sata_gp;
280 struct {
281 uint32_t iddq_bias:1; /* 0 */
282 uint32_t ext_pwr_down:4; /* 1-4 */
283 uint32_t force_dll_en:1; /* 5 */
284 uint32_t iddq_global_pwr:1; /* 6 */
285 uint32_t reserved:25;
286 } Bits_switch_z1_qgphy;
287 struct {
288 uint32_t iddq_bias:1; /* 0 */
289 uint32_t ext_pwr_down:1; /* 1 */
290 uint32_t force_dll_en:1; /* 2 */
291 uint32_t iddq_global_pwd:1; /* 3 */
292 uint32_t ck25_dis:1; /* 4 */
293 uint32_t phy_reset:1; /* 5 */
294 uint32_t reserved0:2;
295 uint32_t phy_ad:5; /* 8-12 */
296 uint32_t reserved1:18;
297 uint32_t ctrl_en:1; /* 31 */
298 } Bits_egphy_1port;
299 struct {
300 uint32_t iddq_bias:1; /* 0 */
301 uint32_t ext_pwr_down:4; /* 1-4 */
302 uint32_t force_dll_en:1; /* 5 */
303 uint32_t iddq_global_pwd:1; /* 6 */
304 uint32_t ck25_dis:1; /* 7 */
305 uint32_t phy_reset:1; /* 8 */
306 uint32_t reserved0:3;
307 uint32_t phy_ad:5; /* 12-16 */
308 uint32_t reserved1:14;
309 uint32_t ctrl_en:1; /* 31 */
310 } Bits_egphy_4port;
311 struct {
312 uint32_t iddq_bias:1; /* 0 */
313 uint32_t ext_pwr_down:4; /* 1-4 */
314 uint32_t force_dll_en:1; /* 5 */
315 uint32_t iddq_global_pwr:1; /* 6 */
316 uint32_t reserved0:25; /* 7-31 */
317 } Bits_qgphy_cntl;
318 struct {
319 uint32_t ctl;
320 } Bits_vdsl_phy;
321 struct {
322 uint32_t alt_bfc_vector:12; /* 00-11 */
323 uint32_t reserved0:3;
324 uint32_t alt_bfc_en:1; /* 15 */
325 uint32_t reset_dly_cfg:2; /* 16-17 */
326 uint32_t reserved1:8;
327 uint32_t ext_mclk_en_reset:1; /* 26 */
328 uint32_t ext_mclk_en:1; /* 27 */
329 uint32_t por_reset_n_ctl:1; /* 28 */
330 uint32_t reset_n_ctl:1; /* 29 */
331 uint32_t reserved2:1;
332 uint32_t clken:1; /* 31 */
333 } Bits_vdsl_mips;
334 uint32_t Reg32;
335 } BPCM_MISC_CONTROL;
336
337 typedef union {
338 struct {
339 uint32_t field;
340 } Bits_qgphy_status;
341 struct {
342 uint32_t alt_bfc_vector:12; /* 00-11 */
343 uint32_t reserved0:3;
344 uint32_t alt_bfc_en:1; /* 15 */
345 uint32_t reset_dly_cfg:2; /* 16-17 */
346 uint32_t reserved1:8;
347 uint32_t ext_mclk_en_reset:1; /* 26 */
348 uint32_t ext_mclk_en:1; /* 27 */
349 uint32_t por_reset_n_ctl:1; /* 28 */
350 uint32_t reset_n_ctl:1; /* 29 */
351 uint32_t reserved2:1;
352 uint32_t clken:1; /* 31 */
353 } Bits_vdsl_mips; /* second PHY MIPS core */
354 uint32_t Reg32;
355 } BPCM_MISC_CONTROL2;
356
357 typedef union {
358 struct {
359 uint32_t gphy_iddq_bias:1; /* 00 */
360 uint32_t gphy_ext_pwr_down:1; /* 01 */
361 uint32_t gphy_force_dll_en:1; /* 02 */
362 uint32_t gphy_iddq_global_pwr:1; /* 03 */
363 uint32_t serdes_iddq:1; /* 04 */
364 uint32_t serdes_pwrdwn:1; /* 05 */
365 uint32_t reserved0:2; /* 07:06 */
366 uint32_t serdes_refclk_sel:3; /* 10:08 */
367 uint32_t reserved1:5; /* 15:11 */
368 uint32_t pll_clk125_250_sel:1; /* 16 */
369 uint32_t pll_mux_clk_250_sel:1; /* 17 */
370 uint32_t reserved2:14; /* 31:18 */
371 } Bits;
372 uint32_t Reg32;
373 } BPCM_SGPHY_CNTL;
374
375 typedef union {
376 struct {
377 uint32_t field;
378 } Bits;
379 uint32_t Reg32;
380 } BPCM_SGPHY_STATUS;
381
382 typedef union {
383 struct {
384 uint32_t cpu_reset_n:8; // 07:00 R/W
385 uint32_t c0l2_reset:1; // 08:08 R/W
386 uint32_t c1l2_reset:1; // 09:09 R/W
387 uint32_t reserved0:6; // 15:10 R/O
388 uint32_t cpu_bpcm_init_on:8; // 23:16 R/W
389 uint32_t c0l2_bpcm_init_on:1; // 24:24 R/W
390 uint32_t c1l2_bpcm_init_on:1; // 25:25 R/W
391 uint32_t ubus_sr:1; // 26:26 R/W
392 uint32_t cci_sr:1; // 27:27 R/W
393 uint32_t webcores_sr:1; // 28:28 R/W
394 uint32_t hw_done:1; // 29:29 R/O
395 uint32_t sw_done:1; // 30:30 R/W
396 uint32_t start:1; // 31:31 R/W
397 } Bits;
398 uint32_t Reg32;
399 } ARM_CONTROL_REG;
400
401 typedef union {
402 struct {
403 uint32_t mem_pwr_ok:1; // 00:00 R/W
404 uint32_t mem_pwr_on:1; // 01:01 R/W
405 uint32_t mem_clamp_on:1; // 02:02 R/W
406 uint32_t reserved2:1; // 03:03 R/W
407 uint32_t mem_pwr_ok_status:1; // 04:04 R/O
408 uint32_t mem_pwr_on_status:1; // 05:05 R/O
409 uint32_t reserved1:2; // 07:06 R/W
410 uint32_t mem_pda:4; // 11:08 R/W only LS bit for CPU0/1, all four bits for neon_l2
411 uint32_t reserved0:3; // 14:12 R/W
412 uint32_t clamp_on:1; // 15:15 R/W
413 uint32_t pwr_ok:4; // 19:16 R/W ditto
414 uint32_t pwr_on:4; // 23:20 R/W ditto
415 uint32_t pwr_ok_status:4; // 27:24 R/O ditto
416 uint32_t pwr_on_status:4; // 31:28 R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
417 } Bits;
418 uint32_t Reg32;
419 } ARM_CPUx_PWR_CTRL_REG;
420
421 typedef union {
422 struct {
423 uint32_t resetb:1; // 00:00
424 uint32_t post_resetb:1; // 01:01
425 uint32_t pwrdwn:1; // 02:02
426 uint32_t master_reset:1; // 03:03
427 uint32_t pwrdwn_ldo:1; // 04:04
428 uint32_t iso:1; // 05:05 // only used in afepll
429 uint32_t reserved0:2; // 07:06
430 uint32_t ldo_ctrl:6; // 13:08
431 uint32_t reserved1:1; // 14:14
432 uint32_t hold_ch_all:1; // 15:15
433 uint32_t reserved2:4; // 16:19
434 uint32_t byp_wait:1; // 20:20 // only used in b15pll
435 uint32_t reserved3:11; // 21:31
436 } Bits;
437 uint32_t Reg32;
438 } PLL_CTRL_REG;
439
440 typedef union {
441 struct {
442 uint32_t fb_offset:12; // 11:00
443 uint32_t fb_phase_en:1; // 12:12
444 uint32_t _8phase_en:1; // 13:13
445 uint32_t sr:18; // 31:14
446 } Bits;
447 uint32_t Reg32;
448 } PLL_PHASE_REG;
449
450 typedef union {
451 struct {
452 uint32_t ndiv_int:10; // 09:00
453 uint32_t ndiv_frac:20; // 29:10
454 uint32_t reserved0:1; // 30
455 uint32_t ndiv_override:1; // 31
456 } Bits;
457 uint32_t Reg32;
458 } PLL_NDIV_REG;
459
460 typedef union {
461 struct {
462 uint32_t pdiv:3; // 02:00
463 uint32_t reserved0:28; // 30:03
464 uint32_t ndiv_pdiv_override:1; // 31:31
465 } Bits;
466 uint32_t Reg32;
467 } PLL_PDIV_REG;
468
469 typedef union {
470 struct {
471 uint32_t mdiv0:8; // 07:00
472 uint32_t enableb_ch0:1; // 08:08
473 uint32_t hold_ch0:1; // 09:09
474 uint32_t load_en_ch0:1; // 10:10
475 uint32_t mdel0:1; // 11:11
476 uint32_t reserved0:3; // 14:12
477 uint32_t mdiv_override0:1; // 15:15
478 uint32_t mdiv1:8; // 23:16
479 uint32_t enableb_ch1:1; // 24:24
480 uint32_t hold_ch1:1; // 25:25
481 uint32_t load_en_ch1:1; // 26:26
482 uint32_t mdel1:1; // 27:27
483 uint32_t reserved1:3; // 30:28
484 uint32_t mdiv_override1:1; // 31:31
485 } Bits;
486 uint32_t Reg32;
487 } PLL_CHCFG_REG;
488
489 typedef union {
490 struct {
491 uint32_t reserved0:4; // 03:00
492 uint32_t ka:3; // 06:04
493 uint32_t reserved1:1; // 07:07
494 uint32_t ki:3; // 10:08
495 uint32_t reserved2:1; // 11:11
496 uint32_t kp:4; // 15:12
497 uint32_t ssc_step:16; // 31:16
498 } Bits;
499 uint32_t Reg32;
500 } PLL_LOOP0_REG;
501
502 typedef union {
503 struct {
504 uint32_t ssc_limit:22; // 21:00
505 uint32_t reserved0:2; // 23:22
506 uint32_t ssc_clkdiv:4; // 27:24
507 uint32_t ssc_status:1; // 28:28
508 uint32_t reserved1:2; // 30:29
509 uint32_t ssc_mode:1; // 31:31
510 } Bits;
511 uint32_t Reg32;
512 } PLL_LOOP1_REG;
513
514 typedef union {
515 struct {
516 uint32_t fdco_ctrl_bypass:16; // 15:00
517 uint32_t fdco_bypass_en:1; // 16:16
518 uint32_t fdco_dac_sel:1; // 17:17
519 uint32_t state_reset:1; // 18:18
520 uint32_t state_mode:2; // 20:19
521 uint32_t state_sel:3; // 23:21
522 uint32_t state_update:1; // 24:24
523 uint32_t dco_en:1; // 25:25
524 uint32_t dco_div2_div4:1; // 26:26
525 uint32_t dco_bias_boost:1; // 27:27
526 uint32_t bb_en:1; // 28:28
527 uint32_t t2d_offset:3; // 31:29
528 } Bits;
529 uint32_t Reg32;
530 } PLL_CFG0_REG;
531
532 typedef union {
533 struct {
534 uint32_t t2d_offset_msb:1; // 00:00
535 uint32_t t2d_clk_enable:1; // 01:01
536 uint32_t t2d_clk_sel:1; // 02:02
537 uint32_t kpp:4; // 06:03
538 uint32_t pwm_ctrl:2; // 08:07
539 uint32_t port_reset_mode:2; // 10:09
540 uint32_t byp2_en:1; // 11:11
541 uint32_t byp1_en:1; // 12:12
542 uint32_t ref_diff_sel:1; // 13:13
543 uint32_t ki_startlow:1; // 14:14
544 uint32_t en_500ohm:1; // 15:15
545 uint32_t refd2c_bias:3; // 18:16
546 uint32_t post_div2_div3:1; // 19:19
547 uint32_t ki_boost:1; // 20:20
548 uint32_t reserved0:11; // 31:21
549 } Bits;
550 uint32_t Reg32;
551 } PLL_CFG1_REG;
552
553 typedef union {
554 struct {
555 uint32_t en_cml:3; // 02:00
556 uint32_t tri_en:1; // 03:03
557 uint32_t test_sel:3; // 06:04
558 uint32_t test_en:1; // 07:07
559 uint32_t reserved0:24;
560 } Bits;
561 uint32_t Reg32;
562 } PLL_OCTRL_REG;
563
564 typedef union {
565 struct {
566 uint32_t out:12; // 11:00
567 uint32_t reserved:19; // 30:12
568 uint32_t lock:1; // 31:31
569 } Bits;
570 uint32_t Reg32;
571 } PLL_STAT_REG;
572
573 typedef union {
574 struct {
575 uint32_t ndiv_int:10; // 09:00
576 uint32_t reserved0:2; // 11:10
577 uint32_t ndiv_frac:20; // 31:12
578 } Bits;
579 uint32_t Reg32;
580 } PLL_DECNDIV_REG;
581
582 typedef union {
583 struct {
584 uint32_t pdiv:4; // 03:00
585 uint32_t reserved0:12; // 15:04
586 uint32_t mdiv0:8; // 23:16
587 uint32_t mdiv1:8; // 31:24
588 } Bits;
589 uint32_t Reg32;
590 } PLL_DECPDIV_REG;
591
592 typedef union {
593 struct {
594 uint32_t mdiv2:8; // 07:00
595 uint32_t mdiv3:8; // 15:08
596 uint32_t mdiv4:8; // 23:16
597 uint32_t mdiv5:8; // 31:24
598 } Bits;
599 uint32_t Reg32;
600 } PLL_DECCH25_REG;
601
602 typedef union {
603 struct {
604 uint32_t manual_clk_en:1;
605 uint32_t manual_reset_ctl:1;
606 uint32_t freq_scale_used:1; // R/O
607 uint32_t dpg_capable:1; // R/O
608 uint32_t manual_mem_pwr:2;
609 uint32_t manual_iso_ctl:1;
610 uint32_t manual_ctl:1;
611 uint32_t dpg_ctl_en:1;
612 uint32_t pwr_dn_req:1;
613 uint32_t pwr_up_req:1;
614 uint32_t mem_pwr_ctl_en:1;
615 uint32_t blk_reset_assert:1;
616 uint32_t mem_stby:1;
617 uint32_t reserved:5;
618 uint32_t pwr_cntl_state:5;
619 uint32_t freq_scalar_dyn_sel:1; // R/O
620 uint32_t pwr_off_state:1; // R/O
621 uint32_t pwr_on_state:1; // R/O
622 uint32_t pwr_good:1; // R/O
623 uint32_t dpg_pwr_state:1; // R/O
624 uint32_t mem_pwr_state:1; // R/O
625 uint32_t iso_state:1; // R/O
626 uint32_t reset_state:1; // R/O
627 } Bits;
628 uint32_t Reg32;
629 } BPCM_PWR_ZONE_N_CONTROL;
630
631 typedef union {
632 struct {
633 uint32_t pwr_ok_delay_sel:3;
634 uint32_t pwk_ok_thresh:2;
635 uint32_t reserved:3;
636 uint32_t iso_on_delay:4;
637 uint32_t iso_off_delay:4;
638 uint32_t clock_on_delay:4;
639 uint32_t clock_off_delay:4;
640 uint32_t reset_on_delay:4;
641 uint32_t reset_off_delay:4;
642 } Bits;
643 uint32_t Reg32;
644 } BPCM_PWR_ZONE_N_CONFIG1;
645
646 typedef union {
647 struct {
648 uint32_t delay_prescale_sel:3;
649 uint32_t slew_prescale_sel:3;
650 uint32_t reserved:6;
651 uint32_t dpgn_on_delay:4;
652 uint32_t dpg1_on_delay:4;
653 uint32_t dpg_off_delay:4;
654 uint32_t mem_on_delay:4;
655 uint32_t mem_off_delay:4;
656 } Bits;
657 uint32_t Reg32;
658 } BPCM_PWR_ZONE_N_CONFIG2;
659
660 typedef union {
661 struct {
662 uint32_t fs_bypass_en:1;
663 uint32_t gear_sel:1;
664 uint32_t use_dyn_gear_sel:1;
665 uint32_t reserved2:1;
666 uint32_t low_gear_div:3;
667 uint32_t high_gear_div:3;
668 uint32_t reserved:22;
669 } Bits;
670 uint32_t Reg32;
671 } BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
672
673 typedef struct {
674 BPCM_PWR_ZONE_N_CONTROL control;
675 BPCM_PWR_ZONE_N_CONFIG1 config1;
676 BPCM_PWR_ZONE_N_CONFIG2 config2;
677 BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
678 } BPCM_ZONE;
679
680 #define BPCMZoneOffset(reg) offsetof(BPCM_ZONE,reg)
681 #define BPCMZoneRegOffset(reg) (BPCMZoneOffset(reg) >> 2)
682
683 typedef union {
684 struct {
685 uint32_t pmb_Addr:8;
686 uint32_t hw_rev:8;
687 uint32_t module_id:16;
688 } Bits;
689 uint32_t Reg32;
690 } BPCM_UBUS_ID_REG;
691
692 typedef union {
693 struct {
694 uint32_t num_zones:8;
695 uint32_t sr_reg_bits:8;
696 uint32_t pllType:2;
697 uint32_t reserved0:1;
698 uint32_t ubus:1;
699 uint32_t reserved1:12;
700 } Bits;
701 uint32_t Reg32;
702 } BPCM_UBUS_CAPABILITES_REG;
703
704 typedef union {
705 struct {
706 uint32_t ctrl_eswap:4;
707 uint32_t reserved0:4;
708 uint32_t ctrl_cd:4;
709 uint32_t reserved1:4;
710 uint32_t ctrl_seclev:8;
711 uint32_t reqout_seclev:8;
712 } Bits;
713 uint32_t Reg32;
714 } BPCM_UBUS_CTRL_REG;
715
716 typedef union {
717 struct {
718 uint64_t addr_in:24;
719 uint64_t addr_out:24;
720 uint64_t pid:8;
721 uint64_t size:5;
722 uint64_t cmddta:1;
723 uint64_t en:2;
724 } Bits;
725 struct {
726 uint32_t word0;
727 uint32_t word1;
728 } Regs32;
729 uint64_t Reg64;
730 } BPCM_UBUS_CFG_REG;
731
732 // There is a 20-bit address used to access any given BPCM register. The upper 8-bits
733 // is the device address and the lower 12-bits is used to represent the BPCM register
734 // set for that device. 32-bit registers are allocated on 4-byte boundaries
735 // (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
736 // Thus, to get the actual address of any given register within the device's address
737 // space, I'll use the "C" offsetof macro and divide the result by 4
738 // e.g.:
739 // int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL); // yields the byte offset of the target register
740 // int regAddress = regOffset/4; // yields the 32-bit word offset of the target register
741 // The ReadBPCMReg and WriteBPCMReg functions will always take a device address
742 // (address of the BPCM device) and register offset (like regOffset above). The offset
743 // will be divided by 4 and used as the lower 12-bits of the actual target address, while the
744 // device address will serve as the upper 8-bits of the actual address.
745 typedef struct {
746 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
747 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
748 uint32_t control; // offset = 0x08, actual offset = 2
749 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
750 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
751 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
752 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
753 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
754 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
755 BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9
756 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
757 uint32_t reserved; // offset = 0x2c, actual offset = 11
758 BPCM_GLOBAL_CNTL_0 global_control; // offset = 0x30, actual offset = 12
759 BPCM_GLOBAL_CNTL_1 global_control_1; // offset = 0x34, actual offset = 13
760 BPCM_GLOBAL_CNTL_2 global_control_2; // offset = 0x38, actual offset = 14
761 uint32_t global_status; // offset = 0x3c, actual offset = 15
762 BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
763 } BPCM_REGS; // total offset space = 4096
764
765 #define BPCMOffset(reg) offsetof(BPCM_REGS,reg)
766 #define BPCMRegOffset(reg) (BPCMOffset(reg) >> 2)
767
768
769 typedef struct {
770 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
771 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
772 uint32_t control; // offset = 0x08, actual offset = 2
773 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
774 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
775 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
776 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
777 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
778 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
779 BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9
780 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
781 BPCM_GLOBAL_CNTL global_control; // offset = 0x2c, actual offset = 11
782 BPCM_MISC_CONTROL misc_control; // offset = 0x30, actual offset = 12
783 BPCM_MISC_CONTROL2 misc_control2; // offset = 0x34, actual offset = 13
784 uint32_t rvrsd[2];
785 BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
786 } BPCM_VDSL_REGS; // total offset space = 4096
787
788 #define BPCMVDSLOffset(reg) offsetof(BPCM_VDSL_REGS,reg)
789 #define BPCMVDSLRegOffset(reg) (BPCMVDSLOffset(reg) >> 2)
790
791 // ARM BPCM addresses as used by 63138/63148 and possibly others (28nm)
792 typedef struct {
793 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
794 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
795 uint32_t control; // offset = 0x08, actual offset = 2
796 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
797 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
798 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
799 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
800 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
801 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
802 BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9
803 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
804 uint32_t reserved; // offset = 0x2c, actual offset = 11
805 ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12
806 BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
807 } ARM_BPCM_REGS;
808 #define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg)
809 #define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2)
810
811 typedef struct {
812 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
813 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
814 uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3
815 PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4
816 PLL_CFG0_REG cfg0; // offset = 0x14, actual offset = 5
817 PLL_CFG1_REG cfg1; // offset = 0x18, actual offset = 6
818 PLL_NDIV_REG ndiv; // offset = 0x1c, actual offset = 7
819 PLL_PDIV_REG pdiv; // offset = 0x20, actual offset = 8
820 PLL_LOOP0_REG loop0; // offset = 0x24, actual offset = 9
821 PLL_LOOP1_REG loop1; // offset = 0x28, actual offset = a
822 PLL_CHCFG_REG ch01_cfg; // offset = 0x2c, actual offset = b
823 PLL_CHCFG_REG ch23_cfg; // offset = 0x30, actual offset = c
824 PLL_CHCFG_REG ch45_cfg; // offset = 0x34, actual offset = d
825 PLL_OCTRL_REG octrl; // offset = 0x38, actual offset = e
826 PLL_STAT_REG stat; // offset = 0x3c, actual offset = f
827 uint32_t strap; // offset = 0x40, actual offset = 0x10
828 uint32_t decndiv; // offset = 0x44, actual offset = 0x11
829 uint32_t decpdiv; // offset = 0x48, actual offset = 0x12
830 uint32_t decch25; // offset = 0x4c, actual offset = 0x13
831 } PLL_BPCM_REGS;
832
833 #define PLLBPCMOffset(reg) offsetof(PLL_BPCM_REGS,reg)
834 #define PLLBPCMRegOffset(reg) (PLLBPCMOffset(reg) >> 2)
835
836 typedef struct {
837 BPCM_UBUS_ID_REG id_reg; /* offset = 0x00, actual offset = 0 */
838 BPCM_UBUS_CAPABILITES_REG capabilities; /* offset = 0x04, actual offset = 1 */
839 uint32_t reserved0; /* offset = 0x08, actual offset = 2 */
840 BPCM_UBUS_CTRL_REG ctrl; /* offset = 0x0c, actual offset = 3 */
841 BPCM_UBUS_CFG_REG cfg[4]; /* offset = 0x10..0x2c, actual offset = 4..11 */
842 } BPCM_UBUS_REG;
843
844 #define UBUSBPCMOffset(reg) offsetof(BPCM_UBUS_REG,reg)
845 #define UBUSBPCMRegOffset(reg) (UBUSBPCMOffset(reg) >> 2)
846
847 typedef struct {
848 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
849 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
850 uint32_t control; // offset = 0x08, actual offset = 2
851 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
852 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
853 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
854 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
855 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
856 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
857 uint32_t reserved0; // offset = 0x24, actual offset = 9
858 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
859 uint32_t reserved1; // offset = 0x2c, actual offset = 11
860 uint32_t clkrst_cfg; // offset = 0x30, actual offset = 12
861 uint32_t clkrst_control; // offset = 0x34, actual offset = 13
862 uint32_t xtal_control; // offset = 0x38, actual offset = 14
863 uint32_t clkrst_stat; // offset = 0x3c, actual offset = 15
864 } BPCM_CLKRST_REGS;
865
866 #define CLKRSTBPCMOffset(reg) offsetof(BPCM_CLKRST_REGS, reg)
867 #define CLKRSTBPCMRegOffset(reg) (CLKRSTBPCMOffset(reg) >> 2)
868
869 // *************************** macros ******************************
870 #ifndef offsetof
871 #define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
872 #endif
873
874 #endif
Broadcom-s U-Boot