arch/arm/include/asm/arch-bcm63158/misc.h

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  *
   3  *  Copyright 2019 Broadcom Ltd.
   4  */
   5
   6 #ifndef _63158_MISC_H
   7 #define _63158_MISC_H
   8
   9 #define MISC_BASE          0xff802600
  10
  11 /*
  12  * Misc Register Set Definitions.
  13  */
  14 typedef struct Misc {
  15    uint32_t miscStrapBus; /* 0x00 */
  16
  17     /* boot select bits 3-5 */
  18 #define BOOT_SEL_STRAP_NAND_2K_PAGE             0x00
  19 #define BOOT_SEL_STRAP_NAND_4K_PAGE             0x08
  20 #define BOOT_SEL_STRAP_NAND_8K_PAGE             0x10
  21 #define BOOT_SEL_STRAP_NAND_512B_PAGE           0x18
  22 #define BOOT_SEL_STRAP_SPI_NOR                  0x38
  23 #define BOOT_SEL_STRAP_EMMC                     0x30
  24 #define BOOT_SEL_STRAP_SPI_NAND                 0x28
  25
  26 #define BOOT_SEL_STRAP_BOOT_SEL_MASK            (0x38)
  27 #define BOOT_SEL_STRAP_PAGE_SIZE_MASK           (0x7)
  28
  29 #define MISC_STRAP_BUS_BOOT_SEL_SHIFT           0
  30 #define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  31 #define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  32 #define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  33 #define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  34 #define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  35 #define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  36 #define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  37 #define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  38 #define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  39 #define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  40 #define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  41 #define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  42 #define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  43 #define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  44 #define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  45 #define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  46 #define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  47 #define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  48 #define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  49 #define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  50 #define MISC_STRAP_BUS_B53_BOOT_N               (0x1 << 6)
  51 #define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 7)
  52 #define MISC_STRAP_BUS_BOOROM_BOOT_N            MISC_STRAP_BUS_BOOTROM_BOOT_N
  53 #define MISC_STRAP_BUS_LS_SPI_SLAVE_DISABLE     (0x1 << 8)
  54 #define MISC_STRAP_BUS_PCIE_SATA_MASK           (0x1 << 11)  /* 1-PCIe2 0-SATAB */
  55 #define MISC_STRAP_BUS_PCIE0_RC_MODE            (0x1 << 12)
  56 #define MISC_STRAP_BUS_RESET_OUT_DELAY          (0x1 << 13)
  57 #define MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT      15
  58 #define MISC_STRAP_BUS_CPU_SLOW_FREQ            (0x1 << MISC_STRAP_BUS_CPU_SLOW_FREQ_SHIFT)
  59 #define MISC_STRAP_BUS_SW_RESERVE_MASK          (0x1f << 16)
  60    uint32_t miscStrapOverride;     /* 0x04 */
  61    uint32_t miscMaskUBUSErr;       /* 0x08 */
  62    uint32_t miscPeriphCtrl;        /* 0x0c */
  63    uint32_t miscSpiMasterCtrl;     /* 0x10 */
  64    uint32_t reserved0;             /* 0x14 */
  65    uint32_t miscPeriphMiscCtrl;    /* 0x18 */
  66    uint32_t miscPeriphMiscStat;    /* 0x1c */
  67    uint32_t miscSoftResetB;        /* 0x20 */
  68    uint32_t miscSpare0;            /* 0x24 */
  69    uint32_t miscSWdebugNW[2];      /* 0x28 */
  70    uint32_t miscWDResetCtrl;       /* 0x30 */
  71 } Misc;
  72
  73 #define MISC ((volatile Misc * const) MISC_BASE)
  74
  75 #define DUAL_CORE_63152 0x63152
  76
  77 // PERF
  78 typedef struct PerfControl { /* GenInt */
  79      uint32_t        RevID;             /* (00) word 0 */
  80 #define CHIP_ID_SHIFT   12
  81 #define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
  82 #define REV_ID_MASK     0xff
  83 } PerfControl;
  84
  85 #define PERF_BASE              0xff800000
  86 #define PERF ((volatile PerfControl * const) PERF_BASE)
  87
  88 #endif