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Add Broadcom / Netgear changes from RAXE 1.0.0.48
[project/bcm63xx/u-boot.git] / arch / arm / include / asm / arch-bcm6756 / BPCM.h
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2013 Broadcom
4 */
5 /*
6
7 */
8
9 #ifndef BPCM_H
10 #define BPCM_H
11
12 typedef union {
13 struct {
14 uint32_t pmb_Addr:8;
15 uint32_t hw_rev:8;
16 uint32_t sw_strap:16;
17 } Bits;
18 uint32_t Reg32;
19 } BPCM_ID_REG;
20
21 // types of PMB devices
22 enum {
23 kPMB_BPCM = 0,
24 kPMB_MIPS_PLL = 1,
25 kPMB_GEN_PLL = 2,
26 kPMB_LC_PLL = 3,
27 // 4..15 reserved
28 };
29
30 typedef union {
31 struct {
32 uint32_t num_zones:8;
33 uint32_t num_sr_bits:8;
34 uint32_t devType:4; // see enum above
35 uint32_t reserved1:12;
36 } Bits;
37 uint32_t Reg32;
38 } BPCM_CAPABILITES_REG;
39
40 typedef union {
41 struct {
42 uint32_t pwd_alert:1;
43 uint32_t reserved:31;
44 } Bits;
45 uint32_t Reg32;
46 } BPCM_STATUS_REG;
47
48 typedef union {
49 struct {
50 uint32_t ro_en_s:1;
51 uint32_t ro_en_h:1;
52 uint32_t ectr_en_s:1;
53 uint32_t ectr_en_h:1;
54 uint32_t thresh_en_s:1;
55 uint32_t thresh_en_h:1;
56 uint32_t continuous_s:1;
57 uint32_t continuous_h:1;
58 uint32_t reserved:4;
59 uint32_t valid_s:1;
60 uint32_t alert_s:1;
61 uint32_t valid_h:1;
62 uint32_t alert_h:1;
63 uint32_t interval:16;
64 } Bits;
65 uint32_t Reg32;
66 } BPCM_AVS_ROSC_CONTROL_REG;
67
68 typedef union {
69 struct {
70 uint32_t thresh_lo:16;
71 uint32_t thresh_hi:16;
72 } Bits;
73 uint32_t Reg32;
74 } BPCM_AVS_ROSC_THRESHOLD;
75
76 typedef union {
77 struct {
78 uint32_t count_s:16;
79 uint32_t count_h:16;
80 } Bits;
81 uint32_t Reg32;
82 } BPCM_AVS_ROSC_COUNT;
83
84 typedef union {
85 struct {
86 uint32_t pwd_en:1;
87 uint32_t pwd_alert_sel:1;
88 uint32_t start:6;
89 uint32_t pwd_tm_en:1;
90 uint32_t reserved2:6;
91 uint32_t alert:1;
92 uint32_t ccfg:8;
93 uint32_t rsel:3;
94 uint32_t clr_cfg:3;
95 uint32_t reserved1:2;
96 } Bits;
97 uint32_t Reg32;
98 } BPCM_AVS_PWD_CONTROL;
99
100 typedef union {
101 struct {
102 uint32_t tbd:32;
103 } Bits;
104 uint32_t Reg32;
105 } BPCM_PWD_ACCUM_CONTROL;
106
107 typedef union {
108 struct {
109 uint32_t sr:8;
110 uint32_t gp:24;
111 } Bits;
112 uint32_t Reg32;
113 } BPCM_SR_CONTROL;
114
115 typedef union{
116 struct {
117 uint32_t tbd:32;
118 } Bits;
119 uint32_t Reg32;
120 struct {
121 uint32_t vdsl_arm_por_reset_n:1;
122 uint32_t vdsl_arm_reset_n:1;
123 uint32_t vdsl_arm_debug_reset_n:1;
124 uint32_t vdsl_arm_l2_reset_n:1;
125 uint32_t vdsl_arm_cdbgrstreq_en:1;
126 uint32_t vdsl_arm_niden_a7_b0:1;
127 uint32_t vdsl_arm_spniden_a7_b0:1;
128 uint32_t vdsl_arm_nsocdbgreset_a7:1;
129 uint32_t axi4_ubus4_pass_through_disable:1;
130 uint32_t vdsl_arm_dbgen_a7_b0:1;
131 uint32_t vdsl_arm_spiden_a7_b0:1;
132 uint32_t vdsl_arm_scratch_reg:21;
133 } Bits_vdsl;
134 } BPCM_VDSL_ARM_RST_CTL;
135
136 typedef union {
137 struct {
138 uint32_t tbd:32;
139 } Bits;
140 uint32_t Reg32;
141 } BPCM_GLOBAL_CNTL;
142
143 typedef union {
144 struct {
145 uint32_t ctl;
146 } Bits_sata_gp;
147 struct {
148 uint32_t iddq_bias:1; /* 0 */
149 uint32_t ext_pwr_down:4; /* 1-4 */
150 uint32_t force_dll_en:1; /* 5 */
151 uint32_t iddq_global_pwr:1; /* 6 */
152 uint32_t reserved:25;
153 } Bits_switch_z1_qgphy;
154 struct {
155 uint32_t iddq_bias:1; /* 0 */
156 uint32_t ext_pwr_down:1; /* 1 */
157 uint32_t force_dll_en:1; /* 2 */
158 uint32_t iddq_global_pwd:1; /* 3 */
159 uint32_t ck25_dis:1; /* 4 */
160 uint32_t phy_reset:1; /* 5 */
161 uint32_t reserved0:2;
162 uint32_t phy_ad:5; /* 8-12 */
163 uint32_t reserved1:18;
164 uint32_t ctrl_en:1; /* 31 */
165 } Bits_egphy_1port;
166 struct {
167 uint32_t iddq_bias:1; /* 0 */
168 uint32_t ext_pwr_down:4; /* 1-4 */
169 uint32_t force_dll_en:1; /* 5 */
170 uint32_t iddq_global_pwd:1; /* 6 */
171 uint32_t ck25_dis:1; /* 7 */
172 uint32_t phy_reset:1; /* 8 */
173 uint32_t reserved0:3;
174 uint32_t phy_ad:5; /* 12-16 */
175 uint32_t reserved1:14;
176 uint32_t ctrl_en:1; /* 31 */
177 } Bits_egphy_4port;
178 struct {
179 uint32_t iddq_bias:1; /* 0 */
180 uint32_t ext_pwr_down:4; /* 1-4 */
181 uint32_t force_dll_en:1; /* 5 */
182 uint32_t iddq_global_pwr:1; /* 6 */
183 uint32_t reserved0:25; /* 7-31 */
184 } Bits_qgphy_cntl;
185 struct {
186 uint32_t ctl;
187 } Bits_vdsl_phy;
188 struct {
189 uint32_t alt_bfc_vector:12; /* 00-11 */
190 uint32_t reserved0:3;
191 uint32_t alt_bfc_en:1; /* 15 */
192 uint32_t reset_dly_cfg:2; /* 16-17 */
193 uint32_t reserved1:8;
194 uint32_t ext_mclk_en_reset:1; /* 26 */
195 uint32_t ext_mclk_en:1; /* 27 */
196 uint32_t por_reset_n_ctl:1; /* 28 */
197 uint32_t reset_n_ctl:1; /* 29 */
198 uint32_t reserved2:1;
199 uint32_t clken:1; /* 31 */
200 } Bits_vdsl_mips;
201 uint32_t Reg32;
202 } BPCM_MISC_CONTROL;
203
204 typedef union {
205 struct {
206 uint32_t field;
207 } Bits_qgphy_status;
208 struct {
209 uint32_t alt_bfc_vector:12; /* 00-11 */
210 uint32_t reserved0:3;
211 uint32_t alt_bfc_en:1; /* 15 */
212 uint32_t reset_dly_cfg:2; /* 16-17 */
213 uint32_t reserved1:8;
214 uint32_t ext_mclk_en_reset:1; /* 26 */
215 uint32_t ext_mclk_en:1; /* 27 */
216 uint32_t por_reset_n_ctl:1; /* 28 */
217 uint32_t reset_n_ctl:1; /* 29 */
218 uint32_t reserved2:1;
219 uint32_t clken:1; /* 31 */
220 } Bits_vdsl_mips; /* second PHY MIPS core */
221 uint32_t Reg32;
222 } BPCM_MISC_CONTROL2;
223
224 typedef union {
225 struct {
226 uint32_t gphy_iddq_bias:1; /* 00 */
227 uint32_t gphy_ext_pwr_down:1; /* 01 */
228 uint32_t gphy_force_dll_en:1; /* 02 */
229 uint32_t gphy_iddq_global_pwr:1; /* 03 */
230 uint32_t serdes_iddq:1; /* 04 */
231 uint32_t serdes_pwrdwn:1; /* 05 */
232 uint32_t reserved0:2; /* 07:06 */
233 uint32_t serdes_refclk_sel:3; /* 10:08 */
234 uint32_t reserved1:5; /* 15:11 */
235 uint32_t pll_clk125_250_sel:1; /* 16 */
236 uint32_t pll_mux_clk_250_sel:1; /* 17 */
237 uint32_t reserved2:14; /* 31:18 */
238 } Bits;
239 uint32_t Reg32;
240 } BPCM_SGPHY_CNTL;
241
242 typedef union {
243 struct {
244 uint32_t field;
245 } Bits;
246 uint32_t Reg32;
247 } BPCM_SGPHY_STATUS;
248
249 typedef union {
250 struct {
251 uint32_t cpu_reset_n:8; // 07:00 R/W
252 uint32_t c0l2_reset:1; // 08:08 R/W
253 uint32_t c1l2_reset:1; // 09:09 R/W
254 uint32_t reserved0:6; // 15:10 R/O
255 uint32_t cpu_bpcm_init_on:8; // 23:16 R/W
256 uint32_t c0l2_bpcm_init_on:1; // 24:24 R/W
257 uint32_t c1l2_bpcm_init_on:1; // 25:25 R/W
258 uint32_t ubus_sr:1; // 26:26 R/W
259 uint32_t cci_sr:1; // 27:27 R/W
260 uint32_t webcores_sr:1; // 28:28 R/W
261 uint32_t hw_done:1; // 29:29 R/O
262 uint32_t sw_done:1; // 30:30 R/W
263 uint32_t start:1; // 31:31 R/W
264 } Bits;
265 uint32_t Reg32;
266 } ARM_CONTROL_REG;
267
268 typedef union {
269 struct {
270 uint32_t mem_pwr_ok:1; // 00:00 R/W
271 uint32_t mem_pwr_on:1; // 01:01 R/W
272 uint32_t mem_clamp_on:1; // 02:02 R/W
273 uint32_t reserved2:1; // 03:03 R/W
274 uint32_t mem_pwr_ok_status:1; // 04:04 R/O
275 uint32_t mem_pwr_on_status:1; // 05:05 R/O
276 uint32_t reserved1:2; // 07:06 R/W
277 uint32_t mem_pda:4; // 11:08 R/W only LS bit for CPU0/1, all four bits for neon_l2
278 uint32_t reserved0:3; // 14:12 R/W
279 uint32_t clamp_on:1; // 15:15 R/W
280 uint32_t pwr_ok:4; // 19:16 R/W ditto
281 uint32_t pwr_on:4; // 23:20 R/W ditto
282 uint32_t pwr_ok_status:4; // 27:24 R/O ditto
283 uint32_t pwr_on_status:4; // 31:28 R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2
284 } Bits;
285 uint32_t Reg32;
286 } ARM_CPUx_PWR_CTRL_REG;
287
288 typedef union {
289 struct {
290 uint32_t resetb:1; // 00:00
291 uint32_t post_resetb:1; // 01:01
292 uint32_t pwrdwn:1; // 02:02
293 uint32_t master_reset:1; // 03:03
294 uint32_t pwrdwn_ldo:1; // 04:04
295 uint32_t iso:1; // 05:05 // only used in afepll
296 uint32_t reserved0:2; // 07:06
297 uint32_t ldo_ctrl:6; // 13:08
298 uint32_t reserved1:1; // 14:14
299 uint32_t hold_ch_all:1; // 15:15
300 uint32_t reserved2:4; // 16:19
301 uint32_t byp_wait:1; // 20:20 // only used in b15pll
302 uint32_t reserved3:11; // 21:31
303 } Bits;
304 uint32_t Reg32;
305 } PLL_CTRL_REG;
306
307 typedef union {
308 struct {
309 uint32_t fb_offset:12; // 11:00
310 uint32_t fb_phase_en:1; // 12:12
311 uint32_t _8phase_en:1; // 13:13
312 uint32_t sr:18; // 31:14
313 } Bits;
314 uint32_t Reg32;
315 } PLL_PHASE_REG;
316
317 typedef union {
318 struct {
319 uint32_t ndiv_int:10; // 09:00
320 uint32_t ndiv_frac:20; // 29:10
321 uint32_t reserved0:1; // 30
322 uint32_t ndiv_override:1; // 31
323 } Bits;
324 uint32_t Reg32;
325 } PLL_NDIV_REG;
326
327 typedef union {
328 struct {
329 uint32_t pdiv:3; // 02:00
330 uint32_t reserved0:28; // 30:03
331 uint32_t ndiv_pdiv_override:1; // 31:31
332 } Bits;
333 uint32_t Reg32;
334 } PLL_PDIV_REG;
335
336 typedef union {
337 struct {
338 uint32_t mdiv0:8; // 07:00
339 uint32_t enableb_ch0:1; // 08:08
340 uint32_t hold_ch0:1; // 09:09
341 uint32_t load_en_ch0:1; // 10:10
342 uint32_t mdel0:1; // 11:11
343 uint32_t reserved0:3; // 14:12
344 uint32_t mdiv_override0:1; // 15:15
345 uint32_t mdiv1:8; // 23:16
346 uint32_t enableb_ch1:1; // 24:24
347 uint32_t hold_ch1:1; // 25:25
348 uint32_t load_en_ch1:1; // 26:26
349 uint32_t mdel1:1; // 27:27
350 uint32_t reserved1:3; // 30:28
351 uint32_t mdiv_override1:1; // 31:31
352 } Bits;
353 uint32_t Reg32;
354 } PLL_CHCFG_REG;
355
356 typedef union {
357 struct {
358 uint32_t reserved0:4; // 03:00
359 uint32_t ka:3; // 06:04
360 uint32_t reserved1:1; // 07:07
361 uint32_t ki:3; // 10:08
362 uint32_t reserved2:1; // 11:11
363 uint32_t kp:4; // 15:12
364 uint32_t ssc_step:16; // 31:16
365 } Bits;
366 uint32_t Reg32;
367 } PLL_LOOP0_REG;
368
369 typedef union {
370 struct {
371 uint32_t ssc_limit:22; // 21:00
372 uint32_t reserved0:2; // 23:22
373 uint32_t ssc_clkdiv:4; // 27:24
374 uint32_t ssc_status:1; // 28:28
375 uint32_t reserved1:2; // 30:29
376 uint32_t ssc_mode:1; // 31:31
377 } Bits;
378 uint32_t Reg32;
379 } PLL_LOOP1_REG;
380
381 typedef union {
382 struct {
383 uint32_t fdco_ctrl_bypass:16; // 15:00
384 uint32_t fdco_bypass_en:1; // 16:16
385 uint32_t fdco_dac_sel:1; // 17:17
386 uint32_t state_reset:1; // 18:18
387 uint32_t state_mode:2; // 20:19
388 uint32_t state_sel:3; // 23:21
389 uint32_t state_update:1; // 24:24
390 uint32_t dco_en:1; // 25:25
391 uint32_t dco_div2_div4:1; // 26:26
392 uint32_t dco_bias_boost:1; // 27:27
393 uint32_t bb_en:1; // 28:28
394 uint32_t t2d_offset:3; // 31:29
395 } Bits;
396 uint32_t Reg32;
397 } PLL_CFG0_REG;
398
399 typedef union {
400 struct {
401 uint32_t t2d_offset_msb:1; // 00:00
402 uint32_t t2d_clk_enable:1; // 01:01
403 uint32_t t2d_clk_sel:1; // 02:02
404 uint32_t kpp:4; // 06:03
405 uint32_t pwm_ctrl:2; // 08:07
406 uint32_t port_reset_mode:2; // 10:09
407 uint32_t byp2_en:1; // 11:11
408 uint32_t byp1_en:1; // 12:12
409 uint32_t ref_diff_sel:1; // 13:13
410 uint32_t ki_startlow:1; // 14:14
411 uint32_t en_500ohm:1; // 15:15
412 uint32_t refd2c_bias:3; // 18:16
413 uint32_t post_div2_div3:1; // 19:19
414 uint32_t ki_boost:1; // 20:20
415 uint32_t reserved0:11; // 31:21
416 } Bits;
417 uint32_t Reg32;
418 } PLL_CFG1_REG;
419
420 typedef union {
421 struct {
422 uint32_t en_cml:3; // 02:00
423 uint32_t tri_en:1; // 03:03
424 uint32_t test_sel:3; // 06:04
425 uint32_t test_en:1; // 07:07
426 uint32_t reserved0:24;
427 } Bits;
428 uint32_t Reg32;
429 } PLL_OCTRL_REG;
430
431 typedef union {
432 struct {
433 uint32_t out:12; // 11:00
434 uint32_t reserved:19; // 30:12
435 uint32_t lock:1; // 31:31
436 } Bits;
437 uint32_t Reg32;
438 } PLL_STAT_REG;
439
440 typedef union {
441 struct {
442 uint32_t ndiv_int:10; // 09:00
443 uint32_t reserved0:2; // 11:10
444 uint32_t ndiv_frac:20; // 31:12
445 } Bits;
446 uint32_t Reg32;
447 } PLL_DECNDIV_REG;
448
449 typedef union {
450 struct {
451 uint32_t pdiv:4; // 03:00
452 uint32_t reserved0:12; // 15:04
453 uint32_t mdiv0:8; // 23:16
454 uint32_t mdiv1:8; // 31:24
455 } Bits;
456 uint32_t Reg32;
457 } PLL_DECPDIV_REG;
458
459 typedef union {
460 struct {
461 uint32_t mdiv2:8; // 07:00
462 uint32_t mdiv3:8; // 15:08
463 uint32_t mdiv4:8; // 23:16
464 uint32_t mdiv5:8; // 31:24
465 } Bits;
466 uint32_t Reg32;
467 } PLL_DECCH25_REG;
468
469 typedef union {
470 struct {
471 uint32_t manual_clk_en:1;
472 uint32_t manual_reset_ctl:1;
473 uint32_t freq_scale_used:1; // R/O
474 uint32_t dpg_capable:1; // R/O
475 uint32_t manual_mem_pwr:2;
476 uint32_t manual_iso_ctl:1;
477 uint32_t manual_ctl:1;
478 uint32_t dpg_ctl_en:1;
479 uint32_t pwr_dn_req:1;
480 uint32_t pwr_up_req:1;
481 uint32_t mem_pwr_ctl_en:1;
482 uint32_t blk_reset_assert:1;
483 uint32_t mem_stby:1;
484 uint32_t reserved:5;
485 uint32_t pwr_cntl_state:5;
486 uint32_t freq_scalar_dyn_sel:1; // R/O
487 uint32_t pwr_off_state:1; // R/O
488 uint32_t pwr_on_state:1; // R/O
489 uint32_t pwr_good:1; // R/O
490 uint32_t dpg_pwr_state:1; // R/O
491 uint32_t mem_pwr_state:1; // R/O
492 uint32_t iso_state:1; // R/O
493 uint32_t reset_state:1; // R/O
494 } Bits;
495 uint32_t Reg32;
496 } BPCM_PWR_ZONE_N_CONTROL;
497
498 typedef union {
499 struct {
500 uint32_t pwr_ok_delay_sel:3;
501 uint32_t pwk_ok_thresh:2;
502 uint32_t reserved:3;
503 uint32_t iso_on_delay:4;
504 uint32_t iso_off_delay:4;
505 uint32_t clock_on_delay:4;
506 uint32_t clock_off_delay:4;
507 uint32_t reset_on_delay:4;
508 uint32_t reset_off_delay:4;
509 } Bits;
510 uint32_t Reg32;
511 } BPCM_PWR_ZONE_N_CONFIG1;
512
513 typedef union {
514 struct {
515 uint32_t delay_prescale_sel:3;
516 uint32_t slew_prescale_sel:3;
517 uint32_t reserved:6;
518 uint32_t dpgn_on_delay:4;
519 uint32_t dpg1_on_delay:4;
520 uint32_t dpg_off_delay:4;
521 uint32_t mem_on_delay:4;
522 uint32_t mem_off_delay:4;
523 } Bits;
524 uint32_t Reg32;
525 } BPCM_PWR_ZONE_N_CONFIG2;
526
527 typedef union {
528 struct {
529 uint32_t fs_bypass_en:1;
530 uint32_t gear_sel:1;
531 uint32_t use_dyn_gear_sel:1;
532 uint32_t reserved2:1;
533 uint32_t low_gear_div:3;
534 uint32_t high_gear_div:3;
535 uint32_t reserved:22;
536 } Bits;
537 uint32_t Reg32;
538 } BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
539
540 typedef struct {
541 BPCM_PWR_ZONE_N_CONTROL control;
542 BPCM_PWR_ZONE_N_CONFIG1 config1;
543 BPCM_PWR_ZONE_N_CONFIG2 config2;
544 uint32_t reserved0;
545 uint32_t timer_control;
546 uint32_t timer_status;
547 uint32_t reserved1[2];
548 } BPCM_ZONE;
549
550 #define BPCMZoneOffset(reg) offsetof(BPCM_ZONE,reg)
551 #define BPCMZoneRegOffset(reg) (BPCMZoneOffset(reg) >> 2)
552
553 typedef union {
554 struct {
555 uint32_t pmb_Addr:8;
556 uint32_t hw_rev:8;
557 uint32_t module_id:16;
558 } Bits;
559 uint32_t Reg32;
560 } BPCM_UBUS_ID_REG;
561
562 typedef union {
563 struct {
564 uint32_t num_zones:8;
565 uint32_t sr_reg_bits:8;
566 uint32_t pllType:2;
567 uint32_t reserved0:1;
568 uint32_t ubus:1;
569 uint32_t reserved1:12;
570 } Bits;
571 uint32_t Reg32;
572 } BPCM_UBUS_CAPABILITES_REG;
573
574 typedef union {
575 struct {
576 uint32_t ctrl_eswap:4;
577 uint32_t reserved0:4;
578 uint32_t ctrl_cd:4;
579 uint32_t reserved1:4;
580 uint32_t ctrl_seclev:8;
581 uint32_t reqout_seclev:8;
582 } Bits;
583 uint32_t Reg32;
584 } BPCM_UBUS_CTRL_REG;
585
586 typedef union {
587 struct {
588 uint64_t addr_in:24;
589 uint64_t addr_out:24;
590 uint64_t pid:8;
591 uint64_t size:5;
592 uint64_t cmddta:1;
593 uint64_t en:2;
594 } Bits;
595 struct {
596 uint32_t word0;
597 uint32_t word1;
598 } Regs32;
599 uint64_t Reg64;
600 } BPCM_UBUS_CFG_REG;
601
602 typedef union {
603 struct {
604 uint32_t ubus_soft_rst:1;
605 uint32_t alt_ubus_clk_sel:1;
606 uint32_t obsv_clk_swinit:1;
607 uint32_t reserved0:17;
608 uint32_t wl0_rf_enable:1;
609 uint32_t wl1_rf_enable:1;
610 uint32_t reserved1:10;
611 } Bits;
612 uint32_t Reg32;
613 } BPCM_CLKRST_CONTROL;
614
615 // There is a 20-bit address used to access any given BPCM register. The upper 8-bits
616 // is the device address and the lower 12-bits is used to represent the BPCM register
617 // set for that device. 32-bit registers are allocated on 4-byte boundaries
618 // (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
619 // Thus, to get the actual address of any given register within the device's address
620 // space, I'll use the "C" offsetof macro and divide the result by 4
621 // e.g.:
622 // int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL); // yields the byte offset of the target register
623 // int regAddress = regOffset/4; // yields the 32-bit word offset of the target register
624 // The ReadBPCMReg and WriteBPCMReg functions will always take a device address
625 // (address of the BPCM device) and register offset (like regOffset above). The offset
626 // will be divided by 4 and used as the lower 12-bits of the actual target address, while the
627 // device address will serve as the upper 8-bits of the actual address.
628 typedef struct {
629 // PMB-slave:
630 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
631 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
632 uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3
633 // BPCM
634 uint32_t control; // offset 0x10, PMB reg index 4
635 BPCM_SR_CONTROL sr_control; // offset 0x14, PMB reg index 5
636 uint32_t reserved1[2]; // offset 0x18, PMB reg index 6/7
637 // Client-specific registers
638 uint32_t client_specific[24]; // offset 0x20, PMB reg index 8..31
639 // Zones
640 BPCM_ZONE zones[]; // offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1))
641 } BPCM_REGS; // total offset space = 4096
642
643 #define BPCM_OFFSET(reg) (offsetof(BPCM_REGS,reg)>>2)
644
645 typedef struct {
646 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
647 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
648 uint32_t control; // offset = 0x08, actual offset = 2
649 BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
650 BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
651 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5
652 BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6
653 BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7
654 BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8
655 BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9
656 BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10
657 BPCM_GLOBAL_CNTL global_control; // offset = 0x2c, actual offset = 11
658 BPCM_MISC_CONTROL misc_control; // offset = 0x30, actual offset = 12
659 BPCM_MISC_CONTROL2 misc_control2; // offset = 0x34, actual offset = 13
660 uint32_t rvrsd[2];
661 BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
662 } BPCM_VDSL_REGS; // total offset space = 4096
663
664 #define BPCMVDSLOffset(reg) offsetof(BPCM_VDSL_REGS,reg)
665 #define BPCMVDSLRegOffset(reg) (BPCMVDSLOffset(reg) >> 2)
666
667 #define BPCMOffset(reg) offsetof(BPCM_REGS,reg)
668 #define BPCMRegOffset(reg) (BPCMOffset(reg) >> 2)
669
670 typedef struct {
671 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
672 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
673 uint32_t reserved0[2]; // offset = 0x08, actual offset = 2
674 uint32_t cfg_control; // offset = 0x10, actual offset = 4
675 BPCM_SR_CONTROL sr_control; // offset = 0x14, actual offset = 5
676 uint32_t reserved1[6]; // offset = 0x18, actual offset = 6
677 ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12
678 uint32_t biu_clk_control0; // offset = 0x34, actual offset = 13
679 uint32_t tbd[18]; // offset = 0x38, actual offset = 14
680 BPCM_ZONE zones; // offset = 0x80, actual offset = 32
681 } ARM_BPCM_REGS;
682 #define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg)
683 #define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2)
684
685 typedef struct {
686 BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
687 BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
688 uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3
689 PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4
690 PLL_CFG0_REG cfg0; // offset = 0x14, actual offset = 5
691 PLL_CFG1_REG cfg1; // offset = 0x18, actual offset = 6
692 PLL_NDIV_REG ndiv; // offset = 0x1c, actual offset = 7
693 PLL_PDIV_REG pdiv; // offset = 0x20, actual offset = 8
694 PLL_LOOP0_REG loop0; // offset = 0x24, actual offset = 9
695 PLL_LOOP1_REG loop1; // offset = 0x28, actual offset = a
696 PLL_CHCFG_REG ch01_cfg; // offset = 0x2c, actual offset = b
697 PLL_CHCFG_REG ch23_cfg; // offset = 0x30, actual offset = c
698 PLL_CHCFG_REG ch45_cfg; // offset = 0x34, actual offset = d
699 PLL_OCTRL_REG octrl; // offset = 0x38, actual offset = e
700 PLL_STAT_REG stat; // offset = 0x3c, actual offset = f
701 uint32_t strap; // offset = 0x40, actual offset = 0x10
702 PLL_DECNDIV_REG decndiv; // offset = 0x44, actual offset = 0x11
703 PLL_DECPDIV_REG decpdiv; // offset = 0x48, actual offset = 0x12
704 PLL_DECCH25_REG decch25; // offset = 0x4c, actual offset = 0x13
705 } PLL_BPCM_REGS;
706
707 #define PLLBPCMOffset(reg) offsetof(PLL_BPCM_REGS,reg)
708 #define PLLBPCMRegOffset(reg) (PLLBPCMOffset(reg) >> 2)
709
710 typedef struct {
711 BPCM_UBUS_ID_REG id_reg; /* offset = 0x00, actual offset = 0 */
712 BPCM_UBUS_CAPABILITES_REG capabilities; /* offset = 0x04, actual offset = 1 */
713 uint32_t reserved0; /* offset = 0x08, actual offset = 2 */
714 BPCM_UBUS_CTRL_REG ctrl; /* offset = 0x0c, actual offset = 3 */
715 BPCM_UBUS_CFG_REG cfg[4]; /* offset = 0x10..0x2c, actual offset = 4..11 */
716 } BPCM_UBUS_REG;
717
718 #define UBUSBPCMOffset(reg) offsetof(BPCM_UBUS_REG,reg)
719 #define UBUSBPCMRegOffset(reg) (UBUSBPCMOffset(reg) >> 2)
720
721 typedef struct {
722 // PMB-slave:
723 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
724 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
725 uint32_t reserved0[7]; // offset 0x08-0x20, PMB reg index 2-8
726 uint32_t control; // offset 0x24, PMB reg index 9
727 uint32_t observe_cntrl; // offset 0x28, PMB reg index 10
728 uint32_t observe_div; // offset 0x2c, PMB reg index 11
729 uint32_t observe_enable; // offset 0x30, PMB reg index 12
730 BPCM_CLKRST_CONTROL clkrst_control; // offset 0x34, PMB reg index 13
731 } BPCM_CLKRST_REGS;
732
733 #define CLKRSTBPCMOffset(reg) offsetof(BPCM_CLKRST_REGS, reg)
734 #define CLKRSTBPCMRegOffset(reg) (CLKRSTBPCMOffset(reg) >> 2)
735
736 typedef struct {
737 BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0
738 BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1
739 uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3
740 // BPCM
741 uint32_t control; // offset 0x10, PMB reg index 4
742 BPCM_SR_CONTROL sr_control; // offset 0x14, PMB reg index 5
743
744 uint32_t z0_pm_cntl; // offset 0x18
745 uint32_t z0_pm_status; // offset 0x1c
746 uint32_t z1_pm_cntl; // offset 0x20
747 uint32_t z2_pm_cntl; // offset 0x24
748 uint32_t reserved1[22]; // reserved from 0x28 to 0x7F
749 BPCM_ZONE zones[];
750
751 } BPCM_SYSPORT_REGS;
752
753 #define SYSPOffset(reg) offsetof(BPCM_SYSPORT_REGS,reg)
754 #define SYSPRegOffset(reg) (SYSPOffset(reg) >> 2)
755
756 // *************************** macros ******************************
757 #ifndef offsetof
758 #define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
759 #endif
760
761 #endif
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