arch/arm/include/asm/arch-bcm6878/misc.h

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  *
   3  *  Copyright 2019 Broadcom Ltd.
   4  */
   5
   6 #ifndef _6878_MISC_H
   7 #define _6878_MISC_H
   8
   9 /*
  10  * Gpio Controller
  11  */
  12 typedef struct GpioControl {
  13         uint32_t GPIODir[8];             /* 0x00-0x1c */
  14         uint32_t GPIOio[8];              /* 0x20-0x3c */
  15         uint32_t PadCtrl;                 /* 0x40 */
  16         uint32_t SpiSlaveCfg;             /* 0x44 */
  17         uint32_t TestControl;             /* 0x48 */
  18         uint32_t TestPortBlockEnMSB;      /* 0x4c */
  19         uint32_t TestPortBlockEnLSB;      /* 0x50 */
  20         uint32_t TestPortBlockDataMSB;    /* 0x54 */
  21         uint32_t TestPortBlockDataLSB;    /* 0x58 */
  22 #define PINMUX_DATA_SHIFT       12
  23 #define PINMUX_0                0
  24 #define PINMUX_1                1
  25 #define PINMUX_2                2
  26 #define PINMUX_3                3
  27 #define PINMUX_4                4
  28 #define PINMUX_5                5
  29 #define PINMUX_6                6
  30 #define PINMUX_7                7
  31 #define PAD_CTRL_SHIFT          12
  32 #define PAD_CTRL_MASK           (0x3f<<PAD_CTRL_SHIFT)
  33 #define PAD_SEL_SHIFT           12
  34 #define PAD_AMP_SHIFT           15
  35 #define PAD_IND_SHIFT           16
  36 #define PAD_GMII_SHIFT          17
  37        uint32_t TestPortCmd;             /* 0x5c */
  38 #define LOAD_MUX_REG_CMD        0x21
  39 #define LOAD_PAD_CTRL_CMD       0x22
  40         uint32_t DiagReadBack;            /* 0x60 */
  41         uint32_t DiagReadBackHi;          /* 0x64 */
  42         uint32_t GeneralPurpose;          /* 0x68 */
  43         uint32_t spare[3];
  44 } GpioControl;
  45
  46 #define GPIO_BASE          0xff800500
  47 #define GPIO ((volatile GpioControl * const) GPIO_BASE)
  48
  49 /*
  50  ** Misc Register Set Definitions.
  51  */
  52 typedef struct Misc {
  53     uint32_t  miscStrapBus;                       /* 0x00 */
  54 #define MISC_STRAP_BUS_BOOT_SEL_SHIFT           5
  55 #define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  56 #define MISC_STRAP_BUS_BOOT_SPI_NOR             (0x38 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  57 #define MISC_STRAP_BUS_BOOT_EMMC                (0x30 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  58 #define MISC_STRAP_BUS_BOOT_SPI_NAND            (0x28 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  59 #define MISC_STRAP_BUS_BOOT_SEL_NAND_MASK       (0x20 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  60 #define MISC_STRAP_BUS_BOOT_NAND                (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  61 #define MISC_STRAP_BUS_BOOT_SEL_PAGE_MASK       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  62 #define MISC_STRAP_BUS_BOOT_NAND_2K_PAGE        (0x00 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  63 #define MISC_STRAP_BUS_BOOT_NAND_4K_PAGE        (0x08 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  64 #define MISC_STRAP_BUS_BOOT_NAND_8K_PAGE        (0x10 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  65 #define MISC_STRAP_BUS_BOOT_NAND_512_PAGE       (0x18 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  66 #define MISC_STRAP_BUS_BOOT_SEL_ECC_MASK        (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  67 #define MISC_STRAP_BUS_BOOT_NAND_ECC_DISABLE    (0x0 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  68 #define MISC_STRAP_BUS_BOOT_NAND_ECC_1_BIT      (0x1 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  69 #define MISC_STRAP_BUS_BOOT_NAND_ECC_4_BIT      (0x2 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  70 #define MISC_STRAP_BUS_BOOT_NAND_ECC_8_BIT      (0x3 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  71 #define MISC_STRAP_BUS_BOOT_NAND_ECC_12_BIT     (0x4 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  72 #define MISC_STRAP_BUS_BOOT_NAND_ECC_24_BIT     (0x5 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  73 #define MISC_STRAP_BUS_BOOT_NAND_ECC_40_BIT     (0x6 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  74 #define MISC_STRAP_BUS_BOOT_NAND_ECC_60_BIT     (0x7 << MISC_STRAP_BUS_BOOT_SEL_SHIFT)
  75 #define MISC_STRAP_BUS_BOOTROM_BOOT_N           (0x1 << 11)
  76
  77 #define MISC_STRAP_BUS_PCIE_RC_MODE_SHIFT       0
  78 #define MISC_STRAP_BUS_PCIE_RC_MODE MASK        (1 << MISC_STRAP_BUS_PCIE_SINGLE_LANES_SHIFT) /* 1-root complex  0-end point */
  79 #define MISC_STRAP_GPON_TX_EN_SHIFT             1
  80 #define MISC_STRAP_GPON_TX_EN_MASK              (1 << MISC_STRAP_GPON_TX_EN_SHIFT)  // 1-Single ended, 0-differential
  81 #define MISC_STRAP_USB_PMU_POLARITY_SHIFT       30
  82 #define MISC_STRAP_USB_PMU_POLARITY_MASK        (1 << MISC_STRAP_USB_PMU_POLARITY_SHIFT)  // 1-active low, 0-active high
  83
  84     uint32_t  miscStrapOverride;                  /* 0x04 */
  85     uint32_t  miscMaskUBUSErr;                    /* 0x08 */
  86     uint32_t  miscPeriphCtrl;                     /* 0x0c */
  87     uint32_t  miscSPImasterCtrl;                  /* 0x10 */
  88     uint32_t  miscDierevid;                       /* 0x14 */
  89     uint32_t  miscPeriphMiscCtrl;                 /* 0x18 */
  90     uint32_t  miscPeriphMiscStat;                 /* 0x1c */
  91     uint32_t  miscSoftResetB;                     /* 0x20 */
  92     uint32_t  reserved0;                          /* 0x24 */
  93     uint32_t  miscSWdebugNW[2];                   /* 0x3c */
  94     uint32_t  miscWDresetCtrl;                    /* 0x30 */
  95 } Misc;
  96
  97 #define MISC_BASE          0xff802600
  98 #define MISC ((volatile Misc * const) MISC_BASE)
  99
 100 // PERF
 101 typedef struct PerfControl { /* GenInt */
 102      uint32_t        RevID;             /* (00) word 0 */
 103 #define CHIP_ID_SHIFT   12
 104 #define CHIP_ID_MASK    (0xfffff << CHIP_ID_SHIFT)
 105 #define REV_ID_MASK     0xff
 106 } PerfControl;
 107
 108 #define PERF_BASE              0xff800000
 109 #define PERF ((volatile PerfControl * const) PERF_BASE)
 110
 111 #endif