arch/arm/mach-bcmbca/bcm6855/cpu.c

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019 Broadcom Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <asm/arch/cpu.h>
   8 #include <asm/arch/ddr.h>
   9 #include <asm/arch/ubus4.h>
  10 #include <spl.h>
  11 #include "bcm_otp.h"
  12 #if defined(CONFIG_BCMBCA_PMC)
  13 #include "pmc_drv.h"
  14 #include "asm/arch/BPCM.h"
  15 #include "clk_rst.h"
  16 #endif
  17
  18 int arch_cpu_init(void)
  19 {
  20 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
  21     u32 frq = COUNTER_FREQUENCY;
  22
  23     // set arch timer frequency
  24     asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
  25
  26     // enable system timer
  27     BIUCFG->TSO_CNTCR |= 1;
  28
  29     /* enable unalgined access */
  30     set_cr(get_cr() & ~CR_A);
  31 #endif
  32
  33     return 0;
  34 }
  35
  36 void boost_cpu_clock(void)
  37 {
  38     int stat = 0;
  39     uint32_t chipid;
  40     PLL_CTRL_REG ctrl_reg;
  41
  42     chipid =  (((PERF->RevID & CHIP_ID_MASK) >> (CHIP_ID_SHIFT-CHIP_ID_LC_SIZE)) | (TOP->OtpChipidLC && CHIP_ID_LC_MASK));
  43     if ((chipid==0x68552c) || (chipid==0x682520) || (chipid==0x685500))
  44     {
  45         stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
  46         ctrl_reg.Bits.byp_wait = 1;
  47         stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
  48
  49         stat |= pll_vco_config(PMB_ADDR_BIU_PLL ,60, 1);
  50         stat |= pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, 2);
  51
  52         stat = ReadBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), &ctrl_reg.Reg32);
  53         ctrl_reg.Bits.byp_wait = 0;
  54         stat |= WriteBPCMRegister(PMB_ADDR_BIU_PLL, PLLBPCMRegOffset(resets), ctrl_reg.Reg32);
  55     }
  56     else if (chipid==685520)
  57         stat = pll_ch_freq_set(PMB_ADDR_BIU_PLL, 0, 2);
  58
  59     if (stat)
  60         printf("Error: failed to set cpu clock\n");
  61
  62     UBUS4CLK->ClockCtrl = UBUS4_CLK_BYPASS_MASK;
  63 }
  64
  65 #if !defined(CONFIG_SPL_BUILD)
  66 void print_chipinfo(void)
  67 {
  68         unsigned int cpu_speed, rdp_speed, nr_cores;
  69         unsigned int chipId = (PERF->RevID & CHIP_ID_MASK) >> CHIP_ID_SHIFT;
  70         unsigned int revId = PERF->RevID & REV_ID_MASK;
  71
  72     unsigned int chipIdLC = (TOP->OtpChipidLC && CHIP_ID_LC_MASK);
  73     if (chipIdLC)
  74         chipId = (chipId << CHIP_ID_LC_SIZE) | chipIdLC;
  75
  76     printf("Chip ID: BCM%X_%X\n",chipId,revId);
  77
  78     pll_ch_freq_get(PMB_ADDR_BIU_PLL, 0, &cpu_speed);
  79     if (bcm_otp_get_nr_cpus(&nr_cores))
  80         printf("Error: failed to read cores from OTP\n");
  81     else
  82     {
  83         if (nr_cores)
  84             printf("ARM Cortex A7 Dual Core: %dMHz", cpu_speed);
  85         else
  86             printf("ARM Cortex A7 Triple Core: %dMHz", cpu_speed);
  87     }
  88
  89     get_rdp_freq(& rdp_speed);
  90     printf("RDP Freq: %dMHz\n", rdp_speed);
  91 }
  92 #endif
  93
  94 int bcmbca_get_boot_device(void)
  95 {
  96         if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_NAND_MASK) == MISC_STRAP_BUS_BOOT_NAND)
  97                 return BOOT_DEVICE_NAND;
  98
  99         if ((MISC->miscStrapBus&MISC_STRAP_BUS_BOOT_SEL_MASK) == MISC_STRAP_BUS_BOOT_SPI_NAND)
 100                 return BOOT_DEVICE_SPI;
 101
 102         printf("Error: boot_sel straps are not set correctly\n");
 103
 104         return BOOT_DEVICE_NONE;
 105 }
 106
 107 #if !defined(CONFIG_TPL_ATF)
 108 void boot_secondary_cpu(unsigned long vector)
 109 {
 110     uint32_t cpu = 1;
 111     uint32_t nr_cpus;
 112     ARM_CONTROL_REG ctrl_reg;
 113     uint64_t rvbar = vector;
 114     int stat;
 115
 116     printf("boot secondary cpu from 0x%lx\n", vector);
 117
 118     *(volatile uint32_t*)(BOOTLUT_BASE+0x20) = vector;
 119
 120     if ( bcm_otp_get_nr_cpus(&nr_cpus) )
 121         return;
 122
 123     nr_cpus = MAX_NUM_OF_CPU-nr_cpus;
 124
 125     while (cpu < nr_cpus)
 126     {
 127         BIUCFG->cluster[0].rvbar_addr[cpu] = rvbar;
 128
 129         stat = PowerOnDevice(PMB_ADDR_ORION_CPU0 + cpu);
 130         if (stat != kPMC_NO_ERROR)
 131             printf("failed to power on secondary cpu %d - sts %d\n", cpu, stat);
 132
 133         stat = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), &ctrl_reg.Reg32);
 134         ctrl_reg.Bits.cpu_reset_n &= ~(0x1 << cpu);
 135         stat |= WriteBPCMRegister(PMB_ADDR_BIU_BPCM, ARMBPCMRegOffset(arm_control), ctrl_reg.Reg32);
 136         if (stat != kPMC_NO_ERROR)
 137             printf("failed to boot secondary cpu %d - sts %d\n", cpu, stat);
 138         cpu++;
 139     }
 140
 141     return;
 142 }
 143 #endif
 144