arch/arm/mach-bcmbca/rdp/rdd_data_structures.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2013 Broadcom
   4  */
   5 /*
   6
   7 */
   8
   9 #ifndef _BL_LILAC_DRV_RUNNER_DATA_STRUCTURES_H
  10 #define _BL_LILAC_DRV_RUNNER_DATA_STRUCTURES_H
  11
  12
  13 /********************************** Defines ***********************************/
  14
  15 /* Runner Device Driver version */
  16 #define LILAC_RDD_RELEASE                                   ( 0x04 )
  17 #define LILAC_RDD_VERSION                                   ( 0x10 )
  18 #define LILAC_RDD_PATCH                                     ( 0x02 )
  19 #define LILAC_RDD_REVISION                                  ( 0x01 )
  20
  21 #define RDP_CFG_BUF_SIZE_2K                                 0
  22 #define RDP_CFG_BUF_SIZE_4K                                 1
  23 #define RDP_CFG_BUF_SIZE_16K                                2
  24 #define RDP_CFG_BUF_SIZE_2_5K                               7
  25
  26
  27 #if defined(WL4908) && defined(CONFIG_BCM_JUMBO_FRAME)
  28 #define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 512 /* FPM token size */
  29 #elif defined(WL4908)
  30 #define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 256 /* FPM token size */
  31 #elif defined(DSL_63138) && defined(CONFIG_BCM_JUMBO_FRAME)
  32 #define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 2560
  33 #define RDP_CFG_BUF_SIZE_VALUE RDP_CFG_BUF_SIZE_2_5K
  34 #elif defined(DSL_63148) && defined(CONFIG_BCM_JUMBO_FRAME)
  35 #define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 4096
  36 #define RDP_CFG_BUF_SIZE_VALUE RDP_CFG_BUF_SIZE_4K
  37 #else
  38 #define LILAC_RDD_RUNNER_PACKET_BUFFER_SIZE                 2048
  39 #define RDP_CFG_BUF_SIZE_VALUE RDP_CFG_BUF_SIZE_2K
  40 #endif
  41 #define RDD_SIMULATION_PACKET_BUFFER_SIZE                   2048
  42 #define LILAC_RDD_RUNNER_EXTENSION_BUFFER_SIZE              512
  43 #define LILAC_RDD_PACKET_DDR_OFFSET                         18
  44 #define LILAC_RDD_RUNNER_PSRAM_BUFFER_SIZE                  128
  45 #define LILAC_RDD_RUNNER_EXTENSION_PACKET_BUFFER_SIZE       64
  46 #define LILAC_RDD_RUNNER_EXTENSION_PACKET_HEADER_SIZE       32
  47
  48 /* RX - TX */
  49 #define LILAC_RDD_RATE_CONTROLLERS_BUDGET_SET_SIZE          16
  50 #define RDD_EMAC_NUMBER_OF_QUEUES                           8
  51 #define LILAC_RDD_EMAC_EGRESS_COUNTER_OFFSET                0
  52 #define LILAC_RDD_EMAC_RATE_SHAPER_GROUPS_STATUS_OFFSET     8
  53 #define RDD_RATE_CONTROL_EXPONENT0                          1
  54 #define RDD_RATE_CONTROL_EXPONENT1                          4
  55 #define RDD_RATE_CONTROL_EXPONENT2                          7
  56 #define RDD_RATE_CONTROL_EXPONENT_NUM                       3
  57
  58 /* CPU-RX table & queues */
  59
  60 /* CPU-TX table */
  61 #define LILAC_RDD_CPU_TX_QUEUE_SIZE                         16
  62 #define LILAC_RDD_CPU_TX_QUEUE_SIZE_MASK                    0xFF7F
  63 #define LILAC_RDD_CPU_TX_DESCRIPTOR_NUMBER_MASK             0x00F8
  64 #define LILAC_RDD_CPU_TX_ABS_DATA_PTR_DESCRIPTOR_SIZE       4
  65 #define LILAC_RDD_CPU_TX_ABS_DATA_PTR_QUEUE_SIZE            16
  66 #define LILAC_RDD_CPU_TX_ABS_DATA_PTR_QUEUE_SIZE_MASK       0xFFBF
  67 #define LILAC_RDD_CPU_TX_COMMAND_EGRESS_PORT_PACKET         0
  68 #define LILAC_RDD_CPU_TX_COMMAND_BRIDGE_PACKET              1
  69 #define LILAC_RDD_CPU_TX_COMMAND_INTERWORKING_PACKET        2
  70 #define LILAC_RDD_CPU_TX_COMMAND_ABSOLUTE_ADDRESS_PACKET    3
  71 #define LILAC_RDD_CPU_TX_COMMAND_SPDSVC_PACKET              4
  72 #define LILAC_RDD_CPU_TX_COMMAND_MESSAGE                    7
  73
  74 /* Bridging */
  75 #define LILAC_RDD_NUMBER_OF_BRIDGE_PORTS                    15
  76 #define LILAC_RDD_FLOW_CLASSIFICATION_ENTRY_STOP            0xFFFF
  77 #define LILAC_RDD_MAX_PBITS                                 7
  78 #define LILAC_RDD_NUMBER_OF_ETHER_TYPE_FILTERS              12
  79
  80 /* Ingress Classification */
  81 #define RDD_INGRESS_CLASSIFICATION_SEARCH_HOP               BL_LILAC_RDD_MAC_TABLE_MAX_HOP_4
  82 #define RDD_INGRESS_CLASSIFICATION_SEARCH_DEPTH             (1 << RDD_INGRESS_CLASSIFICATION_SEARCH_HOP)
  83
  84 /* Ingress Handler */
  85 #define LILAC_RDD_IH_HEADER_LENGTH                          110
  86 #define LILAC_RDD_IH_BUFFER_BBH_ADDRESS                     0x8000
  87 #define LILAC_RDD_RUNNER_A_IH_BUFFER                        14
  88 #define LILAC_RDD_RUNNER_B_IH_BUFFER                        15
  89 #define LILAC_RDD_RUNNER_A_IH_BUFFER_BBH_OFFSET             ( ( LILAC_RDD_RUNNER_A_IH_BUFFER * 128 + LILAC_RDD_PACKET_DDR_OFFSET ) / 8 )
  90 #define LILAC_RDD_RUNNER_B_IH_BUFFER_BBH_OFFSET             ( ( LILAC_RDD_RUNNER_B_IH_BUFFER * 128 + LILAC_RDD_PACKET_DDR_OFFSET ) / 8 )
  91 #define LILAC_RDD_IH_HEADER_DESCRIPTOR_BBH_ADDRESS          0x0
  92 #define INVALID_BPM_BUFFER                                  0xFFFF
  93
  94 #define LILAC_RDD_IH_PCI_CLASS                              2
  95 #define LILAC_RDD_IH_WAN_BRIDGE_LOW_CLASS                   9
  96 #define LILAC_RDD_IH_LAN_EMAC0_CLASS                        10
  97 #define LILAC_RDD_IH_LAN_EMAC1_CLASS                        11
  98 #define LILAC_RDD_IH_LAN_EMAC2_CLASS                        12
  99 #define LILAC_RDD_IH_LAN_EMAC3_CLASS                        13
 100 #define LILAC_RDD_IH_LAN_EMAC4_CLASS                        14
 101
 102 /* MAC Table */
 103 #define LILAC_RDD_MAC_CONTEXT_MULTICAST                     0x1
 104 #define LILAC_RDD_MAC_CONTEXT_ENTRY_TYPE_MASK               ( 1 << 6 )
 105
 106 /* Router Tables */
 107 #define LILAC_RDD_NUMBER_OF_SUBNETS                         3
 108
 109 #define LILAC_RDD_NUMBER_OF_TIMER_TASKS                     8
 110 #define LILAC_RDD_CPU_RX_METER_TIMER_PERIOD                 10000
 111
 112 /* VLAN & PBITs actions */
 113 #define LILAC_RDD_VLAN_TYPES                                4
 114 #define LILAC_RDD_VLAN_TYPE_UNTAGGED                        0
 115 #define LILAC_RDD_VLAN_TYPE_SINGLE                          1
 116 #define LILAC_RDD_VLAN_TYPE_DOUBLE                          2
 117 #define LILAC_RDD_VLAN_TYPE_PRIORITY                        3
 118 #define LILAC_RDD_VLAN_COMMAND_SKIP                         128
 119
 120 /* VLAN switching */
 121 #define LILAC_RDD_LAN_VID_SKIP_VALUE                        0x8000
 122 #define LILAC_RDD_LAN_VID_STOP_VALUE                        0xFFFF
 123
 124 /* Firewall */
 125 #define LILAC_RDD_FIREWALL_RULES_MASK_MAX_LENGTH            32
 126
 127 /* PCI */
 128 #define LILAC_RDD_PCI_TX_NUMBER_OF_FIFOS                    4
 129 #define LILAC_RDD_PCI_TX_FIFO_SIZE                          8
 130
 131 /* CRC */
 132 #define RDD_CRC_TYPE_16                                     0
 133 #define RDD_CRC_TYPE_32                                     1
 134
 135 /* GPIO */
 136 #define RDD_GPIO_IO_ADDRESS                                 0x148
 137
 138 /* -Etc- */
 139 #define LILAC_RDD_TRUE                                      1
 140 #define LILAC_RDD_FALSE                                     0
 141 #define LILAC_RDD_ON                                        1
 142 #define LILAC_RDD_OFF                                       0
 143
 144 /* CPU TX */
 145 #define LILAC_RDD_CPU_TX_SKB_INDEX_OWNERSHIP_BIT_MASK       0x8000
 146 #define LILAC_RDD_CPU_TX_SKB_INDEX_MASK                     0x3FFF
 147 #define LILAC_RDD_CPU_TX_SKB_LIMIT_MIN                      256
 148 #define LILAC_RDD_CPU_TX_SKB_LIMIT_MAX                      16384
 149 #define LILAC_RDD_CPU_TX_SKB_LIMIT_MULTIPLICATION           8
 150
 151 #define RDD_CLEAR_REGISTER( v )                             ( *( ( uint32_t *) v ) = 0 )
 152
 153 #define ADDRESS_OF(runner, task_name)                       runner##_##task_name
 154
 155 #define ROUND_UP_TO_BITS(_val, _bit)      (((_val) + (1 << _bit) - 1) & ~((1 << _bit) - 1))
 156 #define ROUND_UP_MB(_n)                   ROUND_UP_TO_BITS(_n, 20ul)
 157
 158 #if defined(WL4908)
 159 #define RDP_NATC_CONTEXT_TABLE_SIZE       (sizeof(RDD_NATC_CONTEXT_TABLE_DTS))
 160 #define RDP_NATC_CONTEXT_TABLE_ADDR       (NATC_CONTEXT_TABLE_ADDRESS)
 161
 162 #define RDP_CONTEXT_CONTINUATION_TABLE_SIZE  (sizeof(RDD_CONTEXT_CONTINUATION_TABLE_DTS))
 163 #define RDP_CONTEXT_CONTINUATION_TABLE_ADDR  (RDP_NATC_CONTEXT_TABLE_ADDR + ROUND_UP_TO_BITS(RDP_NATC_CONTEXT_TABLE_SIZE, 21))
 164
 165 #define RDP_NATC_KEY_TABLE_SIZE           (sizeof(RDD_NAT_CACHE_TABLE_DTS) + sizeof(RDD_NAT_CACHE_EXTENSION_TABLE_DTS))
 166 #define RDP_NATC_KEY_TABLE_ADDR           (RDP_CONTEXT_CONTINUATION_TABLE_ADDR + ROUND_UP_MB(RDP_CONTEXT_CONTINUATION_TABLE_SIZE))
 167
 168 #define RDP_DDR_DATA_STRUCTURES_SIZE      (RDP_NATC_KEY_TABLE_ADDR + ROUND_UP_MB(RDP_NATC_KEY_TABLE_SIZE))
 169
 170 #ifdef CONFIG_BCM_RDPA_MCAST
 171 #define RDP_DDR_MC_HEADER_SIZE            0x2000000
 172 #else
 173 #define RDP_DDR_MC_HEADER_SIZE            0
 174 #endif
 175 #else // if defined(WL4908) else DSL_63138
 176 #define RDP_DDR_DATA_STRUCTURES_SIZE      (sizeof(RDD_CONNECTION_TABLE_DTS) * 2 + ROUND_UP_MB(sizeof(RDD_CONTEXT_TABLE_DTS)))
 177 #endif
 178
 179 #if !defined(FIRMWARE_INIT)
 180 /* DDR offsets */
 181 #define DsConnectionTableBase              ( g_runner_tables_ptr + DS_CONNECTION_TABLE_ADDRESS )
 182 #define UsConnectionTableBase              ( g_runner_tables_ptr + US_CONNECTION_TABLE_ADDRESS )
 183 #endif
 184
 185 /******************************* Data structures ******************************/
 186
 187 #define LILAC_RDD_FIELD_SHIFT( ls_bit_number, field_width, write_value )    ( ( write_value & ( ( 1 << (field_width) ) - 1 ) ) << ( ls_bit_number ) )
 188
 189 #define RDD_EMAC_DESCRIPTOR_EGRESS_COUNTER_OFFSET  0
 190
 191 /* WAN TX Pointers table */
 192 typedef struct
 193 {
 194     uint16_t  wan_channel_ptr;
 195     uint16_t  rate_controller_ptr;
 196     uint16_t  wan_tx_queue_ptr;
 197 }
 198 __PACKING_ATTRIBUTE_STRUCT_END__ RDD_WAN_TX_POINTERS_ENTRY_DTS;
 199
 200
 201 typedef struct
 202 {
 203     RDD_WAN_TX_POINTERS_ENTRY_DTS  entry[ RDD_WAN_CHANNELS_0_7_TABLE_SIZE + RDD_WAN_CHANNELS_8_39_TABLE_SIZE ][ RDD_WAN_CHANNEL_0_7_DESCRIPTOR_RATE_CONTROLLER_ADDR_NUMBER ]
 204                                         [ RDD_US_RATE_CONTROLLER_DESCRIPTOR_TX_QUEUE_ADDR_NUMBER ];
 205 }
 206 RDD_WAN_TX_POINTERS_TABLE_DTS;
 207
 208
 209 #define RDD_CPU_RX_DESCRIPTOR_SKB_INDEX_READ( r, p )            FIELD_MREAD_32( ( (uint8_t *)p + 4),  0,  8, r )
 210 #define RDD_CPU_RX_DESCRIPTOR_REASON_L_READ( p )                FIELD_GET( *( (uint32_t *)p + 0), 25,  6 )
 211 #define RDD_CPU_RX_DESCRIPTOR_PAYLOAD_OFFSET_FLAG_L_READ( p )   FIELD_GET( *( (uint32_t *)p + 0), 22,  1 )
 212 #define RDD_CPU_RX_DESCRIPTOR_FLOW_ID_L_READ( p )               FIELD_GET( *( (uint32_t *)p + 0), 14,  8 )
 213 #define RDD_CPU_RX_DESCRIPTOR_PACKET_LENGTH_L_READ( p )         FIELD_GET( *( (uint32_t *)p + 0),  0, 14 )
 214 #define RDD_CPU_RX_DESCRIPTOR_SRC_PORT_L_READ( p )              FIELD_GET( *( (uint32_t *)p + 1), 28,  4 )
 215 #define RDD_CPU_RX_DESCRIPTOR_NEXT_PTR_L_READ( p )              FIELD_GET( *( (uint32_t *)p + 1), 15, 13 )
 216 #define RDD_CPU_RX_DESCRIPTOR_ABS_FLAG_L_READ( p )              FIELD_GET( *( (uint32_t *)p + 1), 14,  1 )
 217 #if defined(DSL_63138)
 218 #define RDD_CPU_RX_DESCRIPTOR_BUFFER_NUMBER_L_READ( p )         FIELD_GET( *( (uint32_t *)p + 1),  0, 15 )
 219 #else
 220 #define RDD_CPU_RX_DESCRIPTOR_BUFFER_NUMBER_L_READ( p )         FIELD_GET( *( (uint32_t *)p + 1),  0, 14 )
 221 #endif
 222 #define RDD_CPU_RX_DESCRIPTOR_SKB_INDEX_L_READ( p )             FIELD_GET( *( (uint32_t *)p + 1),  0,  8 )
 223
 224
 225 #define RDD_CPU_TX_DESCRIPTOR_CONTEXT_INDEX_WRITE( v, p )      FIELD_MWRITE_32( ( (uint8_t *)p + 0), 0, 15, v )
 226 #define RDD_CPU_TX_DESCRIPTOR_COUNTER_WRITE( v, p )            FIELD_MWRITE_32( ( (uint8_t *)p + 0), 0,  5, v )
 227 #define RDD_CPU_TX_DESCRIPTOR_IPTV_MAC_IDX_WRITE( v, p )       FIELD_MWRITE_32( ( (uint8_t *)p + 0), 0, 11, v )
 228 #define RDD_CPU_TX_DESCRIPTOR_COUNTER_4_BYTES_WRITE( v, p )    FIELD_MWRITE_32( ( (uint8_t *)p + 0), 5,  1, v )
 229 #define RDD_CPU_TX_DESCRIPTOR_SRC_BRIDGE_PORT_WRITE( v, p )    FIELD_MWRITE_32( ( (uint8_t *)p + 0), 14, 5, v )
 230 #define RDD_CPU_TX_DESCRIPTOR_QUEUE_WRITE( v, p )              FIELD_MWRITE_32( ( (uint8_t *)p + 0), 19, 3, v )
 231 #define RDD_CPU_TX_DESCRIPTOR_GROUP_WRITE( v, p )              FIELD_MWRITE_32( ( (uint8_t *)p + 0), 19, 7, v )
 232 #define RDD_CPU_TX_DESCRIPTOR_FLOW_WRITE( v, p )               FIELD_MWRITE_32( ( (uint8_t *)p + 0), 19, 9, v )
 233 #define RDD_CPU_TX_DESCRIPTOR_EMAC_WRITE( v, p )               FIELD_MWRITE_32( ( (uint8_t *)p + 0), 22, 4, v )
 234 #define RDD_CPU_TX_DESCRIPTOR_INTERRUPT_NUMBER_WRITE( v, p )   FIELD_MWRITE_32( ( (uint8_t *)p + 0), 22, 4, v )
 235 #define RDD_CPU_TX_DESCRIPTOR_TCONT_INDEX_WRITE( v, p )        FIELD_MWRITE_32( ( (uint8_t *)p + 4), 22, 6, v )
 236 #define RDD_CPU_TX_DESCRIPTOR_TX_QUEUE_PTR_WRITE( v, p )       FIELD_MWRITE_32( ( (uint8_t *)p + 4), 23, 9, v )
 237 #define RDD_CPU_TX_DESCRIPTOR_MESSAGE_PARAMETER_WRITE( v, p )  FIELD_MWRITE_32( ( (uint8_t *)p + 4), 23, 5, v )
 238
 239 #define RDD_CPU_TX_DESCRIPTOR_VALID_L_WRITE( v )               LILAC_RDD_FIELD_SHIFT( 31,  1, (v) )
 240 #define RDD_CPU_TX_DESCRIPTOR_COMMAND_L_WRITE( v )             LILAC_RDD_FIELD_SHIFT( 28,  3, (v) )
 241 #ifndef G9991
 242 #define RDD_CPU_TX_DESCRIPTOR_EMAC_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 22,  4, (v) )
 243 #else
 244 #define RDD_CPU_TX_DESCRIPTOR_EMAC_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 22,  5, (v) )
 245 #endif
 246 #define RDD_CPU_TX_DESCRIPTOR_US_GEM_FLOW_L_WRITE( v )         LILAC_RDD_FIELD_SHIFT( 20,  8, (v) )
 247 #define RDD_CPU_TX_DESCRIPTOR_QUEUE_L_WRITE( v )               LILAC_RDD_FIELD_SHIFT( 19,  3, (v) )
 248 #define RDD_CPU_TX_DESCRIPTOR_SUBNET_ID_L_WRITE( v )           LILAC_RDD_FIELD_SHIFT( 19,  4, (v) )
 249 #define RDD_CPU_TX_DESCRIPTOR_DS_GEM_FLOW_L_WRITE( v )         LILAC_RDD_FIELD_SHIFT( 14,  8, (v) )
 250 #define RDD_CPU_TX_DESCRIPTOR_SRC_BRIDGE_PORT_L_WRITE( v )     LILAC_RDD_FIELD_SHIFT( 14,  5, (v) )
 251 #define RDD_CPU_TX_DESCRIPTOR_PACKET_LENGTH_L_WRITE( v )       LILAC_RDD_FIELD_SHIFT(  0, 14, (v) )
 252 #define RDD_CPU_TX_DESCRIPTOR_SSID_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 27,  4, (v) )
 253 #define RDD_CPU_TX_DESCRIPTOR_TX_QUEUE_PTR_L_WRITE( v )        LILAC_RDD_FIELD_SHIFT( 23,  9, (v) )
 254 #define RDD_CPU_TX_DESCRIPTOR_MESSAGE_PARAMETER_L_WRITE( v )   LILAC_RDD_FIELD_SHIFT( 23,  5, (v) )
 255 #define RDD_CPU_TX_DESCRIPTOR_IH_CLASS_L_WRITE( v )            LILAC_RDD_FIELD_SHIFT( 23,  4, (v) )
 256 #define RDD_CPU_TX_DESCRIPTOR_PAYLOAD_OFFSET_L_WRITE( v )      LILAC_RDD_FIELD_SHIFT( 16,  7, (v) )
 257 #define RDD_CPU_TX_DESCRIPTOR_1588_INDICATION_L_WRITE( v )     LILAC_RDD_FIELD_SHIFT( 27,  1, (v) )
 258 #define RDD_CPU_TX_DESCRIPTOR_TCONT_INDEX_L_WRITE( v )         LILAC_RDD_FIELD_SHIFT(  8,  6, (v) )
 259 #define RDD_CPU_TX_DESCRIPTOR_ABS_FLAG_L_WRITE( v )            LILAC_RDD_FIELD_SHIFT( 31,  1, (v) )
 260 #define RDD_CPU_TX_DESCRIPTOR_GSO_PKT_L_WRITE( v )             LILAC_RDD_FIELD_SHIFT( 27,  1, (v) )
 261 #if defined(DSL_63138)
 262 #define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_L_WRITE( v )       LILAC_RDD_FIELD_SHIFT(  0, 15, (v) )
 263 #else
 264 #define RDD_CPU_TX_DESCRIPTOR_BUFFER_NUMBER_L_WRITE( v )       LILAC_RDD_FIELD_SHIFT(  0, 14, (v) )
 265 #endif
 266 #define RDD_CPU_TX_DESCRIPTOR_SKB_INDEX_L_WRITE( v )           LILAC_RDD_FIELD_SHIFT(  0,  8, (v) )
 267 #define RDD_CPU_TX_DESCRIPTOR_FLOW_L_WRITE( v )                LILAC_RDD_FIELD_SHIFT( 19,  9, (v) )
 268 #define RDD_CPU_TX_DESCRIPTOR_IPTV_MAC_IDX_L_WRITE( v )        LILAC_RDD_FIELD_SHIFT(  0, 11, (v) )
 269 #define RDD_CPU_TX_DESCRIPTOR_GROUP_L_WRITE( v )               LILAC_RDD_FIELD_SHIFT( 19,  7, (v) )
 270 #define RDD_CPU_TX_DESCRIPTOR_COUNTER_L_WRITE( v )             LILAC_RDD_FIELD_SHIFT(  0,  5, (v) )
 271 #define RDD_CPU_TX_DESCRIPTOR_COUNTER_4_BYTES_L_WRITE( v )     LILAC_RDD_FIELD_SHIFT(  5,  1, (v) )
 272 #define RDD_CPU_TX_DESCRIPTOR_MSG_TYPE_L_WRITE( v )            LILAC_RDD_FIELD_SHIFT(  0,  4, (v) )
 273
 274
 275 #define LILAC_RDD_INGRESS_RATE_LIMITER_MAX_ALLOCATED_BUDGET    ( ( 1 << 17 ) - 1)
 276
 277
 278 typedef struct
 279 {
 280     BL_LILAC_RDD_FILTER_MODE_DTE  entry[ 9 ][ LILAC_RDD_NUMBER_OF_SUBNETS ][ LILAC_RDD_NUMBER_OF_ETHER_TYPE_FILTERS ];
 281 }
 282 BL_LILAC_RDD_ETHER_TYPE_FILTER_MATRIX_DTS;
 283
 284
 285 /* software version */
 286 typedef struct
 287 {
 288     /* code */
 289     uint8_t   code;
 290
 291     /* version */
 292     uint8_t   version;
 293
 294     /* patch */
 295     uint8_t   patch;
 296
 297     /* revision */
 298     uint8_t   revision;
 299 }
 300 BL_LILAC_RDD_VERSION_DTS;
 301
 302
 303 #if defined(WL4908)
 304 #define RDD_FLOW_ENTRIES_SIZE 16512
 305 #define RDD_FLOW_ENTRY_VALID 0x80000000
 306 #define RDD_RESERVED_CONTEXT_ENTRIES 128
 307 #define RDD_CONTEXT_TABLE_SIZE RDD_FLOW_ENTRIES_SIZE
 308 #endif /* WL4908 */
 309
 310
 311 /****************************** Enumeration ***********************************/
 312
 313 typedef enum
 314 {
 315     LILAC_RDD_CPU_TX_MESSAGE_DDR_HEADROOM_SIZE_SET                = 0,
 316     LILAC_RDD_CPU_TX_MESSAGE_RX_FLOW_PM_COUNTERS_GET              = 1,
 317     LILAC_RDD_CPU_TX_MESSAGE_TX_FLOW_PM_COUNTERS_GET              = 2,
 318     LILAC_RDD_CPU_TX_MESSAGE_FLOW_PM_COUNTERS_GET                 = 3,
 319     LILAC_RDD_CPU_TX_MESSAGE_BRIDGE_PORT_PM_COUNTERS_GET          = 4,
 320     LILAC_RDD_CPU_TX_MESSAGE_FLUSH_GPON_QUEUE                     = 5,
 321     LILAC_RDD_CPU_TX_MESSAGE_LAG_PORT_GET                         = 5,
 322     LILAC_RDD_CPU_TX_MESSAGE_GLOBAL_REGISTERS_GET                 = 6,
 323     LILAC_RDD_CPU_TX_MESSAGE_IPTV_MAC_COUNTER_GET                 = 7,
 324     LILAC_RDD_CPU_TX_MESSAGE_INVALIDATE_CONTEXT_INDEX_CACHE_ENTRY = 8,
 325     LILAC_RDD_CPU_TX_MESSAGE_RING_DESTROY                         = 9,
 326     LILAC_RDD_CPU_TX_MESSAGE_IPV6_CRC_GET                         = 10,
 327     LILAC_RDD_CPU_TX_MESSAGE_PM_COUNTER_GET                       = 11,
 328     LILAC_RDD_CPU_TX_MESSAGE_FLUSH_ETH_QUEUE                      = 12,
 329     LILAC_RDD_CPU_TX_MESSAGE_UPDATE_US_PD_POOL_QUOTA              = 12,
 330     LILAC_RDD_CPU_TX_MESSAGE_ACTIVATE_TCONT                       = 13,
 331     LILAC_RDD_CPU_TX_MESSAGE_UPDATE_PD_POOL_QUOTA                 = 13,
 332     LILAC_RDD_CPU_TX_MESSAGE_MIRRORING_MODE_CONFIG                = 14,
 333     LILAC_RDD_CPU_TX_MESSAGE_DHD_MESSAGE                          = 14,
 334     LILAC_RDD_CPU_TX_MESSAGE_RELEASE_SKB_BUFFERS                  = 15,
 335 }
 336 LILAC_RDD_CPU_TX_MESSAGE_TYPE;
 337
 338 #define RDD_CPU_TX_MESSAGE_DHD_MESSAGE LILAC_RDD_CPU_TX_MESSAGE_DHD_MESSAGE
 339
 340 typedef enum
 341 {
 342     LILAC_RDD_MAC_HASH_TYPE_INCREMENTAL = 0,
 343     LILAC_RDD_MAC_HASH_TYPE_CRC16       = 1,
 344 }
 345 LILAC_RDD_MAC_TABLE_HASH_TYPE;
 346
 347
 348 typedef enum
 349 {
 350     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_UNKNOWN         = 0,
 351     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_PPPOE_DISCOVERY = 1,
 352     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_PPPOE_SESSION   = 2,
 353     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_IPOE            = 4,
 354     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_0  = 8,
 355     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_1  = 16,
 356     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_2  = 32,
 357     LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_USER_DEFINED_3  = 64,
 358 }
 359 LILAC_RDD_PARSER_LAYER2_PROTOCOL_1_HOT_DTE;
 360
 361
 362 typedef enum
 363 {
 364     LILAC_RDD_FARWARDING_DIRECTION_UPSTREAM =   0,
 365     LILAC_RDD_FARWARDING_DIRECTION_DOWNSTREAM = 1,
 366 }
 367 LILAC_RDD_BRIDGE_FORWARDING_DIRECTION_DTS;
 368
 369
 370
 371 typedef enum
 372 {
 373     CS_R8  = 0,
 374     CS_R9  = 1,
 375     CS_R10 = 2,
 376     CS_R11 = 4,
 377     CS_R12 = 5,
 378     CS_R13 = 6,
 379     CS_R14 = 8,
 380     CS_R15 = 9,
 381     CS_R16 = 10,
 382     CS_R17 = 12,
 383     CS_R18 = 13,
 384     CS_R19 = 14,
 385     CS_R20 = 16,
 386     CS_R21 = 17,
 387     CS_R22 = 18,
 388     CS_R23 = 20,
 389     CS_R24 = 21,
 390     CS_R25 = 22,
 391     CS_R26 = 24,
 392     CS_R27 = 25,
 393     CS_R28 = 26,
 394     CS_R29 = 28,
 395     CS_R30 = 29,
 396     CS_R31 = 30,
 397 }
 398 LILAC_RDD_LOCAL_REGISTER_INDEX_DTS;
 399
 400
 401 typedef enum
 402 {
 403     FAST_RUNNER_A = 0,
 404     FAST_RUNNER_B = 1,
 405     PICO_RUNNER_A = 2,
 406     PICO_RUNNER_B = 3,
 407 }
 408 LILAC_RDD_RUNNER_INDEX_DTS;
 409
 410
 411
 412 /**** ingress classification ****/
 413
 414 typedef struct
 415 {
 416     uint32_t    valid;
 417     int32_t     priority;
 418     uint32_t    rule_type;
 419     uint32_t    next_rule_cfg_id;
 420     uint32_t    next_group_id;
 421 }
 422 __PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_RULE_CFG_DTE;
 423
 424
 425 typedef struct
 426 {
 427     uint32_t                                 first_rule_cfg_id;
 428     uint32_t                                 first_gen_filter_rule_cfg_id;
 429     RDD_INGRESS_CLASSIFICATION_RULE_CFG_DTE  rule_cfg[ 16 ];
 430 }
 431 __PACKING_ATTRIBUTE_STRUCT_END__ RDD_INGRESS_CLASSIFICATION_RULE_CFG_TABLE_DTE;
 432
 433
 434
 435 /**** Router definitions ****/
 436
 437 #define LILAC_RDD_CONNECTION_ENTRY_SIZE                 16
 438 #define LILAC_RDD_CONTEXT_ENTRY_SIZE                    sizeof(RDD_CONTEXT_ENTRY_UNION_DTS)
 439 #define LILAC_RDD_CONNECTION_TABLE_SET_SIZE             4
 440 #define LILAC_RDD_RESERVED_CONTEXT_ENTRIES              128
 441
 442 #define PARSER_LAYER4_PROTOCOL_TCP                      1
 443 #define PARSER_LAYER4_PROTOCOL_UDP                      2
 444
 445 /* Offsets must correspond to current rdd_data_structures_auto.h number_of_ports and port_mask offsets. */
 446 #define RDD_FC_MCAST_FLOW_CONTEXT_ENTRY_NUM_PORTS_PORT_MASK_WRITE( v, p ) FIELD_MWRITE_16((uint8_t *)p + 8, 0, 12, v )
 447
 448 typedef struct
 449 {
 450         uint32_t        good_csum_packets               :32     __PACKING_ATTRIBUTE_FIELD_LEVEL__;
 451         uint32_t        no_csum_packets                 :32     __PACKING_ATTRIBUTE_FIELD_LEVEL__;
 452         uint32_t        bad_ipv4_hdr_csum_packets       :32     __PACKING_ATTRIBUTE_FIELD_LEVEL__;
 453         uint32_t        bad_tcp_udp_csum_packets        :32     __PACKING_ATTRIBUTE_FIELD_LEVEL__;
 454 }
 455 __PACKING_ATTRIBUTE_STRUCT_END__ RDD_CSO_COUNTERS_ENTRY_DTS;
 456
 457 #define rdd_phys_addr_t bdmf_phys_addr_t
 458
 459 #endif /*_BL_LILAC_DRV_RUNNER_DATA_STRUCTURES_H */
 460