arch/arm/mach-bcmbca/rdp/rdp_ih.h

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2013 Broadcom
   4  */
   5 /*
   6
   7 */
   8
   9 #ifndef __IH_H_INCLUDED
  10 #define __IH_H_INCLUDED
  11
  12 /*  File automatically generated by Reggae at 15/08/2013  10:54:43   */
  13
  14 #include "access_macros.h"
  15 #include "packing.h"
  16 #include "rdp_map.h"
  17
  18 /*****************************************************************************************/
  19 /* Lilac Ingres Handler. Ingres Handler in Lilac is responsible for incoming ingres traf */
  20 /* fic pre-processing. It includes re-used accelerators from Ginger: Parser & Look-up en */
  21 /* gine. The main features of IH (Ingres Handler) are as following: (1) Runner proccessi */
  22 /* ng offload (Parsing, Lookup engine), (2) Ingres QoS, (3) Target Memory decision: DDR  */
  23 /* or SRAM, (4) Runner load balancing                                                    */
  24 /*****************************************************************************************/
  25
  26 /*****************************************************************************************/
  27 /* Blocks offsets                                                                        */
  28 /*****************************************************************************************/
  29 /*****************************************************************************************/
  30 /* Functions offsets and addresses                                                       */
  31 /*****************************************************************************************/
  32 #define IH_REGS_LOOKUP_CONFIGURATION_OFFSET     ( 0x00000000 )
  33 #define IH_REGS_LOOKUP_CONFIGURATION_ADDRESS    ( IH_REGS_OFFSET + IH_REGS_LOOKUP_CONFIGURATION_OFFSET )
  34
  35 #define IH_REGS_PARSER_CORE_CONFIGURATION_OFFSET        ( 0x00000400 )
  36 #define IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS       ( IH_REGS_OFFSET + IH_REGS_PARSER_CORE_CONFIGURATION_OFFSET )
  37
  38 #define IH_REGS_GENERAL_CONFIGURATION_OFFSET    ( 0x00000800 )
  39 #define IH_REGS_GENERAL_CONFIGURATION_ADDRESS   ( IH_REGS_OFFSET + IH_REGS_GENERAL_CONFIGURATION_OFFSET )
  40
  41 /*   'd' is module index   */
  42 /*   'i' is block index    */
  43 /*   'j' is function index */
  44 /*   'e' is function entry */
  45 /*   'k' is register index */
  46
  47 /*****************************************************************************************/
  48 /* LKUP_TBL0_LUT_CFG                                                                     */
  49 /* Look-up table 0:  Configuration of LUT: table params + main flag                      */
  50 /*****************************************************************************************/
  51
  52 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
  53 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
  54 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
  55 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
  56 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
  57 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
  58 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
  59 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
  60 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
  61 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
  62 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
  63 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
  64 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
  65 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
  66 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
  67 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
  68 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
  69 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
  70 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
  71 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
  72 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
  73 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
  74 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
  75 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
  76 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
  77 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
  78 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
  79 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
  80 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
  81 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
  82 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
  83 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
  84 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
  85 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
  86 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
  87 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
  88 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
  89 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED_RESERVED_VALUE                               ( 0x0 )
  90 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_RESERVED_RESERVED_VALUE_RESET_VALUE                   ( 0x0 )
  91 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
  92 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
  93
  94
  95 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_OFFSET ( 0x00000000 )
  96
  97 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_OFFSET )
  98 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_ADDRESS ), (r) )
  99 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG_ADDRESS ), (v) )
 100
 101 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 102 typedef struct
 103 {
 104         /* Reserved */
 105         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 106
 107         /* five_tuple_en */
 108         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 109
 110         /* aging_en */
 111         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 112
 113         /* sa_search_en */
 114         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 115
 116         /* Max_Hop */
 117         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 118
 119         /* Hash_Type */
 120         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 121
 122         /* Table_Size */
 123         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 124
 125         /* RESERVED */
 126         uint32_t reserved       : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 127
 128         /* Table_base_address */
 129         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 130 }
 131 __PACKING_ATTRIBUTE_STRUCT_END__
 132 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG ;
 133 #else
 134 typedef struct
 135 {
 136         /* Table_base_address */
 137         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 138
 139         /* RESERVED */
 140         uint32_t reserved       : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 141
 142         /* Table_Size */
 143         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 144
 145         /* Hash_Type */
 146         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 147
 148         /* Max_Hop */
 149         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 150
 151         /* sa_search_en */
 152         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 153
 154         /* aging_en */
 155         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 156
 157         /* five_tuple_en */
 158         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 159
 160         /* Reserved */
 161         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 162 }
 163 __PACKING_ATTRIBUTE_STRUCT_END__
 164 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG ;
 165 #endif
 166
 167 /*****************************************************************************************/
 168 /* LKUP_TBL1_LUT_CFG                                                                     */
 169 /* Look-up table 1:  Configuration of LUT: table params + main flags                     */
 170 /*****************************************************************************************/
 171
 172 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
 173 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
 174 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
 175 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
 176 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
 177 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
 178 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
 179 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
 180 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
 181 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
 182 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
 183 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
 184 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
 185 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
 186 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
 187 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
 188 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
 189 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
 190 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
 191 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
 192 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
 193 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
 194 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
 195 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
 196 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
 197 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
 198 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
 199 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
 200 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
 201 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
 202 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
 203 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
 204 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
 205 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
 206 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
 207 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
 208 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
 209 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
 210 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
 211 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
 212 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
 213
 214
 215 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_OFFSET ( 0x00000004 )
 216
 217 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_OFFSET )
 218 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_ADDRESS ), (r) )
 219 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG_ADDRESS ), (v) )
 220
 221 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 222 typedef struct
 223 {
 224         /* Reserved */
 225         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 226
 227         /* five_tuple_en */
 228         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 229
 230         /* aging_en */
 231         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 232
 233         /* sa_search_en */
 234         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 235
 236         /* Max_Hop */
 237         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 238
 239         /* Hash_Type */
 240         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 241
 242         /* Table_Size */
 243         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 244
 245         /* RESERVED */
 246         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 247
 248         /* Table_base_address */
 249         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 250 }
 251 __PACKING_ATTRIBUTE_STRUCT_END__
 252 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG ;
 253 #else
 254 typedef struct
 255 {
 256         /* Table_base_address */
 257         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 258
 259         /* RESERVED */
 260         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 261
 262         /* Table_Size */
 263         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 264
 265         /* Hash_Type */
 266         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 267
 268         /* Max_Hop */
 269         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 270
 271         /* sa_search_en */
 272         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 273
 274         /* aging_en */
 275         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 276
 277         /* five_tuple_en */
 278         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 279
 280         /* Reserved */
 281         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 282 }
 283 __PACKING_ATTRIBUTE_STRUCT_END__
 284 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG ;
 285 #endif
 286
 287 /*****************************************************************************************/
 288 /* LKUP_TBL2_LUT_CFG                                                                     */
 289 /* Look-up table 2:  Configuration of LUT: table params + main flags                     */
 290 /*****************************************************************************************/
 291
 292 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
 293 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
 294 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
 295 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
 296 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
 297 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
 298 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
 299 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
 300 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
 301 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
 302 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
 303 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
 304 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
 305 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
 306 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
 307 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
 308 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
 309 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
 310 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
 311 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
 312 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
 313 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
 314 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
 315 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
 316 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
 317 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
 318 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
 319 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
 320 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
 321 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
 322 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
 323 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
 324 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
 325 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
 326 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
 327 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
 328 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
 329 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
 330 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
 331 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
 332 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
 333
 334
 335 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_OFFSET ( 0x00000008 )
 336
 337 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_OFFSET )
 338 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_ADDRESS ), (r) )
 339 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG_ADDRESS ), (v) )
 340
 341 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 342 typedef struct
 343 {
 344         /* Reserved */
 345         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 346
 347         /* five_tuple_en */
 348         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 349
 350         /* aging_en */
 351         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 352
 353         /* sa_search_en */
 354         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 355
 356         /* Max_Hop */
 357         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 358
 359         /* Hash_Type */
 360         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 361
 362         /* Table_Size */
 363         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 364
 365         /* RESERVED */
 366         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 367
 368         /* Table_base_address */
 369         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 370 }
 371 __PACKING_ATTRIBUTE_STRUCT_END__
 372 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG ;
 373 #else
 374 typedef struct
 375 {
 376         /* Table_base_address */
 377         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 378
 379         /* RESERVED */
 380         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 381
 382         /* Table_Size */
 383         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 384
 385         /* Hash_Type */
 386         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 387
 388         /* Max_Hop */
 389         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 390
 391         /* sa_search_en */
 392         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 393
 394         /* aging_en */
 395         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 396
 397         /* five_tuple_en */
 398         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 399
 400         /* Reserved */
 401         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 402 }
 403 __PACKING_ATTRIBUTE_STRUCT_END__
 404 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG ;
 405 #endif
 406
 407 /*****************************************************************************************/
 408 /* LKUP_TBL3_LUT_CFG                                                                     */
 409 /* Look-up table 3:  Configuration of LUT: table params + main flags                     */
 410 /*****************************************************************************************/
 411
 412 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
 413 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
 414 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
 415 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
 416 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
 417 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
 418 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
 419 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
 420 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
 421 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
 422 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
 423 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
 424 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
 425 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
 426 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
 427 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
 428 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
 429 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
 430 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
 431 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
 432 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
 433 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
 434 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
 435 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
 436 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
 437 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
 438 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
 439 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
 440 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
 441 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
 442 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
 443 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
 444 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
 445 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
 446 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
 447 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
 448 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
 449 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
 450 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
 451 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
 452 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
 453
 454
 455 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_OFFSET ( 0x0000000C )
 456
 457 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_OFFSET )
 458 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_ADDRESS ), (r) )
 459 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG_ADDRESS ), (v) )
 460
 461 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 462 typedef struct
 463 {
 464         /* Reserved */
 465         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 466
 467         /* five_tuple_en */
 468         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 469
 470         /* aging_en */
 471         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 472
 473         /* sa_search_en */
 474         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 475
 476         /* Max_Hop */
 477         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 478
 479         /* Hash_Type */
 480         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 481
 482         /* Table_Size */
 483         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 484
 485         /* RESERVED */
 486         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 487
 488         /* Table_base_address */
 489         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 490 }
 491 __PACKING_ATTRIBUTE_STRUCT_END__
 492 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG ;
 493 #else
 494 typedef struct
 495 {
 496         /* Table_base_address */
 497         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 498
 499         /* RESERVED */
 500         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 501
 502         /* Table_Size */
 503         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 504
 505         /* Hash_Type */
 506         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 507
 508         /* Max_Hop */
 509         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 510
 511         /* sa_search_en */
 512         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 513
 514         /* aging_en */
 515         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 516
 517         /* five_tuple_en */
 518         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 519
 520         /* Reserved */
 521         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 522 }
 523 __PACKING_ATTRIBUTE_STRUCT_END__
 524 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG ;
 525 #endif
 526
 527 /*****************************************************************************************/
 528 /* LKUP_TBL4_LUT_CFG                                                                     */
 529 /* Look-up table 4:  Configuration of LUT: table params + main flags                     */
 530 /*****************************************************************************************/
 531
 532 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
 533 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
 534 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
 535 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
 536 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
 537 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
 538 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
 539 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
 540 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
 541 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
 542 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
 543 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
 544 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
 545 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
 546 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
 547 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
 548 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
 549 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
 550 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
 551 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
 552 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
 553 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
 554 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
 555 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
 556 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
 557 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
 558 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
 559 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
 560 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
 561 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
 562 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
 563 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
 564 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
 565 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
 566 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
 567 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
 568 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
 569 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
 570 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
 571 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
 572 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
 573
 574
 575 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_OFFSET ( 0x00000010 )
 576
 577 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_OFFSET )
 578 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_ADDRESS ), (r) )
 579 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG_ADDRESS ), (v) )
 580
 581 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 582 typedef struct
 583 {
 584         /* Reserved */
 585         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 586
 587         /* five_tuple_en */
 588         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 589
 590         /* aging_en */
 591         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 592
 593         /* sa_search_en */
 594         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 595
 596         /* Max_Hop */
 597         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 598
 599         /* Hash_Type */
 600         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 601
 602         /* Table_Size */
 603         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 604
 605         /* RESERVED */
 606         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 607
 608         /* Table_base_address */
 609         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 610 }
 611 __PACKING_ATTRIBUTE_STRUCT_END__
 612 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG ;
 613 #else
 614 typedef struct
 615 {
 616         /* Table_base_address */
 617         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 618
 619         /* RESERVED */
 620         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 621
 622         /* Table_Size */
 623         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 624
 625         /* Hash_Type */
 626         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 627
 628         /* Max_Hop */
 629         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 630
 631         /* sa_search_en */
 632         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 633
 634         /* aging_en */
 635         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 636
 637         /* five_tuple_en */
 638         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 639
 640         /* Reserved */
 641         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 642 }
 643 __PACKING_ATTRIBUTE_STRUCT_END__
 644 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG ;
 645 #endif
 646
 647 /*****************************************************************************************/
 648 /* LKUP_TBL5_LUT_CFG                                                                     */
 649 /* Look-up table 5:  Configuration of LUT: table params + main flags                     */
 650 /*****************************************************************************************/
 651
 652 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
 653 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
 654 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
 655 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
 656 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
 657 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
 658 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
 659 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
 660 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
 661 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
 662 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
 663 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
 664 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
 665 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
 666 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
 667 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
 668 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
 669 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
 670 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
 671 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
 672 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
 673 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
 674 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
 675 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
 676 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
 677 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
 678 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
 679 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
 680 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
 681 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
 682 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
 683 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
 684 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
 685 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
 686 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
 687 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
 688 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
 689 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
 690 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
 691 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
 692 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
 693
 694
 695 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_OFFSET ( 0x00000014 )
 696
 697 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_OFFSET )
 698 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_ADDRESS ), (r) )
 699 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG_ADDRESS ), (v) )
 700
 701 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 702 typedef struct
 703 {
 704         /* Reserved */
 705         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 706
 707         /* five_tuple_en */
 708         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 709
 710         /* aging_en */
 711         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 712
 713         /* sa_search_en */
 714         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 715
 716         /* Max_Hop */
 717         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 718
 719         /* Hash_Type */
 720         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 721
 722         /* Table_Size */
 723         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 724
 725         /* RESERVED */
 726         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 727
 728         /* Table_base_address */
 729         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 730 }
 731 __PACKING_ATTRIBUTE_STRUCT_END__
 732 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG ;
 733 #else
 734 typedef struct
 735 {
 736         /* Table_base_address */
 737         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 738
 739         /* RESERVED */
 740         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 741
 742         /* Table_Size */
 743         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 744
 745         /* Hash_Type */
 746         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 747
 748         /* Max_Hop */
 749         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 750
 751         /* sa_search_en */
 752         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 753
 754         /* aging_en */
 755         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 756
 757         /* five_tuple_en */
 758         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 759
 760         /* Reserved */
 761         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 762 }
 763 __PACKING_ATTRIBUTE_STRUCT_END__
 764 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG ;
 765 #endif
 766
 767 /*****************************************************************************************/
 768 /* LKUP_TBL6_LUT_CFG                                                                     */
 769 /* Look-up table 6:  Configuration of LUT: table params + main flags                     */
 770 /*****************************************************************************************/
 771
 772 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
 773 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
 774 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
 775 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
 776 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
 777 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
 778 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
 779 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
 780 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
 781 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
 782 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
 783 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
 784 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
 785 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
 786 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
 787 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
 788 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
 789 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
 790 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
 791 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
 792 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
 793 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
 794 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
 795 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
 796 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
 797 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
 798 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
 799 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
 800 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
 801 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
 802 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
 803 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
 804 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
 805 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
 806 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
 807 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
 808 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
 809 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
 810 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
 811 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
 812 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
 813
 814
 815 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_OFFSET ( 0x00000018 )
 816
 817 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_OFFSET )
 818 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_ADDRESS ), (r) )
 819 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG_ADDRESS ), (v) )
 820
 821 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 822 typedef struct
 823 {
 824         /* Reserved */
 825         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 826
 827         /* five_tuple_en */
 828         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 829
 830         /* aging_en */
 831         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 832
 833         /* sa_search_en */
 834         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 835
 836         /* Max_Hop */
 837         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 838
 839         /* Hash_Type */
 840         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 841
 842         /* Table_Size */
 843         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 844
 845         /* RESERVED */
 846         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 847
 848         /* Table_base_address */
 849         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 850 }
 851 __PACKING_ATTRIBUTE_STRUCT_END__
 852 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG ;
 853 #else
 854 typedef struct
 855 {
 856         /* Table_base_address */
 857         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 858
 859         /* RESERVED */
 860         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 861
 862         /* Table_Size */
 863         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 864
 865         /* Hash_Type */
 866         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 867
 868         /* Max_Hop */
 869         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 870
 871         /* sa_search_en */
 872         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 873
 874         /* aging_en */
 875         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 876
 877         /* five_tuple_en */
 878         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 879
 880         /* Reserved */
 881         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 882 }
 883 __PACKING_ATTRIBUTE_STRUCT_END__
 884 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG ;
 885 #endif
 886
 887 /*****************************************************************************************/
 888 /* LKUP_TBL7_LUT_CFG                                                                     */
 889 /* Look-up table 7:  Configuration of LUT: table params + main flags                     */
 890 /*****************************************************************************************/
 891
 892 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
 893 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
 894 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
 895 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
 896 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
 897 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
 898 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
 899 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
 900 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
 901 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
 902 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
 903 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
 904 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
 905 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
 906 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
 907 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
 908 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
 909 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
 910 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
 911 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
 912 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
 913 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
 914 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
 915 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
 916 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
 917 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
 918 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
 919 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
 920 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
 921 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
 922 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
 923 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
 924 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
 925 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
 926 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
 927 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
 928 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
 929 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
 930 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
 931 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
 932 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
 933
 934
 935 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_OFFSET ( 0x0000001C )
 936
 937 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_OFFSET )
 938 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_ADDRESS ), (r) )
 939 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG_ADDRESS ), (v) )
 940
 941 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
 942 typedef struct
 943 {
 944         /* Reserved */
 945         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 946
 947         /* five_tuple_en */
 948         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 949
 950         /* aging_en */
 951         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 952
 953         /* sa_search_en */
 954         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 955
 956         /* Max_Hop */
 957         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 958
 959         /* Hash_Type */
 960         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 961
 962         /* Table_Size */
 963         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 964
 965         /* Reserved */
 966         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 967
 968         /* Table_base_address */
 969         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 970 }
 971 __PACKING_ATTRIBUTE_STRUCT_END__
 972 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG ;
 973 #else
 974 typedef struct
 975 {
 976         /* Table_base_address */
 977         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 978
 979         /* Reserved */
 980         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 981
 982         /* Table_Size */
 983         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 984
 985         /* Hash_Type */
 986         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 987
 988         /* Max_Hop */
 989         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 990
 991         /* sa_search_en */
 992         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 993
 994         /* aging_en */
 995         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 996
 997         /* five_tuple_en */
 998         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
 999
1000         /* Reserved */
1001         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1002 }
1003 __PACKING_ATTRIBUTE_STRUCT_END__
1004 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG ;
1005 #endif
1006
1007 /*****************************************************************************************/
1008 /* LKUP_TBL8_LUT_CFG                                                                     */
1009 /* Look-up table 8:  Configuration of LUT: table params + main flags                     */
1010 /*****************************************************************************************/
1011
1012 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
1013 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
1014 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
1015 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
1016 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
1017 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
1018 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
1019 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
1020 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
1021 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
1022 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
1023 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
1024 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
1025 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
1026 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
1027 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
1028 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
1029 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
1030 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
1031 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
1032 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
1033 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
1034 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
1035 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
1036 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
1037 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
1038 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
1039 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
1040 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
1041 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
1042 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
1043 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
1044 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
1045 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
1046 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
1047 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
1048 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
1049 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
1050 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
1051 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
1052 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
1053
1054
1055 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_OFFSET ( 0x00000020 )
1056
1057 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_OFFSET )
1058 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_ADDRESS ), (r) )
1059 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG_ADDRESS ), (v) )
1060
1061 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1062 typedef struct
1063 {
1064         /* Reserved */
1065         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1066
1067         /* five_tuple_en */
1068         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1069
1070         /* aging_en */
1071         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1072
1073         /* sa_search_en */
1074         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1075
1076         /* Max_Hop */
1077         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1078
1079         /* Hash_Type */
1080         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1081
1082         /* Table_Size */
1083         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1084
1085         /* Reserved */
1086         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1087
1088         /* Table_base_address */
1089         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1090 }
1091 __PACKING_ATTRIBUTE_STRUCT_END__
1092 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG ;
1093 #else
1094 typedef struct
1095 {
1096         /* Table_base_address */
1097         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1098
1099         /* Reserved */
1100         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1101
1102         /* Table_Size */
1103         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1104
1105         /* Hash_Type */
1106         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1107
1108         /* Max_Hop */
1109         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1110
1111         /* sa_search_en */
1112         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1113
1114         /* aging_en */
1115         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1116
1117         /* five_tuple_en */
1118         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1119
1120         /* Reserved */
1121         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1122 }
1123 __PACKING_ATTRIBUTE_STRUCT_END__
1124 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG ;
1125 #endif
1126
1127 /*****************************************************************************************/
1128 /* LKUP_TBL9_LUT_CFG                                                                     */
1129 /* Look-up table 9:  Configuration of LUT: table params + main flags                     */
1130 /*****************************************************************************************/
1131
1132 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_RESERVED1_RESERVED_VALUE                              ( 0x0 )
1133 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE                  ( 0x0 )
1134 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE                     ( 0x0 )
1135 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_FIVE_TUPLE_EN_FIVE_TUPLE_EN_VALUE_RESET_VALUE         ( 0x0 )
1136 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_AGING_EN_AGING_EN_VALUE                               ( 0x0 )
1137 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_AGING_EN_AGING_EN_VALUE_RESET_VALUE                   ( 0x0 )
1138 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE                       ( 0x0 )
1139 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_SA_SEARCH_EN_SA_SEARCH_EN_VALUE_RESET_VALUE           ( 0x0 )
1140 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE                              ( 0x0 )
1141 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_1_STEP_VALUE_RESET_VALUE                  ( 0x0 )
1142 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_2_STEPS_VALUE                             ( 0x1 )
1143 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_4_STEPS_VALUE                             ( 0x2 )
1144 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_8_STEPS_VALUE                             ( 0x3 )
1145 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_16_STEPS_VALUE                            ( 0x4 )
1146 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_32_STEPS_VALUE                            ( 0x5 )
1147 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_64_STEPS_VALUE                            ( 0x6 )
1148 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_128_STEPS_VALUE                           ( 0x7 )
1149 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_256_STEPS_VALUE                           ( 0x8 )
1150 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_512_STEPS_VALUE                           ( 0x9 )
1151 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_MAX_1K_STEPS_VALUE                            ( 0xA )
1152 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED0_VALUE                               ( 0xB )
1153 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED1_VALUE                               ( 0xC )
1154 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED2_VALUE                               ( 0xD )
1155 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED3_VALUE                               ( 0xE )
1156 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_MAX_HOP_RESERVED4_VALUE                               ( 0xF )
1157 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE             ( 0x0 )
1158 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_HASH_TYPE_HASH_FOR_INCREMENTAL_KEYS_VALUE_RESET_VALUE ( 0x0 )
1159 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_HASH_TYPE_CRC16_VALUE                                 ( 0x1 )
1160 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE                       ( 0x0 )
1161 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_32_ENTRIES_VALUE_RESET_VALUE           ( 0x0 )
1162 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_64_ENTRIES_VALUE                       ( 0x1 )
1163 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_128_ENTRIES_VALUE                      ( 0x2 )
1164 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_256_ENTRIES_VALUE                      ( 0x3 )
1165 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_512_ENTRIES_VALUE                      ( 0x4 )
1166 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_1K_ENTRIES_VALUE                       ( 0x5 )
1167 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_2K_ENTRIES_VALUE                       ( 0x6 )
1168 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_TABLE_SIZE_MAX_4K_ENTRIES_VALUE                       ( 0x7 )
1169 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_R2_RESERVED_VALUE                                     ( 0x0 )
1170 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_R2_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
1171 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
1172 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
1173
1174
1175 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_OFFSET ( 0x00000024 )
1176
1177 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_OFFSET )
1178 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_ADDRESS ), (r) )
1179 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG_ADDRESS ), (v) )
1180
1181 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1182 typedef struct
1183 {
1184         /* Reserved */
1185         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1186
1187         /* five_tuple_en */
1188         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1189
1190         /* aging_en */
1191         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1192
1193         /* sa_search_en */
1194         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1195
1196         /* Max_Hop */
1197         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1198
1199         /* Hash_Type */
1200         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1201
1202         /* Table_Size */
1203         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1204
1205         /* Reserved */
1206         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1207
1208         /* Table_base_address */
1209         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1210 }
1211 __PACKING_ATTRIBUTE_STRUCT_END__
1212 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG ;
1213 #else
1214 typedef struct
1215 {
1216         /* Table_base_address */
1217         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1218
1219         /* Reserved */
1220         uint32_t r2             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1221
1222         /* Table_Size */
1223         uint32_t table_size     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1224
1225         /* Hash_Type */
1226         uint32_t hash_type      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1227
1228         /* Max_Hop */
1229         uint32_t max_hop        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1230
1231         /* sa_search_en */
1232         uint32_t sa_search_en   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1233
1234         /* aging_en */
1235         uint32_t aging_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1236
1237         /* five_tuple_en */
1238         uint32_t five_tuple_en  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1239
1240         /* Reserved */
1241         uint32_t reserved1      : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1242 }
1243 __PACKING_ATTRIBUTE_STRUCT_END__
1244 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG ;
1245 #endif
1246
1247 /*****************************************************************************************/
1248 /* LKUP_TBL0_CAM_CFG                                                                     */
1249 /* Look-up table 0: CAM configurations (base addr + cam extention enable)                */
1250 /*****************************************************************************************/
1251
1252 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1253 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1254 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1255 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1256 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1257 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1258 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1259 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1260 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1261
1262
1263 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_OFFSET ( 0x00000028 )
1264
1265 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_OFFSET )
1266 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_ADDRESS ), (r) )
1267 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG_ADDRESS ), (v) )
1268
1269 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1270 typedef struct
1271 {
1272         /* Resreved */
1273         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1274
1275         /* CAM_enable */
1276         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1277
1278         /* Reserved */
1279         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1280
1281         /* Base_Address */
1282         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1283 }
1284 __PACKING_ATTRIBUTE_STRUCT_END__
1285 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG ;
1286 #else
1287 typedef struct
1288 {
1289         /* Base_Address */
1290         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1291
1292         /* Reserved */
1293         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1294
1295         /* CAM_enable */
1296         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1297
1298         /* Resreved */
1299         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1300 }
1301 __PACKING_ATTRIBUTE_STRUCT_END__
1302 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG ;
1303 #endif
1304
1305 /*****************************************************************************************/
1306 /* LKUP_TBL1_CAM_CFG                                                                     */
1307 /* Look-up table 1: CAM configurations (base CAM addr + CAM extention enable)            */
1308 /*****************************************************************************************/
1309
1310 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1311 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1312 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1313 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1314 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1315 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1316 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1317 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1318 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1319
1320
1321 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_OFFSET ( 0x0000002C )
1322
1323 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_OFFSET )
1324 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_ADDRESS ), (r) )
1325 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG_ADDRESS ), (v) )
1326
1327 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1328 typedef struct
1329 {
1330         /* Resreved */
1331         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1332
1333         /* CAM_enable */
1334         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1335
1336         /* Reserved */
1337         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1338
1339         /* Base_Address */
1340         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1341 }
1342 __PACKING_ATTRIBUTE_STRUCT_END__
1343 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG ;
1344 #else
1345 typedef struct
1346 {
1347         /* Base_Address */
1348         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1349
1350         /* Reserved */
1351         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1352
1353         /* CAM_enable */
1354         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1355
1356         /* Resreved */
1357         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1358 }
1359 __PACKING_ATTRIBUTE_STRUCT_END__
1360 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG ;
1361 #endif
1362
1363 /*****************************************************************************************/
1364 /* LKUP_TBL2_CAM_CFG                                                                     */
1365 /* Look-up table 2: CAM configurations (base addr + cam extention enable)                */
1366 /*****************************************************************************************/
1367
1368 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1369 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1370 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1371 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1372 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1373 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1374 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1375 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1376 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1377
1378
1379 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_OFFSET ( 0x00000030 )
1380
1381 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_OFFSET )
1382 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_ADDRESS ), (r) )
1383 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG_ADDRESS ), (v) )
1384
1385 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1386 typedef struct
1387 {
1388         /* Resreved */
1389         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1390
1391         /* CAM_enable */
1392         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1393
1394         /* Reserved */
1395         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1396
1397         /* Base_Address */
1398         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1399 }
1400 __PACKING_ATTRIBUTE_STRUCT_END__
1401 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG ;
1402 #else
1403 typedef struct
1404 {
1405         /* Base_Address */
1406         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1407
1408         /* Reserved */
1409         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1410
1411         /* CAM_enable */
1412         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1413
1414         /* Resreved */
1415         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1416 }
1417 __PACKING_ATTRIBUTE_STRUCT_END__
1418 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG ;
1419 #endif
1420
1421 /*****************************************************************************************/
1422 /* LKUP_TBL3_CAM_CFG                                                                     */
1423 /* Look-up table 3: CAM configurations (CAM base addr + CAM extention enable)            */
1424 /*****************************************************************************************/
1425
1426 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1427 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1428 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1429 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1430 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1431 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1432 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1433 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1434 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1435
1436
1437 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_OFFSET ( 0x00000034 )
1438
1439 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_OFFSET )
1440 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_ADDRESS ), (r) )
1441 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG_ADDRESS ), (v) )
1442
1443 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1444 typedef struct
1445 {
1446         /* Resreved */
1447         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1448
1449         /* CAM_enable */
1450         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1451
1452         /* Reserved */
1453         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1454
1455         /* Base_Address */
1456         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1457 }
1458 __PACKING_ATTRIBUTE_STRUCT_END__
1459 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG ;
1460 #else
1461 typedef struct
1462 {
1463         /* Base_Address */
1464         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1465
1466         /* Reserved */
1467         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1468
1469         /* CAM_enable */
1470         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1471
1472         /* Resreved */
1473         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1474 }
1475 __PACKING_ATTRIBUTE_STRUCT_END__
1476 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG ;
1477 #endif
1478
1479 /*****************************************************************************************/
1480 /* LKUP_TBL4_CAM_CFG                                                                     */
1481 /* Look-up table 4: CAM configurations (CAM base addr + CAM extention enable)            */
1482 /*****************************************************************************************/
1483
1484 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1485 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1486 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1487 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1488 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1489 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1490 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1491 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1492 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1493
1494
1495 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_OFFSET ( 0x00000038 )
1496
1497 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_OFFSET )
1498 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_ADDRESS ), (r) )
1499 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG_ADDRESS ), (v) )
1500
1501 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1502 typedef struct
1503 {
1504         /* Resreved */
1505         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1506
1507         /* CAM_enable */
1508         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1509
1510         /* Reserved */
1511         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1512
1513         /* Base_Address */
1514         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1515 }
1516 __PACKING_ATTRIBUTE_STRUCT_END__
1517 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG ;
1518 #else
1519 typedef struct
1520 {
1521         /* Base_Address */
1522         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1523
1524         /* Reserved */
1525         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1526
1527         /* CAM_enable */
1528         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1529
1530         /* Resreved */
1531         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1532 }
1533 __PACKING_ATTRIBUTE_STRUCT_END__
1534 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG ;
1535 #endif
1536
1537 /*****************************************************************************************/
1538 /* LKUP_TBL5_CAM_CFG                                                                     */
1539 /* Look-up table 5: CAM configurations (CAM base addr + CAM extention enable)            */
1540 /*****************************************************************************************/
1541
1542 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1543 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1544 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1545 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1546 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1547 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1548 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1549 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1550 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1551
1552
1553 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_OFFSET ( 0x0000003C )
1554
1555 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_OFFSET )
1556 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_ADDRESS ), (r) )
1557 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG_ADDRESS ), (v) )
1558
1559 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1560 typedef struct
1561 {
1562         /* Resreved */
1563         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1564
1565         /* CAM_enable */
1566         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1567
1568         /* Reserved */
1569         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1570
1571         /* Base_Address */
1572         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1573 }
1574 __PACKING_ATTRIBUTE_STRUCT_END__
1575 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG ;
1576 #else
1577 typedef struct
1578 {
1579         /* Base_Address */
1580         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1581
1582         /* Reserved */
1583         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1584
1585         /* CAM_enable */
1586         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1587
1588         /* Resreved */
1589         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1590 }
1591 __PACKING_ATTRIBUTE_STRUCT_END__
1592 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG ;
1593 #endif
1594
1595 /*****************************************************************************************/
1596 /* LKUP_TBL6_CAM_CFG                                                                     */
1597 /* Look-up table 6: CAM configurations (CAM base addr + CAM extention enable)            */
1598 /*****************************************************************************************/
1599
1600 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1601 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1602 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1603 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1604 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1605 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1606 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1607 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1608 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1609
1610
1611 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_OFFSET ( 0x00000040 )
1612
1613 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_OFFSET )
1614 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_ADDRESS ), (r) )
1615 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG_ADDRESS ), (v) )
1616
1617 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1618 typedef struct
1619 {
1620         /* Resreved */
1621         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1622
1623         /* CAM_enable */
1624         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1625
1626         /* Reserved */
1627         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1628
1629         /* Base_Address */
1630         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1631 }
1632 __PACKING_ATTRIBUTE_STRUCT_END__
1633 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG ;
1634 #else
1635 typedef struct
1636 {
1637         /* Base_Address */
1638         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1639
1640         /* Reserved */
1641         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1642
1643         /* CAM_enable */
1644         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1645
1646         /* Resreved */
1647         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1648 }
1649 __PACKING_ATTRIBUTE_STRUCT_END__
1650 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG ;
1651 #endif
1652
1653 /*****************************************************************************************/
1654 /* LKUP_TBL7_CAM_CFG                                                                     */
1655 /* Look-up table 7: CAM configurations (CAM base addr + CAM extention enable)            */
1656 /*****************************************************************************************/
1657
1658 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1659 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1660 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1661 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1662 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1663 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1664 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1665 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1666 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1667
1668
1669 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_OFFSET ( 0x00000044 )
1670
1671 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_OFFSET )
1672 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_ADDRESS ), (r) )
1673 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG_ADDRESS ), (v) )
1674
1675 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1676 typedef struct
1677 {
1678         /* Resreved */
1679         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1680
1681         /* CAM_enable */
1682         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1683
1684         /* Reserved */
1685         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1686
1687         /* Base_Address */
1688         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1689 }
1690 __PACKING_ATTRIBUTE_STRUCT_END__
1691 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG ;
1692 #else
1693 typedef struct
1694 {
1695         /* Base_Address */
1696         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1697
1698         /* Reserved */
1699         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1700
1701         /* CAM_enable */
1702         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1703
1704         /* Resreved */
1705         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1706 }
1707 __PACKING_ATTRIBUTE_STRUCT_END__
1708 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG ;
1709 #endif
1710
1711 /*****************************************************************************************/
1712 /* LKUP_TBL8_CAM_CFG                                                                     */
1713 /* Look-up table 8: CAM configurations (CAM base addr + CAM extention enable)            */
1714 /*****************************************************************************************/
1715
1716 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1717 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1718 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1719 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1720 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1721 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1722 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1723 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1724 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1725
1726
1727 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_OFFSET ( 0x00000048 )
1728
1729 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_OFFSET )
1730 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_ADDRESS ), (r) )
1731 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG_ADDRESS ), (v) )
1732
1733 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1734 typedef struct
1735 {
1736         /* Resreved */
1737         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1738
1739         /* CAM_enable */
1740         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1741
1742         /* Reserved */
1743         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1744
1745         /* Base_Address */
1746         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1747 }
1748 __PACKING_ATTRIBUTE_STRUCT_END__
1749 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG ;
1750 #else
1751 typedef struct
1752 {
1753         /* Base_Address */
1754         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1755
1756         /* Reserved */
1757         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1758
1759         /* CAM_enable */
1760         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1761
1762         /* Resreved */
1763         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1764 }
1765 __PACKING_ATTRIBUTE_STRUCT_END__
1766 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG ;
1767 #endif
1768
1769 /*****************************************************************************************/
1770 /* LKUP_TBL9_CAM_CFG                                                                     */
1771 /* Look-up table 9: CAM configurations (CAM base addr + CAM extention enable)            */
1772 /*****************************************************************************************/
1773
1774 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
1775 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
1776 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE              ( 0x0 )
1777 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_CAM_EN_CAM_DISABLED_VALUE_RESET_VALUE  ( 0x0 )
1778 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_CAM_EN_CAM_ENABLED_VALUE               ( 0x1 )
1779 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_R1_RESERVED_VALUE                      ( 0x0 )
1780 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_R1_RESERVED_VALUE_RESET_VALUE          ( 0x0 )
1781 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
1782 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
1783
1784
1785 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_OFFSET ( 0x0000004C )
1786
1787 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_OFFSET )
1788 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_ADDRESS ), (r) )
1789 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG_ADDRESS ), (v) )
1790
1791 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1792 typedef struct
1793 {
1794         /* Resreved */
1795         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1796
1797         /* CAM_enable */
1798         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1799
1800         /* Reserved */
1801         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1802
1803         /* Base_Address */
1804         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1805 }
1806 __PACKING_ATTRIBUTE_STRUCT_END__
1807 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG ;
1808 #else
1809 typedef struct
1810 {
1811         /* Base_Address */
1812         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1813
1814         /* Reserved */
1815         uint32_t r1             : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1816
1817         /* CAM_enable */
1818         uint32_t cam_en         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1819
1820         /* Resreved */
1821         uint32_t resreved1      : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1822 }
1823 __PACKING_ATTRIBUTE_STRUCT_END__
1824 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG ;
1825 #endif
1826
1827 /*****************************************************************************************/
1828 /* LKUP_TBL0_LUT_CNXT_CFG                                                                */
1829 /* Look-up table 0: LUT Context Table configurations (base addr + entry context size)    */
1830 /*****************************************************************************************/
1831
1832 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
1833 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
1834 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
1835 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
1836 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
1837 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
1838 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
1839 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
1840 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
1841 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
1842 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
1843
1844
1845 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_OFFSET ( 0x00000050 )
1846
1847 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_OFFSET )
1848 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_ADDRESS ), (r) )
1849 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG_ADDRESS ), (v) )
1850
1851 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1852 typedef struct
1853 {
1854         /* Resreved */
1855         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1856
1857         /* Context_entry_size */
1858         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1859
1860         /* Reserved */
1861         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1862
1863         /* Base_Address */
1864         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1865 }
1866 __PACKING_ATTRIBUTE_STRUCT_END__
1867 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG ;
1868 #else
1869 typedef struct
1870 {
1871         /* Base_Address */
1872         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1873
1874         /* Reserved */
1875         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1876
1877         /* Context_entry_size */
1878         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1879
1880         /* Resreved */
1881         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1882 }
1883 __PACKING_ATTRIBUTE_STRUCT_END__
1884 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG ;
1885 #endif
1886
1887 /*****************************************************************************************/
1888 /* LKUP_TBL1_LUT_CNXT_CFG                                                                */
1889 /* Look-up table 1: LUT Context Table configurations (base addr + entry context size)    */
1890 /*****************************************************************************************/
1891
1892 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
1893 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
1894 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
1895 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
1896 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
1897 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
1898 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
1899 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
1900 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
1901 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
1902 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
1903
1904
1905 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_OFFSET ( 0x00000054 )
1906
1907 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_OFFSET )
1908 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_ADDRESS ), (r) )
1909 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG_ADDRESS ), (v) )
1910
1911 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1912 typedef struct
1913 {
1914         /* Resreved */
1915         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1916
1917         /* Context_entry_size */
1918         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1919
1920         /* Reserved */
1921         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1922
1923         /* Base_Address */
1924         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1925 }
1926 __PACKING_ATTRIBUTE_STRUCT_END__
1927 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG ;
1928 #else
1929 typedef struct
1930 {
1931         /* Base_Address */
1932         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1933
1934         /* Reserved */
1935         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1936
1937         /* Context_entry_size */
1938         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1939
1940         /* Resreved */
1941         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1942 }
1943 __PACKING_ATTRIBUTE_STRUCT_END__
1944 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG ;
1945 #endif
1946
1947 /*****************************************************************************************/
1948 /* LKUP_TBL2_LUT_CNXT_CFG                                                                */
1949 /* Look-up table 2: LUT Context Table configurations (base addr + entry context size)    */
1950 /*****************************************************************************************/
1951
1952 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
1953 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
1954 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
1955 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
1956 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
1957 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
1958 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
1959 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
1960 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
1961 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
1962 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
1963
1964
1965 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_OFFSET ( 0x00000058 )
1966
1967 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_OFFSET )
1968 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_ADDRESS ), (r) )
1969 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG_ADDRESS ), (v) )
1970
1971 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
1972 typedef struct
1973 {
1974         /* Resreved */
1975         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1976
1977         /* Context_entry_size */
1978         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1979
1980         /* Reserved */
1981         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1982
1983         /* Base_Address */
1984         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1985 }
1986 __PACKING_ATTRIBUTE_STRUCT_END__
1987 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG ;
1988 #else
1989 typedef struct
1990 {
1991         /* Base_Address */
1992         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1993
1994         /* Reserved */
1995         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1996
1997         /* Context_entry_size */
1998         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
1999
2000         /* Resreved */
2001         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2002 }
2003 __PACKING_ATTRIBUTE_STRUCT_END__
2004 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG ;
2005 #endif
2006
2007 /*****************************************************************************************/
2008 /* LKUP_TBL3_LUT_CNXT_CFG                                                                */
2009 /* Look-up table 3: LUT Context Table configurations (base addr + entry context size)    */
2010 /*****************************************************************************************/
2011
2012 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
2013 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
2014 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
2015 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
2016 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
2017 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
2018 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
2019 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
2020 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
2021 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
2022 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
2023
2024
2025 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_OFFSET ( 0x0000005C )
2026
2027 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_OFFSET )
2028 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_ADDRESS ), (r) )
2029 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG_ADDRESS ), (v) )
2030
2031 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2032 typedef struct
2033 {
2034         /* Resreved */
2035         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2036
2037         /* Context_entry_size */
2038         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2039
2040         /* Reserved */
2041         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2042
2043         /* Base_Address */
2044         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2045 }
2046 __PACKING_ATTRIBUTE_STRUCT_END__
2047 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG ;
2048 #else
2049 typedef struct
2050 {
2051         /* Base_Address */
2052         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2053
2054         /* Reserved */
2055         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2056
2057         /* Context_entry_size */
2058         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2059
2060         /* Resreved */
2061         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2062 }
2063 __PACKING_ATTRIBUTE_STRUCT_END__
2064 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG ;
2065 #endif
2066
2067 /*****************************************************************************************/
2068 /* LKUP_TBL4_LUT_CNXT_CFG                                                                */
2069 /* Look-up table 4: LUT Context Table configurations (base addr + entry context size)    */
2070 /*****************************************************************************************/
2071
2072 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
2073 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
2074 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
2075 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
2076 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
2077 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
2078 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
2079 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
2080 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
2081 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
2082 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
2083
2084
2085 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_OFFSET ( 0x00000060 )
2086
2087 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_OFFSET )
2088 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_ADDRESS ), (r) )
2089 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG_ADDRESS ), (v) )
2090
2091 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2092 typedef struct
2093 {
2094         /* Resreved */
2095         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2096
2097         /* Context_entry_size */
2098         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2099
2100         /* Reserved */
2101         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2102
2103         /* Base_Address */
2104         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2105 }
2106 __PACKING_ATTRIBUTE_STRUCT_END__
2107 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG ;
2108 #else
2109 typedef struct
2110 {
2111         /* Base_Address */
2112         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2113
2114         /* Reserved */
2115         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2116
2117         /* Context_entry_size */
2118         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2119
2120         /* Resreved */
2121         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2122 }
2123 __PACKING_ATTRIBUTE_STRUCT_END__
2124 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG ;
2125 #endif
2126
2127 /*****************************************************************************************/
2128 /* LKUP_TBL5_LUT_CNXT_CFG                                                                */
2129 /* Look-up table 5: LUT Context Table configurations (base addr + entry context size)    */
2130 /*****************************************************************************************/
2131
2132 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
2133 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
2134 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
2135 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
2136 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
2137 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
2138 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
2139 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
2140 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
2141 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
2142 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
2143
2144
2145 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_OFFSET ( 0x00000064 )
2146
2147 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_OFFSET )
2148 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_ADDRESS ), (r) )
2149 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG_ADDRESS ), (v) )
2150
2151 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2152 typedef struct
2153 {
2154         /* Resreved */
2155         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2156
2157         /* Context_entry_size */
2158         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2159
2160         /* Reserved */
2161         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2162
2163         /* Base_Address */
2164         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2165 }
2166 __PACKING_ATTRIBUTE_STRUCT_END__
2167 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG ;
2168 #else
2169 typedef struct
2170 {
2171         /* Base_Address */
2172         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2173
2174         /* Reserved */
2175         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2176
2177         /* Context_entry_size */
2178         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2179
2180         /* Resreved */
2181         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2182 }
2183 __PACKING_ATTRIBUTE_STRUCT_END__
2184 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG ;
2185 #endif
2186
2187 /*****************************************************************************************/
2188 /* LKUP_TBL6_LUT_CNXT_CFG                                                                */
2189 /* Look-up table 6: LUT Context Table configurations (base addr + entry context size)    */
2190 /*****************************************************************************************/
2191
2192 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
2193 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
2194 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
2195 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
2196 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
2197 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
2198 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
2199 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED_RESERVED_VALUE                               ( 0x0 )
2200 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_RESREVED_RESERVED_VALUE_RESET_VALUE                   ( 0x0 )
2201 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
2202 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
2203
2204
2205 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_OFFSET ( 0x00000068 )
2206
2207 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_OFFSET )
2208 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_ADDRESS ), (r) )
2209 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG_ADDRESS ), (v) )
2210
2211 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2212 typedef struct
2213 {
2214         /* Resreved */
2215         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2216
2217         /* Context_entry_size */
2218         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2219
2220         /* Resreved */
2221         uint32_t resreved               : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2222
2223         /* Base_Address */
2224         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2225 }
2226 __PACKING_ATTRIBUTE_STRUCT_END__
2227 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG ;
2228 #else
2229 typedef struct
2230 {
2231         /* Base_Address */
2232         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2233
2234         /* Resreved */
2235         uint32_t resreved               : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2236
2237         /* Context_entry_size */
2238         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2239
2240         /* Resreved */
2241         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2242 }
2243 __PACKING_ATTRIBUTE_STRUCT_END__
2244 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG ;
2245 #endif
2246
2247 /*****************************************************************************************/
2248 /* LKUP_TBL7_LUT_CNXT_CFG                                                                */
2249 /* Look-up table 7: LUT Context Table configurations (base addr + entry context size)    */
2250 /*****************************************************************************************/
2251
2252 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
2253 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
2254 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
2255 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
2256 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
2257 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
2258 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
2259 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
2260 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
2261 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
2262 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
2263
2264
2265 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_OFFSET ( 0x0000006C )
2266
2267 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_OFFSET )
2268 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_ADDRESS ), (r) )
2269 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG_ADDRESS ), (v) )
2270
2271 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2272 typedef struct
2273 {
2274         /* Resreved */
2275         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2276
2277         /* Context_entry_size */
2278         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2279
2280         /* Reserved */
2281         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2282
2283         /* Base_Address */
2284         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2285 }
2286 __PACKING_ATTRIBUTE_STRUCT_END__
2287 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG ;
2288 #else
2289 typedef struct
2290 {
2291         /* Base_Address */
2292         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2293
2294         /* Reserved */
2295         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2296
2297         /* Context_entry_size */
2298         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2299
2300         /* Resreved */
2301         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2302 }
2303 __PACKING_ATTRIBUTE_STRUCT_END__
2304 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG ;
2305 #endif
2306
2307 /*****************************************************************************************/
2308 /* LKUP_TBL8_LUT_CNXT_CFG                                                                */
2309 /* Look-up table 8: LUT Context Table configurations (base addr + entry context size)    */
2310 /*****************************************************************************************/
2311
2312 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
2313 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
2314 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
2315 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
2316 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
2317 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
2318 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
2319 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
2320 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
2321 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
2322 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
2323
2324
2325 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_OFFSET ( 0x00000070 )
2326
2327 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_OFFSET )
2328 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_ADDRESS ), (r) )
2329 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG_ADDRESS ), (v) )
2330
2331 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2332 typedef struct
2333 {
2334         /* Resreved */
2335         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2336
2337         /* Context_entry_size */
2338         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2339
2340         /* Reserved */
2341         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2342
2343         /* Base_Address */
2344         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2345 }
2346 __PACKING_ATTRIBUTE_STRUCT_END__
2347 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG ;
2348 #else
2349 typedef struct
2350 {
2351         /* Base_Address */
2352         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2353
2354         /* Reserved */
2355         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2356
2357         /* Context_entry_size */
2358         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2359
2360         /* Resreved */
2361         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2362 }
2363 __PACKING_ATTRIBUTE_STRUCT_END__
2364 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG ;
2365 #endif
2366
2367 /*****************************************************************************************/
2368 /* LKUP_TBL9_LUT_CNXT_CFG                                                                */
2369 /* Look-up table 9: LUT Context Table configurations (base addr + entry context size)    */
2370 /*****************************************************************************************/
2371
2372 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE                              ( 0x0 )
2373 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE                  ( 0x0 )
2374 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE             ( 0x0 )
2375 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_ONE_BYTE_ENTRY_SIZE_VALUE_RESET_VALUE ( 0x0 )
2376 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_TWO_BYTES_ENTRY_SIZE_VALUE            ( 0x1 )
2377 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_FOUR_BYTES_ENTRY_SIZE_VALUE           ( 0x2 )
2378 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_CNXT_ENTRY_SIZE_INTERNAL_ENTRY_VALUE                  ( 0x3 )
2379 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_R1_RESERVED_VALUE                                     ( 0x0 )
2380 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_R1_RESERVED_VALUE_RESET_VALUE                         ( 0x0 )
2381 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE                            ( 0x0 )
2382 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE                ( 0x0 )
2383
2384
2385 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_OFFSET ( 0x00000074 )
2386
2387 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_OFFSET )
2388 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_ADDRESS ), (r) )
2389 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG_ADDRESS ), (v) )
2390
2391 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2392 typedef struct
2393 {
2394         /* Resreved */
2395         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2396
2397         /* Context_entry_size */
2398         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2399
2400         /* Reserved */
2401         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2402
2403         /* Base_Address */
2404         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2405 }
2406 __PACKING_ATTRIBUTE_STRUCT_END__
2407 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG ;
2408 #else
2409 typedef struct
2410 {
2411         /* Base_Address */
2412         uint32_t base_address           : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2413
2414         /* Reserved */
2415         uint32_t r1                     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2416
2417         /* Context_entry_size */
2418         uint32_t cnxt_entry_size        : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2419
2420         /* Resreved */
2421         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2422 }
2423 __PACKING_ATTRIBUTE_STRUCT_END__
2424 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG ;
2425 #endif
2426
2427 /*****************************************************************************************/
2428 /* LKUP_TBL0_CAM_CNXT_CFG                                                                */
2429 /* Look-up table 0: CAM Context Table configurations (base addr + entry context size)    */
2430 /*****************************************************************************************/
2431
2432 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2433 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2434 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2435 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2436
2437
2438 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_OFFSET ( 0x0000007C )
2439
2440 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_OFFSET )
2441 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_ADDRESS ), (r) )
2442 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG_ADDRESS ), (v) )
2443
2444 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2445 typedef struct
2446 {
2447         /* Resreved */
2448         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2449
2450         /* Base_Address */
2451         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2452 }
2453 __PACKING_ATTRIBUTE_STRUCT_END__
2454 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG ;
2455 #else
2456 typedef struct
2457 {
2458         /* Base_Address */
2459         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2460
2461         /* Resreved */
2462         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2463 }
2464 __PACKING_ATTRIBUTE_STRUCT_END__
2465 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG ;
2466 #endif
2467
2468 /*****************************************************************************************/
2469 /* LKUP_TBL1_CAM_CNXT_CFG                                                                */
2470 /* Look-up table 1: CAM Context Table configurations (base addr + entry context size)    */
2471 /*****************************************************************************************/
2472
2473 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2474 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2475 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2476 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2477
2478
2479 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_OFFSET ( 0x00000080 )
2480
2481 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_OFFSET )
2482 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_ADDRESS ), (r) )
2483 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG_ADDRESS ), (v) )
2484
2485 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2486 typedef struct
2487 {
2488         /* Resreved */
2489         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2490
2491         /* Base_Address */
2492         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2493 }
2494 __PACKING_ATTRIBUTE_STRUCT_END__
2495 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG ;
2496 #else
2497 typedef struct
2498 {
2499         /* Base_Address */
2500         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2501
2502         /* Resreved */
2503         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2504 }
2505 __PACKING_ATTRIBUTE_STRUCT_END__
2506 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG ;
2507 #endif
2508
2509 /*****************************************************************************************/
2510 /* LKUP_TBL2_CAM_CNXT_CFG                                                                */
2511 /* Look-up table 2: CAM Context Table configurations (base addr + entry context size)    */
2512 /*****************************************************************************************/
2513
2514 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2515 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2516 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2517 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2518
2519
2520 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_OFFSET ( 0x00000084 )
2521
2522 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_OFFSET )
2523 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_ADDRESS ), (r) )
2524 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG_ADDRESS ), (v) )
2525
2526 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2527 typedef struct
2528 {
2529         /* Resreved */
2530         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2531
2532         /* Base_Address */
2533         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2534 }
2535 __PACKING_ATTRIBUTE_STRUCT_END__
2536 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG ;
2537 #else
2538 typedef struct
2539 {
2540         /* Base_Address */
2541         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2542
2543         /* Resreved */
2544         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2545 }
2546 __PACKING_ATTRIBUTE_STRUCT_END__
2547 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG ;
2548 #endif
2549
2550 /*****************************************************************************************/
2551 /* LKUP_TBL3_CAM_CNXT_CFG                                                                */
2552 /* Look-up table 3: CAM Context Table configurations (base addr + entry context size)    */
2553 /*****************************************************************************************/
2554
2555 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2556 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2557 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2558 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2559
2560
2561 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_OFFSET ( 0x00000088 )
2562
2563 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_OFFSET )
2564 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_ADDRESS ), (r) )
2565 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG_ADDRESS ), (v) )
2566
2567 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2568 typedef struct
2569 {
2570         /* Resreved */
2571         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2572
2573         /* Base_Address */
2574         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2575 }
2576 __PACKING_ATTRIBUTE_STRUCT_END__
2577 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG ;
2578 #else
2579 typedef struct
2580 {
2581         /* Base_Address */
2582         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2583
2584         /* Resreved */
2585         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2586 }
2587 __PACKING_ATTRIBUTE_STRUCT_END__
2588 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG ;
2589 #endif
2590
2591 /*****************************************************************************************/
2592 /* LKUP_TBL4_CAM_CNXT_CFG                                                                */
2593 /* Look-up table 4: CAM Context Table configurations (base addr + entry context size)    */
2594 /*****************************************************************************************/
2595
2596 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2597 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2598 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2599 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2600
2601
2602 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_OFFSET ( 0x0000008C )
2603
2604 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_OFFSET )
2605 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_ADDRESS ), (r) )
2606 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG_ADDRESS ), (v) )
2607
2608 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2609 typedef struct
2610 {
2611         /* Resreved */
2612         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2613
2614         /* Base_Address */
2615         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2616 }
2617 __PACKING_ATTRIBUTE_STRUCT_END__
2618 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG ;
2619 #else
2620 typedef struct
2621 {
2622         /* Base_Address */
2623         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2624
2625         /* Resreved */
2626         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2627 }
2628 __PACKING_ATTRIBUTE_STRUCT_END__
2629 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG ;
2630 #endif
2631
2632 /*****************************************************************************************/
2633 /* LKUP_TBL5_CAM_CNXT_CFG                                                                */
2634 /* Look-up table 5: CAM Context Table configurations (base addr + entry context size)    */
2635 /*****************************************************************************************/
2636
2637 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2638 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2639 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2640 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2641
2642
2643 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_OFFSET ( 0x00000090 )
2644
2645 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_OFFSET )
2646 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_ADDRESS ), (r) )
2647 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG_ADDRESS ), (v) )
2648
2649 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2650 typedef struct
2651 {
2652         /* Resreved */
2653         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2654
2655         /* Base_Address */
2656         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2657 }
2658 __PACKING_ATTRIBUTE_STRUCT_END__
2659 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG ;
2660 #else
2661 typedef struct
2662 {
2663         /* Base_Address */
2664         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2665
2666         /* Resreved */
2667         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2668 }
2669 __PACKING_ATTRIBUTE_STRUCT_END__
2670 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG ;
2671 #endif
2672
2673 /*****************************************************************************************/
2674 /* LKUP_TBL6_CAM_CNXT_CFG                                                                */
2675 /* Look-up table 6: CAM Context Table configurations (base addr + entry context size)    */
2676 /*****************************************************************************************/
2677
2678 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2679 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2680 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2681 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2682
2683
2684 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_OFFSET ( 0x00000094 )
2685
2686 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_OFFSET )
2687 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_ADDRESS ), (r) )
2688 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG_ADDRESS ), (v) )
2689
2690 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2691 typedef struct
2692 {
2693         /* Resreved */
2694         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2695
2696         /* Base_Address */
2697         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2698 }
2699 __PACKING_ATTRIBUTE_STRUCT_END__
2700 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG ;
2701 #else
2702 typedef struct
2703 {
2704         /* Base_Address */
2705         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2706
2707         /* Resreved */
2708         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2709 }
2710 __PACKING_ATTRIBUTE_STRUCT_END__
2711 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG ;
2712 #endif
2713
2714 /*****************************************************************************************/
2715 /* LKUP_TBL7_CAM_CNXT_CFG                                                                */
2716 /* Look-up table 7: CAM Context Table configurations (base addr + entry context size)    */
2717 /*****************************************************************************************/
2718
2719 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2720 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2721 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2722 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2723
2724
2725 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_OFFSET ( 0x00000098 )
2726
2727 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_OFFSET )
2728 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_ADDRESS ), (r) )
2729 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG_ADDRESS ), (v) )
2730
2731 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2732 typedef struct
2733 {
2734         /* Resreved */
2735         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2736
2737         /* Base_Address */
2738         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2739 }
2740 __PACKING_ATTRIBUTE_STRUCT_END__
2741 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG ;
2742 #else
2743 typedef struct
2744 {
2745         /* Base_Address */
2746         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2747
2748         /* Resreved */
2749         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2750 }
2751 __PACKING_ATTRIBUTE_STRUCT_END__
2752 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG ;
2753 #endif
2754
2755 /*****************************************************************************************/
2756 /* LKUP_TBL8_CAM_CNXT_CFG                                                                */
2757 /* Look-up table 8: CAM Context Table configurations (base addr + entry context size)    */
2758 /*****************************************************************************************/
2759
2760 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2761 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2762 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2763 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2764
2765
2766 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_OFFSET ( 0x0000009C )
2767
2768 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_OFFSET )
2769 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_ADDRESS ), (r) )
2770 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG_ADDRESS ), (v) )
2771
2772 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2773 typedef struct
2774 {
2775         /* Resreved */
2776         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2777
2778         /* Base_Address */
2779         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2780 }
2781 __PACKING_ATTRIBUTE_STRUCT_END__
2782 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG ;
2783 #else
2784 typedef struct
2785 {
2786         /* Base_Address */
2787         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2788
2789         /* Resreved */
2790         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2791 }
2792 __PACKING_ATTRIBUTE_STRUCT_END__
2793 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG ;
2794 #endif
2795
2796 /*****************************************************************************************/
2797 /* LKUP_TBL9_CAM_CNXT_CFG                                                                */
2798 /* Look-up table 9: CAM Context Table configurations (base addr + entry context size)    */
2799 /*****************************************************************************************/
2800
2801 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE               ( 0x0 )
2802 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE   ( 0x0 )
2803 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE             ( 0x0 )
2804 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_BASE_ADDRESS_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
2805
2806
2807 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_OFFSET ( 0x00000100 )
2808
2809 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_OFFSET )
2810 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_ADDRESS ), (r) )
2811 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG_ADDRESS ), (v) )
2812
2813 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2814 typedef struct
2815 {
2816         /* Resreved */
2817         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2818
2819         /* Base_Address */
2820         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2821 }
2822 __PACKING_ATTRIBUTE_STRUCT_END__
2823 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG ;
2824 #else
2825 typedef struct
2826 {
2827         /* Base_Address */
2828         uint32_t base_address   : 13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2829
2830         /* Resreved */
2831         uint32_t resreved1      : 19 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2832 }
2833 __PACKING_ATTRIBUTE_STRUCT_END__
2834 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG ;
2835 #endif
2836
2837 /*****************************************************************************************/
2838 /* LKUP_TBL0_KEY_CFG                                                                     */
2839 /* Look-up table 0: Search key configuration parameters.    Key is based on two parts, e */
2840 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
2841 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
2842 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
2843 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
2844 /*  then two parts are ORed.  There is an option to add source port/GEM flow ID/WAN (tak */
2845 /* en from Ingres Header Descriptor) to LSB of the search key.                           */
2846 /*****************************************************************************************/
2847
2848 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
2849 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
2850 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
2851 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
2852 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
2853 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
2854 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
2855 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
2856 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
2857 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
2858 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
2859 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
2860 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
2861 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
2862 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
2863 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
2864 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
2865 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
2866 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
2867 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
2868 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
2869 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
2870 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
2871 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
2872 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
2873 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
2874 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
2875 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
2876 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
2877 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
2878 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
2879 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
2880 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
2881 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
2882 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
2883 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
2884 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
2885 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
2886 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
2887 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
2888 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
2889 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
2890 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
2891 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
2892 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
2893 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
2894 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
2895 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
2896 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
2897 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
2898 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
2899 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
2900 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
2901 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
2902 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
2903 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
2904 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
2905 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
2906 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
2907 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
2908 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
2909 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
2910 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
2911 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
2912 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
2913 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
2914 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
2915 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
2916 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
2917 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
2918 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
2919 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
2920 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
2921 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
2922 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
2923
2924
2925 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_OFFSET ( 0x00000104 )
2926
2927 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_OFFSET )
2928 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_ADDRESS ), (r) )
2929 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG_ADDRESS ), (v) )
2930
2931 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2932 typedef struct
2933 {
2934         /* Resreved */
2935         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2936
2937         /* KEY_EXT */
2938         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2939
2940         /* shift_offset_p1 */
2941         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2942
2943         /* start_offset_p1 */
2944         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2945
2946         /* shift_offset_p0 */
2947         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2948
2949         /* start_offset_p0 */
2950         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2951 }
2952 __PACKING_ATTRIBUTE_STRUCT_END__
2953 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG ;
2954 #else
2955 typedef struct
2956 {
2957         /* start_offset_p0 */
2958         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2959
2960         /* shift_offset_p0 */
2961         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2962
2963         /* start_offset_p1 */
2964         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2965
2966         /* shift_offset_p1 */
2967         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2968
2969         /* KEY_EXT */
2970         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2971
2972         /* Resreved */
2973         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
2974 }
2975 __PACKING_ATTRIBUTE_STRUCT_END__
2976 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG ;
2977 #endif
2978
2979 /*****************************************************************************************/
2980 /* LKUP_TBL0_KEY_P0_MASKL                                                                */
2981 /* Look-up table 0: MAsk on bits [31:0] of Part 0    Key is based on two parts, each par */
2982 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
2983 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
2984 /*****************************************************************************************/
2985
2986 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
2987 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
2988
2989
2990 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_OFFSET ( 0x00000108 )
2991
2992 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_OFFSET )
2993 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_ADDRESS ), (r) )
2994 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL_ADDRESS ), (v) )
2995
2996 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
2997 typedef struct
2998 {
2999         /* MASKL */
3000         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3001 }
3002 __PACKING_ATTRIBUTE_STRUCT_END__
3003 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL ;
3004 #else
3005 typedef struct
3006 {
3007         /* MASKL */
3008         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3009 }
3010 __PACKING_ATTRIBUTE_STRUCT_END__
3011 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL ;
3012 #endif
3013
3014 /*****************************************************************************************/
3015 /* LKUP_TBL0_KEY_P0_MASKH                                                                */
3016 /* Look-up table 0: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
3017 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3018 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3019 /*****************************************************************************************/
3020
3021 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
3022 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
3023 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
3024 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
3025
3026
3027 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_OFFSET ( 0x0000010C )
3028
3029 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_OFFSET )
3030 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_ADDRESS ), (r) )
3031 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH_ADDRESS ), (v) )
3032
3033 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3034 typedef struct
3035 {
3036         /* reserved */
3037         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3038
3039         /* MASKH */
3040         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3041 }
3042 __PACKING_ATTRIBUTE_STRUCT_END__
3043 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH ;
3044 #else
3045 typedef struct
3046 {
3047         /* MASKH */
3048         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3049
3050         /* reserved */
3051         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3052 }
3053 __PACKING_ATTRIBUTE_STRUCT_END__
3054 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH ;
3055 #endif
3056
3057 /*****************************************************************************************/
3058 /* LKUP_TBL0_KEY_P1_MASKL                                                                */
3059 /* Look-up table 0: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
3060 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
3061 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
3062 /*****************************************************************************************/
3063
3064 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
3065 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
3066
3067
3068 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_OFFSET ( 0x00000110 )
3069
3070 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_OFFSET )
3071 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_ADDRESS ), (r) )
3072 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL_ADDRESS ), (v) )
3073
3074 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3075 typedef struct
3076 {
3077         /* MASKL */
3078         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3079 }
3080 __PACKING_ATTRIBUTE_STRUCT_END__
3081 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL ;
3082 #else
3083 typedef struct
3084 {
3085         /* MASKL */
3086         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3087 }
3088 __PACKING_ATTRIBUTE_STRUCT_END__
3089 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL ;
3090 #endif
3091
3092 /*****************************************************************************************/
3093 /* LKUP_TBL0_KEY_P1_MASKH                                                                */
3094 /* Look-up table 0: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
3095 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3096 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3097 /*****************************************************************************************/
3098
3099 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
3100 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
3101 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
3102 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
3103
3104
3105 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_OFFSET ( 0x00000114 )
3106
3107 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_OFFSET )
3108 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_ADDRESS ), (r) )
3109 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH_ADDRESS ), (v) )
3110
3111 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3112 typedef struct
3113 {
3114         /* reserved */
3115         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3116
3117         /* MASKH */
3118         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3119 }
3120 __PACKING_ATTRIBUTE_STRUCT_END__
3121 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH ;
3122 #else
3123 typedef struct
3124 {
3125         /* MASKH */
3126         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3127
3128         /* reserved */
3129         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3130 }
3131 __PACKING_ATTRIBUTE_STRUCT_END__
3132 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH ;
3133 #endif
3134
3135 /*****************************************************************************************/
3136 /* LKUP_TBL1_KEY_CFG                                                                     */
3137 /* Look-up table 1: Search key configuration parameters.    Key is based on two parts, e */
3138 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
3139 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
3140 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
3141 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
3142 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
3143 /* eader Descriptor) to 5 MSB of the search key.                                         */
3144 /*****************************************************************************************/
3145
3146 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
3147 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
3148 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
3149 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
3150 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
3151 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
3152 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
3153 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
3154 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
3155 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
3156 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
3157 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
3158 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
3159 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
3160 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
3161 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
3162 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
3163 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
3164 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
3165 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
3166 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
3167 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
3168 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
3169 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
3170 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
3171 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
3172 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
3173 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
3174 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
3175 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
3176 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
3177 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
3178 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
3179 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
3180 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
3181 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
3182 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
3183 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
3184 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
3185 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
3186 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
3187 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
3188 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
3189 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
3190 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
3191 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
3192 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
3193 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
3194 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
3195 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
3196 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
3197 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
3198 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
3199 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
3200 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
3201 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
3202 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
3203 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
3204 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
3205 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
3206 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
3207 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
3208 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
3209 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
3210 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
3211 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
3212 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
3213 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
3214 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
3215 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
3216 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
3217 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
3218 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
3219 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
3220 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
3221
3222
3223 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_OFFSET ( 0x00000118 )
3224
3225 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_OFFSET )
3226 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_ADDRESS ), (r) )
3227 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG_ADDRESS ), (v) )
3228
3229 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3230 typedef struct
3231 {
3232         /* Resreved */
3233         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3234
3235         /* KEY_EXT */
3236         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3237
3238         /* shift_offset_p1 */
3239         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3240
3241         /* start_offset_p1 */
3242         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3243
3244         /* shift_offset_p0 */
3245         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3246
3247         /* start_offset_p0 */
3248         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3249 }
3250 __PACKING_ATTRIBUTE_STRUCT_END__
3251 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG ;
3252 #else
3253 typedef struct
3254 {
3255         /* start_offset_p0 */
3256         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3257
3258         /* shift_offset_p0 */
3259         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3260
3261         /* start_offset_p1 */
3262         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3263
3264         /* shift_offset_p1 */
3265         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3266
3267         /* KEY_EXT */
3268         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3269
3270         /* Resreved */
3271         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3272 }
3273 __PACKING_ATTRIBUTE_STRUCT_END__
3274 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG ;
3275 #endif
3276
3277 /*****************************************************************************************/
3278 /* LKUP_TBL1_KEY_P0_MASKL                                                                */
3279 /* Look-up table 0: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
3280 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
3281 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
3282 /*****************************************************************************************/
3283
3284 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
3285 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
3286
3287
3288 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_OFFSET ( 0x0000011C )
3289
3290 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_OFFSET )
3291 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_ADDRESS ), (r) )
3292 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL_ADDRESS ), (v) )
3293
3294 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3295 typedef struct
3296 {
3297         /* MASKL */
3298         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3299 }
3300 __PACKING_ATTRIBUTE_STRUCT_END__
3301 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL ;
3302 #else
3303 typedef struct
3304 {
3305         /* MASKL */
3306         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3307 }
3308 __PACKING_ATTRIBUTE_STRUCT_END__
3309 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL ;
3310 #endif
3311
3312 /*****************************************************************************************/
3313 /* LKUP_TBL1_KEY_P0_MASKH                                                                */
3314 /* Look-up table 0: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
3315 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3316 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3317 /*****************************************************************************************/
3318
3319 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
3320 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
3321 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
3322 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
3323
3324
3325 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_OFFSET ( 0x00000120 )
3326
3327 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_OFFSET )
3328 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_ADDRESS ), (r) )
3329 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH_ADDRESS ), (v) )
3330
3331 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3332 typedef struct
3333 {
3334         /* reserved */
3335         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3336
3337         /* MASKH */
3338         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3339 }
3340 __PACKING_ATTRIBUTE_STRUCT_END__
3341 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH ;
3342 #else
3343 typedef struct
3344 {
3345         /* MASKH */
3346         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3347
3348         /* reserved */
3349         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3350 }
3351 __PACKING_ATTRIBUTE_STRUCT_END__
3352 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH ;
3353 #endif
3354
3355 /*****************************************************************************************/
3356 /* LKUP_TBL1_KEY_P1_MASKL                                                                */
3357 /* Look-up table 1: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
3358 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
3359 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
3360 /*****************************************************************************************/
3361
3362 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
3363 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
3364
3365
3366 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_OFFSET ( 0x00000124 )
3367
3368 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_OFFSET )
3369 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_ADDRESS ), (r) )
3370 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL_ADDRESS ), (v) )
3371
3372 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3373 typedef struct
3374 {
3375         /* MASKL */
3376         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3377 }
3378 __PACKING_ATTRIBUTE_STRUCT_END__
3379 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL ;
3380 #else
3381 typedef struct
3382 {
3383         /* MASKL */
3384         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3385 }
3386 __PACKING_ATTRIBUTE_STRUCT_END__
3387 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL ;
3388 #endif
3389
3390 /*****************************************************************************************/
3391 /* LKUP_TBL1_KEY_P1_MASKH                                                                */
3392 /* Look-up table 1: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
3393 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3394 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3395 /*****************************************************************************************/
3396
3397 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
3398 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
3399 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
3400 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
3401
3402
3403 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_OFFSET ( 0x00000128 )
3404
3405 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_OFFSET )
3406 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_ADDRESS ), (r) )
3407 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH_ADDRESS ), (v) )
3408
3409 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3410 typedef struct
3411 {
3412         /* reserved */
3413         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3414
3415         /* MASKH */
3416         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3417 }
3418 __PACKING_ATTRIBUTE_STRUCT_END__
3419 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH ;
3420 #else
3421 typedef struct
3422 {
3423         /* MASKH */
3424         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3425
3426         /* reserved */
3427         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3428 }
3429 __PACKING_ATTRIBUTE_STRUCT_END__
3430 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH ;
3431 #endif
3432
3433 /*****************************************************************************************/
3434 /* LKUP_TBL2_KEY_CFG                                                                     */
3435 /* Look-up table 2: Search key configuration parameters.    Key is based on two parts, e */
3436 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
3437 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
3438 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
3439 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
3440 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
3441 /* eader Descriptor) to 5 MSB of the search key.                                         */
3442 /*****************************************************************************************/
3443
3444 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
3445 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
3446 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
3447 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
3448 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
3449 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
3450 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
3451 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
3452 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
3453 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
3454 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
3455 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
3456 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
3457 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
3458 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
3459 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
3460 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
3461 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
3462 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
3463 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
3464 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
3465 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
3466 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
3467 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
3468 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
3469 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
3470 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
3471 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
3472 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
3473 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
3474 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
3475 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
3476 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
3477 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
3478 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
3479 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
3480 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
3481 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
3482 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
3483 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
3484 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
3485 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
3486 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
3487 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
3488 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
3489 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
3490 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
3491 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
3492 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
3493 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
3494 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
3495 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
3496 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
3497 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
3498 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
3499 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
3500 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
3501 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
3502 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
3503 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
3504 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
3505 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
3506 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
3507 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
3508 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
3509 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
3510 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
3511 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
3512 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
3513 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
3514 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
3515 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
3516 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
3517 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
3518 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
3519
3520
3521 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_OFFSET ( 0x0000012C )
3522
3523 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_OFFSET )
3524 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_ADDRESS ), (r) )
3525 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG_ADDRESS ), (v) )
3526
3527 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3528 typedef struct
3529 {
3530         /* Resreved */
3531         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3532
3533         /* KEY_EXT */
3534         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3535
3536         /* shift_offset_p1 */
3537         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3538
3539         /* start_offset_p1 */
3540         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3541
3542         /* shift_offset_p0 */
3543         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3544
3545         /* start_offset_p0 */
3546         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3547 }
3548 __PACKING_ATTRIBUTE_STRUCT_END__
3549 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG ;
3550 #else
3551 typedef struct
3552 {
3553         /* start_offset_p0 */
3554         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3555
3556         /* shift_offset_p0 */
3557         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3558
3559         /* start_offset_p1 */
3560         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3561
3562         /* shift_offset_p1 */
3563         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3564
3565         /* KEY_EXT */
3566         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3567
3568         /* Resreved */
3569         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3570 }
3571 __PACKING_ATTRIBUTE_STRUCT_END__
3572 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG ;
3573 #endif
3574
3575 /*****************************************************************************************/
3576 /* LKUP_TBL2_KEY_P0_MASKL                                                                */
3577 /* Look-up table 0: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
3578 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
3579 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
3580 /*****************************************************************************************/
3581
3582 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
3583 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
3584
3585
3586 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_OFFSET ( 0x00000130 )
3587
3588 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_OFFSET )
3589 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_ADDRESS ), (r) )
3590 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL_ADDRESS ), (v) )
3591
3592 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3593 typedef struct
3594 {
3595         /* MASKL */
3596         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3597 }
3598 __PACKING_ATTRIBUTE_STRUCT_END__
3599 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL ;
3600 #else
3601 typedef struct
3602 {
3603         /* MASKL */
3604         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3605 }
3606 __PACKING_ATTRIBUTE_STRUCT_END__
3607 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL ;
3608 #endif
3609
3610 /*****************************************************************************************/
3611 /* LKUP_TBL2_KEY_P0_MASKH                                                                */
3612 /* Look-up table 2: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
3613 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3614 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3615 /*****************************************************************************************/
3616
3617 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
3618 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
3619 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
3620 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
3621
3622
3623 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_OFFSET ( 0x00000134 )
3624
3625 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_OFFSET )
3626 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_ADDRESS ), (r) )
3627 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH_ADDRESS ), (v) )
3628
3629 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3630 typedef struct
3631 {
3632         /* reserved */
3633         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3634
3635         /* MASKH */
3636         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3637 }
3638 __PACKING_ATTRIBUTE_STRUCT_END__
3639 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH ;
3640 #else
3641 typedef struct
3642 {
3643         /* MASKH */
3644         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3645
3646         /* reserved */
3647         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3648 }
3649 __PACKING_ATTRIBUTE_STRUCT_END__
3650 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH ;
3651 #endif
3652
3653 /*****************************************************************************************/
3654 /* LKUP_TBL2_KEY_P1_MASKL                                                                */
3655 /* Look-up table 1: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
3656 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
3657 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
3658 /*****************************************************************************************/
3659
3660 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
3661 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
3662
3663
3664 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_OFFSET ( 0x00000138 )
3665
3666 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_OFFSET )
3667 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_ADDRESS ), (r) )
3668 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL_ADDRESS ), (v) )
3669
3670 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3671 typedef struct
3672 {
3673         /* MASKL */
3674         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3675 }
3676 __PACKING_ATTRIBUTE_STRUCT_END__
3677 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL ;
3678 #else
3679 typedef struct
3680 {
3681         /* MASKL */
3682         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3683 }
3684 __PACKING_ATTRIBUTE_STRUCT_END__
3685 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL ;
3686 #endif
3687
3688 /*****************************************************************************************/
3689 /* LKUP_TBL2_KEY_P1_MASKH                                                                */
3690 /* Look-up table 3: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
3691 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3692 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3693 /*****************************************************************************************/
3694
3695 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
3696 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
3697 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
3698 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
3699
3700
3701 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_OFFSET ( 0x0000013C )
3702
3703 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_OFFSET )
3704 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_ADDRESS ), (r) )
3705 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH_ADDRESS ), (v) )
3706
3707 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3708 typedef struct
3709 {
3710         /* reserved */
3711         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3712
3713         /* MASKH */
3714         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3715 }
3716 __PACKING_ATTRIBUTE_STRUCT_END__
3717 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH ;
3718 #else
3719 typedef struct
3720 {
3721         /* MASKH */
3722         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3723
3724         /* reserved */
3725         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3726 }
3727 __PACKING_ATTRIBUTE_STRUCT_END__
3728 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH ;
3729 #endif
3730
3731 /*****************************************************************************************/
3732 /* LKUP_TBL3_KEY_CFG                                                                     */
3733 /* Look-up table 2: Search key configuration parameters.    Key is based on two parts, e */
3734 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
3735 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
3736 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
3737 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
3738 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
3739 /* eader Descriptor) to 5 MSB of the search key.                                         */
3740 /*****************************************************************************************/
3741
3742 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
3743 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
3744 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
3745 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
3746 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
3747 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
3748 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
3749 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
3750 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
3751 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
3752 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
3753 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
3754 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
3755 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
3756 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
3757 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
3758 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
3759 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
3760 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
3761 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
3762 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
3763 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
3764 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
3765 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
3766 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
3767 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
3768 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
3769 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
3770 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
3771 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
3772 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
3773 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
3774 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
3775 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
3776 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
3777 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
3778 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
3779 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
3780 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
3781 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
3782 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
3783 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
3784 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
3785 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
3786 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
3787 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
3788 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
3789 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
3790 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
3791 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
3792 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
3793 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
3794 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
3795 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
3796 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
3797 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
3798 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
3799 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
3800 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
3801 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
3802 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
3803 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
3804 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
3805 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
3806 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
3807 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
3808 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
3809 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
3810 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
3811 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
3812 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
3813 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
3814 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
3815 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
3816 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
3817
3818
3819 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_OFFSET ( 0x00000140 )
3820
3821 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_OFFSET )
3822 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_ADDRESS ), (r) )
3823 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG_ADDRESS ), (v) )
3824
3825 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3826 typedef struct
3827 {
3828         /* Resreved */
3829         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3830
3831         /* KEY_EXT */
3832         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3833
3834         /* shift_offset_p1 */
3835         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3836
3837         /* start_offset_p1 */
3838         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3839
3840         /* shift_offset_p0 */
3841         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3842
3843         /* start_offset_p0 */
3844         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3845 }
3846 __PACKING_ATTRIBUTE_STRUCT_END__
3847 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG ;
3848 #else
3849 typedef struct
3850 {
3851         /* start_offset_p0 */
3852         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3853
3854         /* shift_offset_p0 */
3855         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3856
3857         /* start_offset_p1 */
3858         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3859
3860         /* shift_offset_p1 */
3861         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3862
3863         /* KEY_EXT */
3864         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3865
3866         /* Resreved */
3867         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3868 }
3869 __PACKING_ATTRIBUTE_STRUCT_END__
3870 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG ;
3871 #endif
3872
3873 /*****************************************************************************************/
3874 /* LKUP_TBL3_KEY_P0_MASKL                                                                */
3875 /* Look-up table 3: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
3876 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
3877 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
3878 /*****************************************************************************************/
3879
3880 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
3881 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
3882
3883
3884 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_OFFSET ( 0x00000144 )
3885
3886 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_OFFSET )
3887 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_ADDRESS ), (r) )
3888 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL_ADDRESS ), (v) )
3889
3890 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3891 typedef struct
3892 {
3893         /* MASKL */
3894         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3895 }
3896 __PACKING_ATTRIBUTE_STRUCT_END__
3897 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL ;
3898 #else
3899 typedef struct
3900 {
3901         /* MASKL */
3902         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3903 }
3904 __PACKING_ATTRIBUTE_STRUCT_END__
3905 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL ;
3906 #endif
3907
3908 /*****************************************************************************************/
3909 /* LKUP_TBL3_KEY_P0_MASKH                                                                */
3910 /* Look-up table 2: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
3911 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3912 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3913 /*****************************************************************************************/
3914
3915 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_RESERVED_RSV_VALUE             ( 0x0 )
3916 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_RESERVED_RSV_VALUE_RESET_VALUE ( 0x0 )
3917 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_MASKH_MASKH_VALUE              ( 0x0 )
3918 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE  ( 0x0 )
3919
3920
3921 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_OFFSET ( 0x00000148 )
3922
3923 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_OFFSET )
3924 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_ADDRESS ), (r) )
3925 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH_ADDRESS ), (v) )
3926
3927 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3928 typedef struct
3929 {
3930         /* reserved */
3931         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3932
3933         /* MASKH */
3934         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3935 }
3936 __PACKING_ATTRIBUTE_STRUCT_END__
3937 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH ;
3938 #else
3939 typedef struct
3940 {
3941         /* MASKH */
3942         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3943
3944         /* reserved */
3945         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3946 }
3947 __PACKING_ATTRIBUTE_STRUCT_END__
3948 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH ;
3949 #endif
3950
3951 /*****************************************************************************************/
3952 /* LKUP_TBL3_KEY_P1_MASKL                                                                */
3953 /* Look-up table 1: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
3954 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
3955 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
3956 /*****************************************************************************************/
3957
3958 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
3959 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
3960
3961
3962 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_OFFSET ( 0x0000014C )
3963
3964 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_OFFSET )
3965 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_ADDRESS ), (r) )
3966 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL_ADDRESS ), (v) )
3967
3968 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
3969 typedef struct
3970 {
3971         /* MASKL */
3972         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3973 }
3974 __PACKING_ATTRIBUTE_STRUCT_END__
3975 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL ;
3976 #else
3977 typedef struct
3978 {
3979         /* MASKL */
3980         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
3981 }
3982 __PACKING_ATTRIBUTE_STRUCT_END__
3983 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL ;
3984 #endif
3985
3986 /*****************************************************************************************/
3987 /* LKUP_TBL3_KEY_P1_MASKH                                                                */
3988 /* Look-up table 3: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
3989 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
3990 /* its own mask that represnted by two registers: MASKL and MASKH                        */
3991 /*****************************************************************************************/
3992
3993 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
3994 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
3995 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
3996 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
3997
3998
3999 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_OFFSET ( 0x00000150 )
4000
4001 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_OFFSET )
4002 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_ADDRESS ), (r) )
4003 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH_ADDRESS ), (v) )
4004
4005 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4006 typedef struct
4007 {
4008         /* reserved */
4009         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4010
4011         /* MASKH */
4012         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4013 }
4014 __PACKING_ATTRIBUTE_STRUCT_END__
4015 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH ;
4016 #else
4017 typedef struct
4018 {
4019         /* MASKH */
4020         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4021
4022         /* reserved */
4023         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4024 }
4025 __PACKING_ATTRIBUTE_STRUCT_END__
4026 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH ;
4027 #endif
4028
4029 /*****************************************************************************************/
4030 /* LKUP_TBL4_KEY_CFG                                                                     */
4031 /* Look-up table 4: Search key configuration parameters.    Key is based on two parts, e */
4032 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
4033 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
4034 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
4035 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
4036 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
4037 /* eader Descriptor) to 5 MSB of the search key.                                         */
4038 /*****************************************************************************************/
4039
4040 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
4041 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
4042 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
4043 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
4044 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
4045 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
4046 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
4047 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
4048 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4049 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
4050 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
4051 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
4052 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
4053 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
4054 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
4055 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
4056 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
4057 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
4058 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
4059 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
4060 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
4061 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
4062 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
4063 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
4064 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
4065 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
4066 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
4067 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
4068 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
4069 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
4070 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
4071 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
4072 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
4073 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
4074 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
4075 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
4076 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
4077 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
4078 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
4079 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
4080 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
4081 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
4082 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4083 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
4084 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
4085 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
4086 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
4087 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
4088 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
4089 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
4090 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
4091 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
4092 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
4093 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
4094 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
4095 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
4096 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
4097 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
4098 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
4099 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
4100 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
4101 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
4102 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
4103 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
4104 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
4105 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
4106 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
4107 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
4108 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
4109 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
4110 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
4111 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
4112 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
4113 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
4114 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
4115
4116
4117 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_OFFSET ( 0x00000154 )
4118
4119 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_OFFSET )
4120 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_ADDRESS ), (r) )
4121 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG_ADDRESS ), (v) )
4122
4123 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4124 typedef struct
4125 {
4126         /* Resreved */
4127         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4128
4129         /* KEY_EXT */
4130         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4131
4132         /* shift_offset_p1 */
4133         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4134
4135         /* start_offset_p1 */
4136         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4137
4138         /* shift_offset_p0 */
4139         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4140
4141         /* start_offset_p0 */
4142         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4143 }
4144 __PACKING_ATTRIBUTE_STRUCT_END__
4145 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG ;
4146 #else
4147 typedef struct
4148 {
4149         /* start_offset_p0 */
4150         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4151
4152         /* shift_offset_p0 */
4153         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4154
4155         /* start_offset_p1 */
4156         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4157
4158         /* shift_offset_p1 */
4159         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4160
4161         /* KEY_EXT */
4162         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4163
4164         /* Resreved */
4165         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4166 }
4167 __PACKING_ATTRIBUTE_STRUCT_END__
4168 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG ;
4169 #endif
4170
4171 /*****************************************************************************************/
4172 /* LKUP_TBL4_KEY_P0_MASKL                                                                */
4173 /* Look-up table 4: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
4174 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
4175 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
4176 /*****************************************************************************************/
4177
4178 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
4179 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
4180
4181
4182 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_OFFSET ( 0x00000158 )
4183
4184 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_OFFSET )
4185 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_ADDRESS ), (r) )
4186 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL_ADDRESS ), (v) )
4187
4188 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4189 typedef struct
4190 {
4191         /* MASKL */
4192         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4193 }
4194 __PACKING_ATTRIBUTE_STRUCT_END__
4195 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL ;
4196 #else
4197 typedef struct
4198 {
4199         /* MASKL */
4200         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4201 }
4202 __PACKING_ATTRIBUTE_STRUCT_END__
4203 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL ;
4204 #endif
4205
4206 /*****************************************************************************************/
4207 /* LKUP_TBL4_KEY_P0_MASKH                                                                */
4208 /* Look-up table 4: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
4209 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
4210 /* its own mask that represnted by two registers: MASKL and MASKH                        */
4211 /*****************************************************************************************/
4212
4213 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
4214 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
4215 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
4216 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
4217
4218
4219 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_OFFSET ( 0x0000015C )
4220
4221 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_OFFSET )
4222 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_ADDRESS ), (r) )
4223 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH_ADDRESS ), (v) )
4224
4225 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4226 typedef struct
4227 {
4228         /* reserved */
4229         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4230
4231         /* MASKH */
4232         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4233 }
4234 __PACKING_ATTRIBUTE_STRUCT_END__
4235 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH ;
4236 #else
4237 typedef struct
4238 {
4239         /* MASKH */
4240         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4241
4242         /* reserved */
4243         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4244 }
4245 __PACKING_ATTRIBUTE_STRUCT_END__
4246 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH ;
4247 #endif
4248
4249 /*****************************************************************************************/
4250 /* LKUP_TBL4_KEY_P1_MASKL                                                                */
4251 /* Look-up table 4: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
4252 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
4253 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
4254 /*****************************************************************************************/
4255
4256 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
4257 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
4258
4259
4260 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_OFFSET ( 0x00000160 )
4261
4262 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_OFFSET )
4263 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_ADDRESS ), (r) )
4264 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL_ADDRESS ), (v) )
4265
4266 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4267 typedef struct
4268 {
4269         /* MASKL */
4270         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4271 }
4272 __PACKING_ATTRIBUTE_STRUCT_END__
4273 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL ;
4274 #else
4275 typedef struct
4276 {
4277         /* MASKL */
4278         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4279 }
4280 __PACKING_ATTRIBUTE_STRUCT_END__
4281 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL ;
4282 #endif
4283
4284 /*****************************************************************************************/
4285 /* LKUP_TBL4_KEY_P1_MASKH                                                                */
4286 /* Look-up table 4: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
4287 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
4288 /* its own mask that represnted by two registers: MASKL and MASKH                        */
4289 /*****************************************************************************************/
4290
4291 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
4292 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
4293 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
4294 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
4295
4296
4297 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_OFFSET ( 0x00000164 )
4298
4299 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_OFFSET )
4300 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_ADDRESS ), (r) )
4301 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH_ADDRESS ), (v) )
4302
4303 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4304 typedef struct
4305 {
4306         /* reserved */
4307         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4308
4309         /* MASKH */
4310         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4311 }
4312 __PACKING_ATTRIBUTE_STRUCT_END__
4313 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH ;
4314 #else
4315 typedef struct
4316 {
4317         /* MASKH */
4318         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4319
4320         /* reserved */
4321         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4322 }
4323 __PACKING_ATTRIBUTE_STRUCT_END__
4324 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH ;
4325 #endif
4326
4327 /*****************************************************************************************/
4328 /* LKUP_TBL5_KEY_CFG                                                                     */
4329 /* Look-up table 5: Search key configuration parameters.    Key is based on two parts, e */
4330 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
4331 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
4332 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
4333 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
4334 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
4335 /* eader Descriptor) to 5 MSB of the search key.                                         */
4336 /*****************************************************************************************/
4337
4338 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
4339 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
4340 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
4341 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
4342 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
4343 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
4344 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
4345 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
4346 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4347 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
4348 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
4349 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
4350 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
4351 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
4352 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
4353 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
4354 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
4355 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
4356 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
4357 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
4358 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
4359 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
4360 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
4361 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
4362 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
4363 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
4364 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
4365 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
4366 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
4367 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
4368 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
4369 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
4370 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
4371 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
4372 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
4373 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
4374 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
4375 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
4376 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
4377 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
4378 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
4379 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
4380 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4381 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
4382 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
4383 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
4384 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
4385 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
4386 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
4387 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
4388 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
4389 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
4390 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
4391 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
4392 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
4393 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
4394 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
4395 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
4396 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
4397 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
4398 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
4399 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
4400 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
4401 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
4402 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
4403 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
4404 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
4405 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
4406 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
4407 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
4408 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
4409 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
4410 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
4411 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
4412 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
4413
4414
4415 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_OFFSET ( 0x00000168 )
4416
4417 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_OFFSET )
4418 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_ADDRESS ), (r) )
4419 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG_ADDRESS ), (v) )
4420
4421 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4422 typedef struct
4423 {
4424         /* Resreved */
4425         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4426
4427         /* KEY_EXT */
4428         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4429
4430         /* shift_offset_p1 */
4431         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4432
4433         /* start_offset_p1 */
4434         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4435
4436         /* shift_offset_p0 */
4437         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4438
4439         /* start_offset_p0 */
4440         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4441 }
4442 __PACKING_ATTRIBUTE_STRUCT_END__
4443 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG ;
4444 #else
4445 typedef struct
4446 {
4447         /* start_offset_p0 */
4448         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4449
4450         /* shift_offset_p0 */
4451         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4452
4453         /* start_offset_p1 */
4454         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4455
4456         /* shift_offset_p1 */
4457         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4458
4459         /* KEY_EXT */
4460         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4461
4462         /* Resreved */
4463         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4464 }
4465 __PACKING_ATTRIBUTE_STRUCT_END__
4466 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG ;
4467 #endif
4468
4469 /*****************************************************************************************/
4470 /* LKUP_TBL5_KEY_P0_MASKL                                                                */
4471 /* Look-up table 4: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
4472 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
4473 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
4474 /*****************************************************************************************/
4475
4476 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
4477 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
4478
4479
4480 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_OFFSET ( 0x0000016C )
4481
4482 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_OFFSET )
4483 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_ADDRESS ), (r) )
4484 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL_ADDRESS ), (v) )
4485
4486 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4487 typedef struct
4488 {
4489         /* MASKL */
4490         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4491 }
4492 __PACKING_ATTRIBUTE_STRUCT_END__
4493 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL ;
4494 #else
4495 typedef struct
4496 {
4497         /* MASKL */
4498         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4499 }
4500 __PACKING_ATTRIBUTE_STRUCT_END__
4501 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL ;
4502 #endif
4503
4504 /*****************************************************************************************/
4505 /* LKUP_TBL5_KEY_P0_MASKH                                                                */
4506 /* Look-up table 5: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
4507 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
4508 /* its own mask that represnted by two registers: MASKL and MASKH                        */
4509 /*****************************************************************************************/
4510
4511 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
4512 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
4513 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
4514 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
4515
4516
4517 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_OFFSET ( 0x00000170 )
4518
4519 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_OFFSET )
4520 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_ADDRESS ), (r) )
4521 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH_ADDRESS ), (v) )
4522
4523 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4524 typedef struct
4525 {
4526         /* reserved */
4527         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4528
4529         /* MASKH */
4530         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4531 }
4532 __PACKING_ATTRIBUTE_STRUCT_END__
4533 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH ;
4534 #else
4535 typedef struct
4536 {
4537         /* MASKH */
4538         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4539
4540         /* reserved */
4541         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4542 }
4543 __PACKING_ATTRIBUTE_STRUCT_END__
4544 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH ;
4545 #endif
4546
4547 /*****************************************************************************************/
4548 /* LKUP_TBL5_KEY_P1_MASKL                                                                */
4549 /* Look-up table 5: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
4550 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
4551 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
4552 /*****************************************************************************************/
4553
4554 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
4555 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
4556
4557
4558 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_OFFSET ( 0x00000174 )
4559
4560 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_OFFSET )
4561 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_ADDRESS ), (r) )
4562 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL_ADDRESS ), (v) )
4563
4564 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4565 typedef struct
4566 {
4567         /* MASKL */
4568         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4569 }
4570 __PACKING_ATTRIBUTE_STRUCT_END__
4571 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL ;
4572 #else
4573 typedef struct
4574 {
4575         /* MASKL */
4576         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4577 }
4578 __PACKING_ATTRIBUTE_STRUCT_END__
4579 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL ;
4580 #endif
4581
4582 /*****************************************************************************************/
4583 /* LKUP_TBL5_KEY_P1_MASKH                                                                */
4584 /* Look-up table 5: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
4585 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
4586 /* its own mask that represnted by two registers: MASKL and MASKH                        */
4587 /*****************************************************************************************/
4588
4589 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
4590 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
4591 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
4592 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
4593
4594
4595 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_OFFSET ( 0x00000178 )
4596
4597 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_OFFSET )
4598 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_ADDRESS ), (r) )
4599 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH_ADDRESS ), (v) )
4600
4601 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4602 typedef struct
4603 {
4604         /* reserved */
4605         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4606
4607         /* MASKH */
4608         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4609 }
4610 __PACKING_ATTRIBUTE_STRUCT_END__
4611 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH ;
4612 #else
4613 typedef struct
4614 {
4615         /* MASKH */
4616         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4617
4618         /* reserved */
4619         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4620 }
4621 __PACKING_ATTRIBUTE_STRUCT_END__
4622 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH ;
4623 #endif
4624
4625 /*****************************************************************************************/
4626 /* LKUP_TBL6_KEY_CFG                                                                     */
4627 /* Look-up table 6: Search key configuration parameters.    Key is based on two parts, e */
4628 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
4629 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
4630 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
4631 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
4632 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
4633 /* eader Descriptor) to 5 MSB of the search key.                                         */
4634 /*****************************************************************************************/
4635
4636 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
4637 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
4638 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
4639 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
4640 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
4641 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
4642 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
4643 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
4644 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4645 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
4646 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
4647 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
4648 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
4649 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
4650 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
4651 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
4652 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
4653 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
4654 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
4655 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
4656 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
4657 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
4658 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
4659 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
4660 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
4661 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
4662 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
4663 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
4664 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
4665 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
4666 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
4667 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
4668 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
4669 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
4670 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
4671 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
4672 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
4673 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
4674 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
4675 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
4676 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
4677 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
4678 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4679 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
4680 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
4681 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
4682 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
4683 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
4684 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
4685 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
4686 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
4687 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
4688 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
4689 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
4690 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
4691 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
4692 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
4693 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
4694 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
4695 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
4696 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
4697 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
4698 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
4699 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
4700 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
4701 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
4702 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
4703 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
4704 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
4705 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
4706 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
4707 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
4708 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
4709 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
4710 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
4711
4712
4713 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_OFFSET ( 0x0000017C )
4714
4715 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_OFFSET )
4716 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_ADDRESS ), (r) )
4717 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG_ADDRESS ), (v) )
4718
4719 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4720 typedef struct
4721 {
4722         /* Resreved */
4723         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4724
4725         /* KEY_EXT */
4726         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4727
4728         /* shift_offset_p1 */
4729         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4730
4731         /* start_offset_p1 */
4732         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4733
4734         /* shift_offset_p0 */
4735         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4736
4737         /* start_offset_p0 */
4738         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4739 }
4740 __PACKING_ATTRIBUTE_STRUCT_END__
4741 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG ;
4742 #else
4743 typedef struct
4744 {
4745         /* start_offset_p0 */
4746         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4747
4748         /* shift_offset_p0 */
4749         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4750
4751         /* start_offset_p1 */
4752         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4753
4754         /* shift_offset_p1 */
4755         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4756
4757         /* KEY_EXT */
4758         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4759
4760         /* Resreved */
4761         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4762 }
4763 __PACKING_ATTRIBUTE_STRUCT_END__
4764 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG ;
4765 #endif
4766
4767 /*****************************************************************************************/
4768 /* LKUP_TBL6_KEY_P0_MASKL                                                                */
4769 /* Look-up table 6: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
4770 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
4771 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
4772 /*****************************************************************************************/
4773
4774 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
4775 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
4776
4777
4778 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_OFFSET ( 0x00000180 )
4779
4780 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_OFFSET )
4781 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_ADDRESS ), (r) )
4782 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL_ADDRESS ), (v) )
4783
4784 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4785 typedef struct
4786 {
4787         /* MASKL */
4788         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4789 }
4790 __PACKING_ATTRIBUTE_STRUCT_END__
4791 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL ;
4792 #else
4793 typedef struct
4794 {
4795         /* MASKL */
4796         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4797 }
4798 __PACKING_ATTRIBUTE_STRUCT_END__
4799 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL ;
4800 #endif
4801
4802 /*****************************************************************************************/
4803 /* LKUP_TBL6_KEY_P0_MASKH                                                                */
4804 /* Look-up table 6: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
4805 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
4806 /* its own mask that represnted by two registers: MASKL and MASKH                        */
4807 /*****************************************************************************************/
4808
4809 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
4810 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
4811 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
4812 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
4813
4814
4815 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_OFFSET ( 0x00000184 )
4816
4817 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_OFFSET )
4818 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_ADDRESS ), (r) )
4819 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH_ADDRESS ), (v) )
4820
4821 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4822 typedef struct
4823 {
4824         /* reserved */
4825         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4826
4827         /* MASKH */
4828         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4829 }
4830 __PACKING_ATTRIBUTE_STRUCT_END__
4831 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH ;
4832 #else
4833 typedef struct
4834 {
4835         /* MASKH */
4836         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4837
4838         /* reserved */
4839         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4840 }
4841 __PACKING_ATTRIBUTE_STRUCT_END__
4842 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH ;
4843 #endif
4844
4845 /*****************************************************************************************/
4846 /* LKUP_TBL6_KEY_P1_MASKL                                                                */
4847 /* Look-up table 6: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
4848 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
4849 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
4850 /*****************************************************************************************/
4851
4852 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
4853 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
4854
4855
4856 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_OFFSET ( 0x00000188 )
4857
4858 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_OFFSET )
4859 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_ADDRESS ), (r) )
4860 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL_ADDRESS ), (v) )
4861
4862 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4863 typedef struct
4864 {
4865         /* MASKL */
4866         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4867 }
4868 __PACKING_ATTRIBUTE_STRUCT_END__
4869 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL ;
4870 #else
4871 typedef struct
4872 {
4873         /* MASKL */
4874         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4875 }
4876 __PACKING_ATTRIBUTE_STRUCT_END__
4877 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL ;
4878 #endif
4879
4880 /*****************************************************************************************/
4881 /* LKUP_TBL6_KEY_P1_MASKH                                                                */
4882 /* Look-up table 6: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
4883 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
4884 /* its own mask that represnted by two registers: MASKL and MASKH                        */
4885 /*****************************************************************************************/
4886
4887 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
4888 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
4889 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
4890 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
4891
4892
4893 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_OFFSET ( 0x0000018C )
4894
4895 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_OFFSET )
4896 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_ADDRESS ), (r) )
4897 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH_ADDRESS ), (v) )
4898
4899 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
4900 typedef struct
4901 {
4902         /* reserved */
4903         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4904
4905         /* MASKH */
4906         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4907 }
4908 __PACKING_ATTRIBUTE_STRUCT_END__
4909 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH ;
4910 #else
4911 typedef struct
4912 {
4913         /* MASKH */
4914         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4915
4916         /* reserved */
4917         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
4918 }
4919 __PACKING_ATTRIBUTE_STRUCT_END__
4920 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH ;
4921 #endif
4922
4923 /*****************************************************************************************/
4924 /* LKUP_TBL7_KEY_CFG                                                                     */
4925 /* Look-up table 7: Search key configuration parameters.    Key is based on two parts, e */
4926 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
4927 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
4928 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
4929 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
4930 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
4931 /* eader Descriptor) to 5 MSB of the search key.                                         */
4932 /*****************************************************************************************/
4933
4934 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
4935 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
4936 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
4937 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
4938 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
4939 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
4940 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
4941 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
4942 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4943 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
4944 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
4945 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
4946 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
4947 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
4948 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
4949 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
4950 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
4951 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
4952 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
4953 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
4954 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
4955 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
4956 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
4957 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
4958 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
4959 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
4960 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
4961 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
4962 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
4963 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
4964 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
4965 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
4966 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
4967 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
4968 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
4969 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
4970 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
4971 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
4972 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
4973 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
4974 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
4975 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
4976 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
4977 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
4978 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
4979 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
4980 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
4981 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
4982 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
4983 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
4984 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
4985 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
4986 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
4987 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
4988 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
4989 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
4990 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
4991 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
4992 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
4993 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
4994 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
4995 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
4996 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
4997 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
4998 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
4999 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
5000 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
5001 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
5002 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
5003 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
5004 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
5005 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
5006 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
5007 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
5008 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
5009
5010
5011 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_OFFSET ( 0x00000190 )
5012
5013 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_OFFSET )
5014 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_ADDRESS ), (r) )
5015 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG_ADDRESS ), (v) )
5016
5017 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5018 typedef struct
5019 {
5020         /* Resreved */
5021         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5022
5023         /* KEY_EXT */
5024         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5025
5026         /* shift_offset_p1 */
5027         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5028
5029         /* start_offset_p1 */
5030         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5031
5032         /* shift_offset_p0 */
5033         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5034
5035         /* start_offset_p0 */
5036         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5037 }
5038 __PACKING_ATTRIBUTE_STRUCT_END__
5039 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG ;
5040 #else
5041 typedef struct
5042 {
5043         /* start_offset_p0 */
5044         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5045
5046         /* shift_offset_p0 */
5047         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5048
5049         /* start_offset_p1 */
5050         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5051
5052         /* shift_offset_p1 */
5053         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5054
5055         /* KEY_EXT */
5056         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5057
5058         /* Resreved */
5059         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5060 }
5061 __PACKING_ATTRIBUTE_STRUCT_END__
5062 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG ;
5063 #endif
5064
5065 /*****************************************************************************************/
5066 /* LKUP_TBL7_KEY_P0_MASKL                                                                */
5067 /* Look-up table 7: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
5068 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
5069 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
5070 /*****************************************************************************************/
5071
5072 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
5073 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
5074
5075
5076 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_OFFSET ( 0x00000194 )
5077
5078 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_OFFSET )
5079 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_ADDRESS ), (r) )
5080 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL_ADDRESS ), (v) )
5081
5082 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5083 typedef struct
5084 {
5085         /* MASKL */
5086         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5087 }
5088 __PACKING_ATTRIBUTE_STRUCT_END__
5089 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL ;
5090 #else
5091 typedef struct
5092 {
5093         /* MASKL */
5094         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5095 }
5096 __PACKING_ATTRIBUTE_STRUCT_END__
5097 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL ;
5098 #endif
5099
5100 /*****************************************************************************************/
5101 /* LKUP_TBL7_KEY_P0_MASKH                                                                */
5102 /* Look-up table 7: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
5103 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
5104 /* its own mask that represnted by two registers: MASKL and MASKH                        */
5105 /*****************************************************************************************/
5106
5107 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
5108 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
5109 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
5110 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
5111
5112
5113 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_OFFSET ( 0x00000198 )
5114
5115 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_OFFSET )
5116 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_ADDRESS ), (r) )
5117 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH_ADDRESS ), (v) )
5118
5119 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5120 typedef struct
5121 {
5122         /* reserved */
5123         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5124
5125         /* MASKH */
5126         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5127 }
5128 __PACKING_ATTRIBUTE_STRUCT_END__
5129 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH ;
5130 #else
5131 typedef struct
5132 {
5133         /* MASKH */
5134         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5135
5136         /* reserved */
5137         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5138 }
5139 __PACKING_ATTRIBUTE_STRUCT_END__
5140 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH ;
5141 #endif
5142
5143 /*****************************************************************************************/
5144 /* LKUP_TBL7_KEY_P1_MASKL                                                                */
5145 /* Look-up table 7: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
5146 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
5147 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
5148 /*****************************************************************************************/
5149
5150 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
5151 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
5152
5153
5154 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_OFFSET ( 0x0000019C )
5155
5156 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_OFFSET )
5157 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_ADDRESS ), (r) )
5158 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL_ADDRESS ), (v) )
5159
5160 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5161 typedef struct
5162 {
5163         /* MASKL */
5164         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5165 }
5166 __PACKING_ATTRIBUTE_STRUCT_END__
5167 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL ;
5168 #else
5169 typedef struct
5170 {
5171         /* MASKL */
5172         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5173 }
5174 __PACKING_ATTRIBUTE_STRUCT_END__
5175 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL ;
5176 #endif
5177
5178 /*****************************************************************************************/
5179 /* LKUP_TBL7_KEY_P1_MASKH                                                                */
5180 /* Look-up table 7: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
5181 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
5182 /* its own mask that represnted by two registers: MASKL and MASKH                        */
5183 /*****************************************************************************************/
5184
5185 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
5186 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
5187 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
5188 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
5189
5190
5191 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_OFFSET ( 0x00000200 )
5192
5193 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_OFFSET )
5194 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_ADDRESS ), (r) )
5195 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH_ADDRESS ), (v) )
5196
5197 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5198 typedef struct
5199 {
5200         /* reserved */
5201         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5202
5203         /* MASKH */
5204         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5205 }
5206 __PACKING_ATTRIBUTE_STRUCT_END__
5207 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH ;
5208 #else
5209 typedef struct
5210 {
5211         /* MASKH */
5212         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5213
5214         /* reserved */
5215         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5216 }
5217 __PACKING_ATTRIBUTE_STRUCT_END__
5218 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH ;
5219 #endif
5220
5221 /*****************************************************************************************/
5222 /* LKUP_TBL8_KEY_CFG                                                                     */
5223 /* Look-up table 8: Search key configuration parameters.    Key is based on two parts, e */
5224 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
5225 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
5226 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
5227 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
5228 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
5229 /* eader Descriptor) to 5 MSB of the search key.                                         */
5230 /*****************************************************************************************/
5231
5232 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
5233 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
5234 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
5235 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
5236 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
5237 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
5238 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
5239 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
5240 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
5241 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
5242 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
5243 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
5244 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
5245 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
5246 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
5247 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
5248 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
5249 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
5250 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
5251 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
5252 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
5253 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
5254 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
5255 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
5256 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
5257 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
5258 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
5259 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
5260 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
5261 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
5262 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
5263 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
5264 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
5265 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
5266 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
5267 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
5268 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
5269 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
5270 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
5271 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
5272 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
5273 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
5274 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
5275 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
5276 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
5277 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
5278 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
5279 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
5280 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
5281 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
5282 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
5283 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
5284 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
5285 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
5286 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
5287 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
5288 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
5289 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
5290 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
5291 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
5292 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
5293 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
5294 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
5295 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
5296 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
5297 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
5298 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
5299 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
5300 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
5301 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
5302 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
5303 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
5304 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
5305 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
5306 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
5307
5308
5309 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_OFFSET ( 0x00000204 )
5310
5311 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_OFFSET )
5312 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_ADDRESS ), (r) )
5313 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG_ADDRESS ), (v) )
5314
5315 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5316 typedef struct
5317 {
5318         /* Resreved */
5319         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5320
5321         /* KEY_EXT */
5322         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5323
5324         /* shift_offset_p1 */
5325         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5326
5327         /* start_offset_p1 */
5328         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5329
5330         /* shift_offset_p0 */
5331         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5332
5333         /* start_offset_p0 */
5334         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5335 }
5336 __PACKING_ATTRIBUTE_STRUCT_END__
5337 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG ;
5338 #else
5339 typedef struct
5340 {
5341         /* start_offset_p0 */
5342         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5343
5344         /* shift_offset_p0 */
5345         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5346
5347         /* start_offset_p1 */
5348         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5349
5350         /* shift_offset_p1 */
5351         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5352
5353         /* KEY_EXT */
5354         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5355
5356         /* Resreved */
5357         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5358 }
5359 __PACKING_ATTRIBUTE_STRUCT_END__
5360 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG ;
5361 #endif
5362
5363 /*****************************************************************************************/
5364 /* LKUP_TBL8_KEY_P0_MASKL                                                                */
5365 /* Look-up table 8: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
5366 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
5367 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
5368 /*****************************************************************************************/
5369
5370 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
5371 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
5372
5373
5374 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_OFFSET ( 0x00000208 )
5375
5376 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_OFFSET )
5377 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_ADDRESS ), (r) )
5378 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL_ADDRESS ), (v) )
5379
5380 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5381 typedef struct
5382 {
5383         /* MASKL */
5384         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5385 }
5386 __PACKING_ATTRIBUTE_STRUCT_END__
5387 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL ;
5388 #else
5389 typedef struct
5390 {
5391         /* MASKL */
5392         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5393 }
5394 __PACKING_ATTRIBUTE_STRUCT_END__
5395 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL ;
5396 #endif
5397
5398 /*****************************************************************************************/
5399 /* LKUP_TBL8_KEY_P0_MASKH                                                                */
5400 /* Look-up table 8: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
5401 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
5402 /* its own mask that represnted by two registers: MASKL and MASKH                        */
5403 /*****************************************************************************************/
5404
5405 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
5406 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
5407 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
5408 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
5409
5410
5411 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_OFFSET ( 0x0000020C )
5412
5413 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_OFFSET )
5414 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_ADDRESS ), (r) )
5415 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH_ADDRESS ), (v) )
5416
5417 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5418 typedef struct
5419 {
5420         /* reserved */
5421         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5422
5423         /* MASKH */
5424         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5425 }
5426 __PACKING_ATTRIBUTE_STRUCT_END__
5427 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH ;
5428 #else
5429 typedef struct
5430 {
5431         /* MASKH */
5432         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5433
5434         /* reserved */
5435         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5436 }
5437 __PACKING_ATTRIBUTE_STRUCT_END__
5438 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH ;
5439 #endif
5440
5441 /*****************************************************************************************/
5442 /* LKUP_TBL8_KEY_P1_MASKL                                                                */
5443 /* Look-up table 8: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
5444 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
5445 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
5446 /*****************************************************************************************/
5447
5448 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
5449 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
5450
5451
5452 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_OFFSET ( 0x00000210 )
5453
5454 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_OFFSET )
5455 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_ADDRESS ), (r) )
5456 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL_ADDRESS ), (v) )
5457
5458 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5459 typedef struct
5460 {
5461         /* MASKL */
5462         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5463 }
5464 __PACKING_ATTRIBUTE_STRUCT_END__
5465 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL ;
5466 #else
5467 typedef struct
5468 {
5469         /* MASKL */
5470         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5471 }
5472 __PACKING_ATTRIBUTE_STRUCT_END__
5473 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL ;
5474 #endif
5475
5476 /*****************************************************************************************/
5477 /* LKUP_TBL8_KEY_P1_MASKH                                                                */
5478 /* Look-up table 8: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
5479 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
5480 /* its own mask that represnted by two registers: MASKL and MASKH                        */
5481 /*****************************************************************************************/
5482
5483 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
5484 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
5485 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
5486 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
5487
5488
5489 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_OFFSET ( 0x00000214 )
5490
5491 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_OFFSET )
5492 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_ADDRESS ), (r) )
5493 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH_ADDRESS ), (v) )
5494
5495 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5496 typedef struct
5497 {
5498         /* reserved */
5499         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5500
5501         /* MASKH */
5502         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5503 }
5504 __PACKING_ATTRIBUTE_STRUCT_END__
5505 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH ;
5506 #else
5507 typedef struct
5508 {
5509         /* MASKH */
5510         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5511
5512         /* reserved */
5513         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5514 }
5515 __PACKING_ATTRIBUTE_STRUCT_END__
5516 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH ;
5517 #endif
5518
5519 /*****************************************************************************************/
5520 /* LKUP_TBL9_KEY_CFG                                                                     */
5521 /* Look-up table 9: Search key configuration parameters.    Key is based on two parts, e */
5522 /* ach part includes 60-bit that generated on Parser Results (64 byte) array. The genera */
5523 /* tion of each part requries start_offset (from which word start collect 60 bit) and sh */
5524 /* ift_rotate paramter (in order to get flexibilty on variety of search key generation). */
5525 /*   Each part has its own mask (mask low on 32 low bits and mask high on 28 high bits), */
5526 /*  then two parts are ORed.  There is an option to add source port (taken from Ingres H */
5527 /* eader Descriptor) to 5 MSB of the search key.                                         */
5528 /*****************************************************************************************/
5529
5530 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_RESREVED1_RESREVED_VALUE                  ( 0x0 )
5531 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_RESREVED1_RESREVED_VALUE_RESET_VALUE      ( 0x0 )
5532 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_NO_EXT_VALUE                      ( 0x0 )
5533 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_NO_EXT_VALUE_RESET_VALUE          ( 0x0 )
5534 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_SP_ADD_EN_VALUE                   ( 0x1 )
5535 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_GEMFID_ADD_EN_VALUE               ( 0x2 )
5536 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_KEY_EXT_WAN_ADD_EN_VALUE                  ( 0x3 )
5537 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE             ( 0x0 )
5538 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
5539 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_4_VALUE             ( 0x1 )
5540 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_8_VALUE             ( 0x2 )
5541 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_12_VALUE            ( 0x3 )
5542 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_16_VALUE            ( 0x4 )
5543 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_20_VALUE            ( 0x5 )
5544 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_24_VALUE            ( 0x6 )
5545 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_28_VALUE            ( 0x7 )
5546 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_32_VALUE            ( 0x8 )
5547 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_36_VALUE            ( 0x9 )
5548 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_40_VALUE            ( 0xA )
5549 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_44_VALUE            ( 0xB )
5550 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_48_VALUE            ( 0xC )
5551 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_52_VALUE            ( 0xD )
5552 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_56_VALUE            ( 0xE )
5553 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P1_SHIFT_60_VALUE            ( 0xF )
5554 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_0_VALUE             ( 0x0 )
5555 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_0_VALUE_RESET_VALUE ( 0x0 )
5556 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_1_VALUE             ( 0x1 )
5557 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_2_VALUE             ( 0x2 )
5558 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_3_VALUE             ( 0x3 )
5559 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_4_VALUE             ( 0x4 )
5560 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_5_VALUE             ( 0x5 )
5561 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_6_VALUE             ( 0x6 )
5562 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_7_VALUE             ( 0x7 )
5563 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_8_VALUE             ( 0x8 )
5564 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_9_VALUE             ( 0x9 )
5565 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_10_VALUE            ( 0xA )
5566 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_11_VALUE            ( 0xB )
5567 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_12_VALUE            ( 0xC )
5568 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_13_VALUE            ( 0xD )
5569 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_START_14_VALUE            ( 0xE )
5570 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P1_RESERVED_VALUE            ( 0xF )
5571 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE             ( 0x0 )
5572 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_0_VALUE_RESET_VALUE ( 0x0 )
5573 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_4_VALUE             ( 0x1 )
5574 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_8_VALUE             ( 0x2 )
5575 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_12_VALUE            ( 0x3 )
5576 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_16_VALUE            ( 0x4 )
5577 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_20_VALUE            ( 0x5 )
5578 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_24_VALUE            ( 0x6 )
5579 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_28_VALUE            ( 0x7 )
5580 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_32_VALUE            ( 0x8 )
5581 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_36_VALUE            ( 0x9 )
5582 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_40_VALUE            ( 0xA )
5583 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_44_VALUE            ( 0xB )
5584 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_48_VALUE            ( 0xC )
5585 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_52_VALUE            ( 0xD )
5586 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_56_VALUE            ( 0xE )
5587 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_SHIFT_OFFSET_P0_SHIFT_60_VALUE            ( 0xF )
5588 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_0_VALUE             ( 0x0 )
5589 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_0_VALUE_RESET_VALUE ( 0x0 )
5590 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_1_VALUE             ( 0x1 )
5591 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_2_VALUE             ( 0x2 )
5592 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_3_VALUE             ( 0x3 )
5593 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_4_VALUE             ( 0x4 )
5594 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_5_VALUE             ( 0x5 )
5595 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_6_VALUE             ( 0x6 )
5596 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_7_VALUE             ( 0x7 )
5597 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_8_VALUE             ( 0x8 )
5598 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_9_VALUE             ( 0x9 )
5599 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_10_VALUE            ( 0xA )
5600 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_11_VALUE            ( 0xB )
5601 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_12_VALUE            ( 0xC )
5602 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_13_VALUE            ( 0xD )
5603 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_START_14_VALUE            ( 0xE )
5604 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_START_OFFSET_P0_RESERVED_VALUE            ( 0xF )
5605
5606
5607 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_OFFSET ( 0x00000218 )
5608
5609 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_OFFSET )
5610 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_ADDRESS ), (r) )
5611 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG_ADDRESS ), (v) )
5612
5613 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5614 typedef struct
5615 {
5616         /* Resreved */
5617         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5618
5619         /* KEY_EXT */
5620         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5621
5622         /* shift_offset_p1 */
5623         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5624
5625         /* start_offset_p1 */
5626         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5627
5628         /* shift_offset_p0 */
5629         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5630
5631         /* start_offset_p0 */
5632         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5633 }
5634 __PACKING_ATTRIBUTE_STRUCT_END__
5635 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG ;
5636 #else
5637 typedef struct
5638 {
5639         /* start_offset_p0 */
5640         uint32_t start_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5641
5642         /* shift_offset_p0 */
5643         uint32_t shift_offset_p0        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5644
5645         /* start_offset_p1 */
5646         uint32_t start_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5647
5648         /* shift_offset_p1 */
5649         uint32_t shift_offset_p1        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5650
5651         /* KEY_EXT */
5652         uint32_t key_ext                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5653
5654         /* Resreved */
5655         uint32_t resreved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5656 }
5657 __PACKING_ATTRIBUTE_STRUCT_END__
5658 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG ;
5659 #endif
5660
5661 /*****************************************************************************************/
5662 /* LKUP_TBL9_KEY_P0_MASKL                                                                */
5663 /* Look-up table 9: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
5664 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
5665 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
5666 /*****************************************************************************************/
5667
5668 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
5669 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
5670
5671
5672 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_OFFSET ( 0x0000021C )
5673
5674 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_OFFSET )
5675 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_ADDRESS ), (r) )
5676 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL_ADDRESS ), (v) )
5677
5678 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5679 typedef struct
5680 {
5681         /* MASKL */
5682         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5683 }
5684 __PACKING_ATTRIBUTE_STRUCT_END__
5685 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL ;
5686 #else
5687 typedef struct
5688 {
5689         /* MASKL */
5690         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5691 }
5692 __PACKING_ATTRIBUTE_STRUCT_END__
5693 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL ;
5694 #endif
5695
5696 /*****************************************************************************************/
5697 /* LKUP_TBL9_KEY_P0_MASKH                                                                */
5698 /* Look-up table 9: Mask on bits [59:32] of Part 0    Key is based on two parts, each pa */
5699 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
5700 /* its own mask that represnted by two registers: MASKL and MASKH                        */
5701 /*****************************************************************************************/
5702
5703 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
5704 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
5705 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
5706 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
5707
5708
5709 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_OFFSET ( 0x00000220 )
5710
5711 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_OFFSET )
5712 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_ADDRESS ), (r) )
5713 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH_ADDRESS ), (v) )
5714
5715 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5716 typedef struct
5717 {
5718         /* reserved */
5719         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5720
5721         /* MASKH */
5722         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5723 }
5724 __PACKING_ATTRIBUTE_STRUCT_END__
5725 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH ;
5726 #else
5727 typedef struct
5728 {
5729         /* MASKH */
5730         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5731
5732         /* reserved */
5733         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5734 }
5735 __PACKING_ATTRIBUTE_STRUCT_END__
5736 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH ;
5737 #endif
5738
5739 /*****************************************************************************************/
5740 /* LKUP_TBL9_KEY_P1_MASKL                                                                */
5741 /* Look-up table 9: Mask on bits [31:0] of Part 1    Key is based on two parts, each par */
5742 /* t includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has i */
5743 /* ts own mask that represnted by two registers: MASKL and MASKH                         */
5744 /*****************************************************************************************/
5745
5746 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_MASKL_MASKL_VALUE             ( 0x0 )
5747 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_MASKL_MASKL_VALUE_RESET_VALUE ( 0x0 )
5748
5749
5750 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_OFFSET ( 0x00000224 )
5751
5752 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_OFFSET )
5753 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_ADDRESS ), (r) )
5754 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL_ADDRESS ), (v) )
5755
5756 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5757 typedef struct
5758 {
5759         /* MASKL */
5760         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5761 }
5762 __PACKING_ATTRIBUTE_STRUCT_END__
5763 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL ;
5764 #else
5765 typedef struct
5766 {
5767         /* MASKL */
5768         uint32_t maskl  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5769 }
5770 __PACKING_ATTRIBUTE_STRUCT_END__
5771 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL ;
5772 #endif
5773
5774 /*****************************************************************************************/
5775 /* LKUP_TBL9_KEY_P1_MASKH                                                                */
5776 /* Look-up table 9: Mask on bits [59:32] of Part 1    Key is based on two parts, each pa */
5777 /* rt includes 60-bit that generated on Parser Results (64 byte) array.   Each Part has  */
5778 /* its own mask that represnted by two registers: MASKL and MASKH                        */
5779 /*****************************************************************************************/
5780
5781 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_RESERVED_RESERVED_VALUE             ( 0x0 )
5782 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_RESERVED_RESERVED_VALUE_RESET_VALUE ( 0x0 )
5783 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_MASKH_MASKH_VALUE                   ( 0x0 )
5784 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_MASKH_MASKH_VALUE_RESET_VALUE       ( 0x0 )
5785
5786
5787 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_OFFSET ( 0x00000228 )
5788
5789 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_ADDRESS     ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_OFFSET )
5790 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_READ( r )   READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_ADDRESS ), (r) )
5791 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_WRITE( v )  WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH_ADDRESS ), (v) )
5792
5793 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5794 typedef struct
5795 {
5796         /* reserved */
5797         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5798
5799         /* MASKH */
5800         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5801 }
5802 __PACKING_ATTRIBUTE_STRUCT_END__
5803 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH ;
5804 #else
5805 typedef struct
5806 {
5807         /* MASKH */
5808         uint32_t maskh          : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5809
5810         /* reserved */
5811         uint32_t reserved       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5812 }
5813 __PACKING_ATTRIBUTE_STRUCT_END__
5814 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH ;
5815 #endif
5816
5817 /*****************************************************************************************/
5818 /* LKUP_TBL0_GL_MASK                                                                     */
5819 /* Look-up table 0: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
5820 /* ) On general key generation, the global mask is ANDed with final result of key (after */
5821 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
5822 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
5823 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
5824 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
5825 /* 00FF                                                                                  */
5826 /*****************************************************************************************/
5827
5828 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
5829 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
5830 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
5831 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
5832
5833
5834 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_OFFSET ( 0x0000022C )
5835
5836 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_OFFSET )
5837 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_ADDRESS ), (r) )
5838 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK_ADDRESS ), (v) )
5839
5840 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5841 typedef struct
5842 {
5843         /* reserved */
5844         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5845
5846         /* MASK_NIBBLE_CODE */
5847         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5848 }
5849 __PACKING_ATTRIBUTE_STRUCT_END__
5850 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK ;
5851 #else
5852 typedef struct
5853 {
5854         /* MASK_NIBBLE_CODE */
5855         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5856
5857         /* reserved */
5858         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5859 }
5860 __PACKING_ATTRIBUTE_STRUCT_END__
5861 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK ;
5862 #endif
5863
5864 /*****************************************************************************************/
5865 /* LKUP_TBL1_GL_MASK                                                                     */
5866 /* Look-up table 1: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
5867 /* ) On general key generation, the global mask is ANDed with final result of key (after */
5868 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
5869 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
5870 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
5871 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
5872 /* 00FF                                                                                  */
5873 /*****************************************************************************************/
5874
5875 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
5876 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
5877 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
5878 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
5879
5880
5881 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_OFFSET ( 0x00000230 )
5882
5883 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_OFFSET )
5884 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_ADDRESS ), (r) )
5885 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK_ADDRESS ), (v) )
5886
5887 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5888 typedef struct
5889 {
5890         /* reserved */
5891         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5892
5893         /* MASK_NIBBLE_CODE */
5894         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5895 }
5896 __PACKING_ATTRIBUTE_STRUCT_END__
5897 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK ;
5898 #else
5899 typedef struct
5900 {
5901         /* MASK_NIBBLE_CODE */
5902         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5903
5904         /* reserved */
5905         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5906 }
5907 __PACKING_ATTRIBUTE_STRUCT_END__
5908 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK ;
5909 #endif
5910
5911 /*****************************************************************************************/
5912 /* LKUP_TBL2_GL_MASK                                                                     */
5913 /* Look-up table 2: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
5914 /* ) On general key generation, the global mask is ANDed with final result of key (after */
5915 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
5916 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
5917 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
5918 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
5919 /* 00FF                                                                                  */
5920 /*****************************************************************************************/
5921
5922 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
5923 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
5924 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
5925 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
5926
5927
5928 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_OFFSET ( 0x00000234 )
5929
5930 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_OFFSET )
5931 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_ADDRESS ), (r) )
5932 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK_ADDRESS ), (v) )
5933
5934 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5935 typedef struct
5936 {
5937         /* reserved */
5938         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5939
5940         /* MASK_NIBBLE_CODE */
5941         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5942 }
5943 __PACKING_ATTRIBUTE_STRUCT_END__
5944 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK ;
5945 #else
5946 typedef struct
5947 {
5948         /* MASK_NIBBLE_CODE */
5949         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5950
5951         /* reserved */
5952         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5953 }
5954 __PACKING_ATTRIBUTE_STRUCT_END__
5955 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK ;
5956 #endif
5957
5958 /*****************************************************************************************/
5959 /* LKUP_TBL3_GL_MASK                                                                     */
5960 /* Look-up table 3: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
5961 /* ) On general key generation, the global mask is ANDed with final result of key (after */
5962 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
5963 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
5964 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
5965 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
5966 /* 00FF                                                                                  */
5967 /*****************************************************************************************/
5968
5969 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
5970 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
5971 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
5972 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
5973
5974
5975 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_OFFSET ( 0x00000238 )
5976
5977 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_OFFSET )
5978 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_ADDRESS ), (r) )
5979 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK_ADDRESS ), (v) )
5980
5981 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
5982 typedef struct
5983 {
5984         /* reserved */
5985         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5986
5987         /* MASK_NIBBLE_CODE */
5988         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5989 }
5990 __PACKING_ATTRIBUTE_STRUCT_END__
5991 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK ;
5992 #else
5993 typedef struct
5994 {
5995         /* MASK_NIBBLE_CODE */
5996         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
5997
5998         /* reserved */
5999         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6000 }
6001 __PACKING_ATTRIBUTE_STRUCT_END__
6002 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK ;
6003 #endif
6004
6005 /*****************************************************************************************/
6006 /* LKUP_TBL4_GL_MASK                                                                     */
6007 /* Look-up table 4: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
6008 /* ) On general key generation, the global mask is ANDed with final result of key (after */
6009 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
6010 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
6011 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
6012 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
6013 /* 00FF                                                                                  */
6014 /*****************************************************************************************/
6015
6016 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
6017 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
6018 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
6019 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
6020
6021
6022 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_OFFSET ( 0x0000023C )
6023
6024 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_OFFSET )
6025 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_ADDRESS ), (r) )
6026 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK_ADDRESS ), (v) )
6027
6028 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6029 typedef struct
6030 {
6031         /* reserved */
6032         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6033
6034         /* MASK_NIBBLE_CODE */
6035         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6036 }
6037 __PACKING_ATTRIBUTE_STRUCT_END__
6038 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK ;
6039 #else
6040 typedef struct
6041 {
6042         /* MASK_NIBBLE_CODE */
6043         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6044
6045         /* reserved */
6046         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6047 }
6048 __PACKING_ATTRIBUTE_STRUCT_END__
6049 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK ;
6050 #endif
6051
6052 /*****************************************************************************************/
6053 /* LKUP_TBL5_GL_MASK                                                                     */
6054 /* Look-up table 5: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
6055 /* ) On general key generation, the global mask is ANDed with final result of key (after */
6056 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
6057 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
6058 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
6059 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
6060 /* 00FF                                                                                  */
6061 /*****************************************************************************************/
6062
6063 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
6064 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
6065 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
6066 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
6067
6068
6069 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_OFFSET ( 0x00000240 )
6070
6071 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_OFFSET )
6072 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_ADDRESS ), (r) )
6073 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK_ADDRESS ), (v) )
6074
6075 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6076 typedef struct
6077 {
6078         /* reserved */
6079         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6080
6081         /* MASK_NIBBLE_CODE */
6082         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6083 }
6084 __PACKING_ATTRIBUTE_STRUCT_END__
6085 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK ;
6086 #else
6087 typedef struct
6088 {
6089         /* MASK_NIBBLE_CODE */
6090         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6091
6092         /* reserved */
6093         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6094 }
6095 __PACKING_ATTRIBUTE_STRUCT_END__
6096 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK ;
6097 #endif
6098
6099 /*****************************************************************************************/
6100 /* LKUP_TBL6_GL_MASK                                                                     */
6101 /* Look-up table 6: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
6102 /* ) On general key generation, the global mask is ANDed with final result of key (after */
6103 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
6104 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
6105 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
6106 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
6107 /* 00FF                                                                                  */
6108 /*****************************************************************************************/
6109
6110 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
6111 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
6112 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
6113 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
6114
6115
6116 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_OFFSET ( 0x00000244 )
6117
6118 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_OFFSET )
6119 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_ADDRESS ), (r) )
6120 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK_ADDRESS ), (v) )
6121
6122 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6123 typedef struct
6124 {
6125         /* reserved */
6126         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6127
6128         /* MASK_NIBBLE_CODE */
6129         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6130 }
6131 __PACKING_ATTRIBUTE_STRUCT_END__
6132 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK ;
6133 #else
6134 typedef struct
6135 {
6136         /* MASK_NIBBLE_CODE */
6137         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6138
6139         /* reserved */
6140         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6141 }
6142 __PACKING_ATTRIBUTE_STRUCT_END__
6143 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK ;
6144 #endif
6145
6146 /*****************************************************************************************/
6147 /* LKUP_TBL7_GL_MASK                                                                     */
6148 /* Look-up table 7: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
6149 /* ) On general key generation, the global mask is ANDed with final result of key (after */
6150 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
6151 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
6152 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
6153 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
6154 /* 00FF                                                                                  */
6155 /*****************************************************************************************/
6156
6157 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
6158 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
6159 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
6160 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
6161
6162
6163 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_OFFSET ( 0x00000248 )
6164
6165 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_OFFSET )
6166 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_ADDRESS ), (r) )
6167 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK_ADDRESS ), (v) )
6168
6169 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6170 typedef struct
6171 {
6172         /* reserved */
6173         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6174
6175         /* MASK_NIBBLE_CODE */
6176         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6177 }
6178 __PACKING_ATTRIBUTE_STRUCT_END__
6179 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK ;
6180 #else
6181 typedef struct
6182 {
6183         /* MASK_NIBBLE_CODE */
6184         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6185
6186         /* reserved */
6187         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6188 }
6189 __PACKING_ATTRIBUTE_STRUCT_END__
6190 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK ;
6191 #endif
6192
6193 /*****************************************************************************************/
6194 /* LKUP_TBL8_GL_MASK                                                                     */
6195 /* Look-up table 8: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
6196 /* ) On general key generation, the global mask is ANDed with final result of key (after */
6197 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
6198 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
6199 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
6200 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
6201 /* 00FF                                                                                  */
6202 /*****************************************************************************************/
6203
6204 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
6205 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
6206 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
6207 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
6208
6209
6210 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_OFFSET ( 0x0000024C )
6211
6212 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_OFFSET )
6213 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_ADDRESS ), (r) )
6214 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK_ADDRESS ), (v) )
6215
6216 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6217 typedef struct
6218 {
6219         /* reserved */
6220         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6221
6222         /* MASK_NIBBLE_CODE */
6223         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6224 }
6225 __PACKING_ATTRIBUTE_STRUCT_END__
6226 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK ;
6227 #else
6228 typedef struct
6229 {
6230         /* MASK_NIBBLE_CODE */
6231         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6232
6233         /* reserved */
6234         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6235 }
6236 __PACKING_ATTRIBUTE_STRUCT_END__
6237 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK ;
6238 #endif
6239
6240 /*****************************************************************************************/
6241 /* LKUP_TBL9_GL_MASK                                                                     */
6242 /* Look-up table 9: Global Mask on 60-bits    Global Mask is applied in two cases:    (1 */
6243 /* ) On general key generation, the global mask is ANDed with final result of key (after */
6244 /*  choosing start offset, shift offsets and ORing of two parts of the key).     (2) On  */
6245 /* comparison between HASH result to LUT entry that done by look-up engine.    Each Glob */
6246 /* al Mask is represnted by one register in bibble (4-bit) resolution, i.e. value of glo */
6247 /* bal_mask register = 0x13 means that the 60-bit key will be masked with following: 0xF */
6248 /* 00FF                                                                                  */
6249 /*****************************************************************************************/
6250
6251 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_R1_RESERVED_VALUE                                   ( 0x0 )
6252 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_R1_RESERVED_VALUE_RESET_VALUE                       ( 0x0 )
6253 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE             ( 0x0 )
6254 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_MASK_NIBBLE_CODE_MASK_NIBBLE_CODE_VALUE_RESET_VALUE ( 0x0 )
6255
6256
6257 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_OFFSET ( 0x00000250 )
6258
6259 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_ADDRESS          ( IH_REGS_LOOKUP_CONFIGURATION_ADDRESS + IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_OFFSET )
6260 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_READ( r )        READ_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_ADDRESS ), (r) )
6261 #define IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_WRITE( v )       WRITE_32( ( IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK_ADDRESS ), (v) )
6262
6263 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6264 typedef struct
6265 {
6266         /* reserved */
6267         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6268
6269         /* MASK_NIBBLE_CODE */
6270         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6271 }
6272 __PACKING_ATTRIBUTE_STRUCT_END__
6273 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK ;
6274 #else
6275 typedef struct
6276 {
6277         /* MASK_NIBBLE_CODE */
6278         uint32_t mask_nibble_code       : 15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6279
6280         /* reserved */
6281         uint32_t r1                     : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6282 }
6283 __PACKING_ATTRIBUTE_STRUCT_END__
6284 IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK ;
6285 #endif
6286
6287 /*****************************************************************************************/
6288 /* DA_FILT0_VAL_L                                                                        */
6289 /* Config DA filter 31:0                                                                 */
6290 /*****************************************************************************************/
6291
6292 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
6293 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
6294
6295
6296 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_OFFSET ( 0x00000000 )
6297
6298 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_OFFSET )
6299 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_ADDRESS ), (r) )
6300 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L_ADDRESS ), (v) )
6301
6302 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6303 typedef struct
6304 {
6305         /* DA_FILT_LSB */
6306         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6307 }
6308 __PACKING_ATTRIBUTE_STRUCT_END__
6309 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L ;
6310 #else
6311 typedef struct
6312 {
6313         /* DA_FILT_LSB */
6314         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6315 }
6316 __PACKING_ATTRIBUTE_STRUCT_END__
6317 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L ;
6318 #endif
6319
6320 /*****************************************************************************************/
6321 /* DA_FILT0_MASK_L                                                                       */
6322 /* Config DA Filter mask 15:0                                                            */
6323 /*****************************************************************************************/
6324
6325 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE             ( 0x0 )
6326 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
6327
6328
6329 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_OFFSET ( 0x00000004 )
6330
6331 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_ADDRESS       ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_OFFSET )
6332 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_READ( r )     READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_ADDRESS ), (r) )
6333 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_WRITE( v )    WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L_ADDRESS ), (v) )
6334
6335 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6336 typedef struct
6337 {
6338         /* DA_FILT_MASK_L */
6339         uint32_t da_filt0_mask_l        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6340 }
6341 __PACKING_ATTRIBUTE_STRUCT_END__
6342 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L ;
6343 #else
6344 typedef struct
6345 {
6346         /* DA_FILT_MASK_L */
6347         uint32_t da_filt0_mask_l        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6348 }
6349 __PACKING_ATTRIBUTE_STRUCT_END__
6350 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L ;
6351 #endif
6352
6353 /*****************************************************************************************/
6354 /* DA_FILT0_CFG_H                                                                        */
6355 /* DA Filter0 Value & Mask highest bits 15:0                                             */
6356 /*****************************************************************************************/
6357
6358 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
6359 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
6360 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE              ( 0x0 )
6361 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE_RESET_VALUE  ( 0x0 )
6362
6363
6364 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_OFFSET ( 0x00000008 )
6365
6366 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_OFFSET )
6367 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_ADDRESS ), (r) )
6368 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H_ADDRESS ), (v) )
6369
6370 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6371 typedef struct
6372 {
6373         /* DA_FILT_MASK_MSB */
6374         uint32_t da_filt_mask_msb       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6375
6376         /* DA_FILT_VAL_MSB */
6377         uint32_t da_filt_val_msb        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6378 }
6379 __PACKING_ATTRIBUTE_STRUCT_END__
6380 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H ;
6381 #else
6382 typedef struct
6383 {
6384         /* DA_FILT_VAL_MSB */
6385         uint32_t da_filt_val_msb        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6386
6387         /* DA_FILT_MASK_MSB */
6388         uint32_t da_filt_mask_msb       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6389 }
6390 __PACKING_ATTRIBUTE_STRUCT_END__
6391 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H ;
6392 #endif
6393
6394 /*****************************************************************************************/
6395 /* PARSER_CFG                                                                            */
6396 /* Parser Configuration                                                                  */
6397 /*****************************************************************************************/
6398
6399 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_RESERVED1_RESERVED_VALUE                  ( 0x0 )
6400 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_RESERVED1_RESERVED_VALUE_RESET_VALUE      ( 0x0 )
6401 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_0_DEFAULT_VALUE              ( 0x0 )
6402 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_0_DEFAULT_VALUE_RESET_VALUE  ( 0x0 )
6403 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_PPP_CODE_1_IPV6_DEFAULT_VALUE             ( 0x0 )
6404 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_PPP_CODE_1_IPV6_DEFAULT_VALUE_RESET_VALUE ( 0x0 )
6405 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_RESET_VALUE                  ( 0xF )
6406 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_EXCEPTION_EN_RESET_VALUE_RESET_VALUE      ( 0xF )
6407 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_TCP_FLAGS_FILT_RESET_VALUE                ( 0x0 )
6408 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_TCP_FLAGS_FILT_RESET_VALUE_RESET_VALUE    ( 0x0 )
6409
6410
6411 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_OFFSET ( 0x0000000C )
6412
6413 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_ADDRESS    ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_OFFSET )
6414 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_READ( r )  READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_ADDRESS ), (r) )
6415 #define IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_WRITE( v ) WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG_ADDRESS ), (v) )
6416
6417 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6418 typedef struct
6419 {
6420         /* RESERVED */
6421         uint32_t reserved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6422
6423         /* exception_en_0 */
6424         uint32_t exception_en_0         : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6425
6426         /* ppp_code_1_ipv6 */
6427         uint32_t ppp_code_1_ipv6        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6428
6429         /* EXCEPTION_EN */
6430         uint32_t exception_en           : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6431
6432         /* TCP_FLAGS_TCP_FILTER */
6433         uint32_t tcp_flags_filt         : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6434 }
6435 __PACKING_ATTRIBUTE_STRUCT_END__
6436 IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG ;
6437 #else
6438 typedef struct
6439 {
6440         /* TCP_FLAGS_TCP_FILTER */
6441         uint32_t tcp_flags_filt         : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6442
6443         /* EXCEPTION_EN */
6444         uint32_t exception_en           : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6445
6446         /* ppp_code_1_ipv6 */
6447         uint32_t ppp_code_1_ipv6        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6448
6449         /* exception_en_0 */
6450         uint32_t exception_en_0         : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6451
6452         /* RESERVED */
6453         uint32_t reserved1              : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6454 }
6455 __PACKING_ATTRIBUTE_STRUCT_END__
6456 IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG ;
6457 #endif
6458
6459 /*****************************************************************************************/
6460 /* QTAG_Ethertype                                                                        */
6461 /* Ethertype values to identify the presence of VLAN QTAG                                */
6462 /*****************************************************************************************/
6463
6464 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_RESET_VALUE             ( 0x0 )
6465 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_1_RESET_VALUE_RESET_VALUE ( 0x0 )
6466 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_RESET_VALUE             ( 0x0 )
6467 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ETHTYPE_QTAG_0_RESET_VALUE_RESET_VALUE ( 0x0 )
6468
6469
6470 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_OFFSET ( 0x00000010 )
6471
6472 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ADDRESS          ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_OFFSET )
6473 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_READ( r )        READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ADDRESS ), (r) )
6474 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_WRITE( v )       WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE_ADDRESS ), (v) )
6475
6476 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6477 typedef struct
6478 {
6479         /* Ethertyp_for_Qtag_1 */
6480         uint32_t ethtype_qtag_1 : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6481
6482         /* Ethertyp_for_Qtag_0 */
6483         uint32_t ethtype_qtag_0 : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6484 }
6485 __PACKING_ATTRIBUTE_STRUCT_END__
6486 IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE ;
6487 #else
6488 typedef struct
6489 {
6490         /* Ethertyp_for_Qtag_0 */
6491         uint32_t ethtype_qtag_0 : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6492
6493         /* Ethertyp_for_Qtag_1 */
6494         uint32_t ethtype_qtag_1 : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6495 }
6496 __PACKING_ATTRIBUTE_STRUCT_END__
6497 IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE ;
6498 #endif
6499
6500 /*****************************************************************************************/
6501 /* QTAG_Nesting                                                                          */
6502 /* Qtag Nesting config                                                                   */
6503 /*****************************************************************************************/
6504
6505 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED1_RESET_VALUE                 ( 0x0 )
6506 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_RESERVED1_RESET_VALUE_RESET_VALUE     ( 0x0 )
6507 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG5_NEST_DISABLED_VALUE             ( 0x0 )
6508 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG5_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
6509 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG4_NEST_DISABLED_VALUE             ( 0x0 )
6510 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG4_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
6511 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG3_NEST_DISABLED_VALUE             ( 0x0 )
6512 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG3_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
6513 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG2_NEST_RESET_VALUE                ( 0x0 )
6514 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG2_NEST_RESET_VALUE_RESET_VALUE    ( 0x0 )
6515 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG1_NEST_DISABLED_VALUE             ( 0x0 )
6516 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG1_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
6517 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG0_NEST_DISABLED_VALUE             ( 0x0 )
6518 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_QTAG0_NEST_DISABLED_VALUE_RESET_VALUE ( 0x0 )
6519
6520
6521 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_OFFSET ( 0x00000014 )
6522
6523 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_ADDRESS     ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_OFFSET )
6524 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_READ( r )   READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_ADDRESS ), (r) )
6525 #define IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_WRITE( v )  WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST_ADDRESS ), (v) )
6526
6527 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6528 typedef struct
6529 {
6530         /* Reserved */
6531         uint32_t reserved1      : 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6532
6533         /* QTAG_5_Nesting_Config */
6534         uint32_t qtag5_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6535
6536         /* QTAG_4_Nesting_Config */
6537         uint32_t qtag4_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6538
6539         /* QTAG_3_Nesting_Config */
6540         uint32_t qtag3_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6541
6542         /* QTAG_2_Nesting_Config */
6543         uint32_t qtag2_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6544
6545         /* QTAG_1_Nesting_Config */
6546         uint32_t qtag1_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6547
6548         /* QTAG_0_Nesting_Config */
6549         uint32_t qtag0_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6550 }
6551 __PACKING_ATTRIBUTE_STRUCT_END__
6552 IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST ;
6553 #else
6554 typedef struct
6555 {
6556         /* QTAG_0_Nesting_Config */
6557         uint32_t qtag0_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6558
6559         /* QTAG_1_Nesting_Config */
6560         uint32_t qtag1_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6561
6562         /* QTAG_2_Nesting_Config */
6563         uint32_t qtag2_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6564
6565         /* QTAG_3_Nesting_Config */
6566         uint32_t qtag3_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6567
6568         /* QTAG_4_Nesting_Config */
6569         uint32_t qtag4_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6570
6571         /* QTAG_5_Nesting_Config */
6572         uint32_t qtag5_nest     : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6573
6574         /* Reserved */
6575         uint32_t reserved1      : 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6576 }
6577 __PACKING_ATTRIBUTE_STRUCT_END__
6578 IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST ;
6579 #endif
6580
6581 /*****************************************************************************************/
6582 /* Snap_organization_code                                                                */
6583 /* Identifies SNAP tunneling organization code                                           */
6584 /*****************************************************************************************/
6585
6586 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED1_RESET_VALUE                 ( 0x0 )
6587 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_RESERVED1_RESET_VALUE_RESET_VALUE     ( 0x0 )
6588 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_DISABLED_VALUE               ( 0x0 )
6589 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_DISABLED_VALUE_RESET_VALUE   ( 0x0 )
6590 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_8021Q_ENABLED_VALUE                ( 0x0 )
6591 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_DISABLED_VALUE             ( 0x0 )
6592 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_DISABLED_VALUE_RESET_VALUE ( 0x0 )
6593 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_EN_RFC1042_ENABLED_VALUE              ( 0x1 )
6594 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_RESET_VALUE                      ( 0x0 )
6595 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_CODE_RESET_VALUE_RESET_VALUE          ( 0x0 )
6596
6597
6598 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_OFFSET ( 0x00000018 )
6599
6600 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_ADDRESS         ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_OFFSET )
6601 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_READ( r )       READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_ADDRESS ), (r) )
6602 #define IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_WRITE( v )      WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE_ADDRESS ), (v) )
6603
6604 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6605 typedef struct
6606 {
6607         /* reserved */
6608         uint32_t reserved1      : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6609
6610         /* 802.1Q_ehternet_encapsulation */
6611         uint32_t en_8021q       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6612
6613         /* RFC1042_ethernet_encapsulation_enable */
6614         uint32_t en_rfc1042     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6615
6616         /* Organization_Code */
6617         uint32_t code           : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6618 }
6619 __PACKING_ATTRIBUTE_STRUCT_END__
6620 IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE ;
6621 #else
6622 typedef struct
6623 {
6624         /* Organization_Code */
6625         uint32_t code           : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6626
6627         /* RFC1042_ethernet_encapsulation_enable */
6628         uint32_t en_rfc1042     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6629
6630         /* 802.1Q_ehternet_encapsulation */
6631         uint32_t en_8021q       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6632
6633         /* reserved */
6634         uint32_t reserved1      : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6635 }
6636 __PACKING_ATTRIBUTE_STRUCT_END__
6637 IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE ;
6638 #endif
6639
6640 /*****************************************************************************************/
6641 /* User_Ethertype_configurtion_0_1                                                       */
6642 /* Configures user Ethertype values                                                      */
6643 /*****************************************************************************************/
6644
6645 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_RESET_VALUE             ( 0x0 )
6646 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_1_RESET_VALUE_RESET_VALUE ( 0x0 )
6647 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_RESET_VALUE             ( 0x0 )
6648 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ETHYPE_0_RESET_VALUE_RESET_VALUE ( 0x0 )
6649
6650
6651 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_OFFSET ( 0x0000001C )
6652
6653 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_OFFSET )
6654 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ADDRESS ), (r) )
6655 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1_ADDRESS ), (v) )
6656
6657 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6658 typedef struct
6659 {
6660         /* User_Ethertype_1 */
6661         uint32_t ethype_1       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6662
6663         /* User_Ethertype_0 */
6664         uint32_t ethype_0       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6665 }
6666 __PACKING_ATTRIBUTE_STRUCT_END__
6667 IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1 ;
6668 #else
6669 typedef struct
6670 {
6671         /* User_Ethertype_0 */
6672         uint32_t ethype_0       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6673
6674         /* User_Ethertype_1 */
6675         uint32_t ethype_1       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6676 }
6677 __PACKING_ATTRIBUTE_STRUCT_END__
6678 IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1 ;
6679 #endif
6680
6681 /*****************************************************************************************/
6682 /* User_Ethertype_configurtion_2_3                                                       */
6683 /* Configures user Ethertype values                                                      */
6684 /*****************************************************************************************/
6685
6686 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_RESET_VALUE             ( 0x0 )
6687 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_3_RESET_VALUE_RESET_VALUE ( 0x0 )
6688 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_RESET_VALUE             ( 0x0 )
6689 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ETHYPE_2_RESET_VALUE_RESET_VALUE ( 0x0 )
6690
6691
6692 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_OFFSET ( 0x00000020 )
6693
6694 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_OFFSET )
6695 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ADDRESS ), (r) )
6696 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3_ADDRESS ), (v) )
6697
6698 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6699 typedef struct
6700 {
6701         /* User_Ethertype_3 */
6702         uint32_t ethype_3       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6703
6704         /* User_Ethertype_2 */
6705         uint32_t ethype_2       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6706 }
6707 __PACKING_ATTRIBUTE_STRUCT_END__
6708 IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3 ;
6709 #else
6710 typedef struct
6711 {
6712         /* User_Ethertype_2 */
6713         uint32_t ethype_2       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6714
6715         /* User_Ethertype_3 */
6716         uint32_t ethype_3       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6717 }
6718 __PACKING_ATTRIBUTE_STRUCT_END__
6719 IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3 ;
6720 #endif
6721
6722 /*****************************************************************************************/
6723 /* User_Ethertype_Configuration                                                          */
6724 /* Configure protocol and enables user Ethertype                                         */
6725 /*****************************************************************************************/
6726
6727 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_RESET_VALUE             ( 0x0 )
6728 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_RESET_VALUE_RESET_VALUE ( 0x0 )
6729 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_RESET_VALUE             ( 0x0 )
6730 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_RESET_VALUE_RESET_VALUE ( 0x0 )
6731 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_RESET_VALUE             ( 0x0 )
6732 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_RESET_VALUE_RESET_VALUE ( 0x0 )
6733 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_RESET_VALUE             ( 0x0 )
6734 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_RESET_VALUE_RESET_VALUE ( 0x0 )
6735 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RSV_RESET_VALUE                               ( 0x0 )
6736 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_RSV_RESET_VALUE_RESET_VALUE                   ( 0x0 )
6737 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_RESET_VALUE                   ( 0x0 )
6738 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_RESET_VALUE_RESET_VALUE       ( 0x0 )
6739 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_RESER_VALUE               ( 0x0 )
6740 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_RESER_VALUE_RESET_VALUE   ( 0x0 )
6741 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_RESER_VALUE               ( 0x0 )
6742 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_RESER_VALUE_RESET_VALUE   ( 0x0 )
6743 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_RESER_VALUE               ( 0x0 )
6744 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_RESER_VALUE_RESET_VALUE   ( 0x0 )
6745 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_RESER_VALUE               ( 0x0 )
6746 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_RESER_VALUE_RESET_VALUE   ( 0x0 )
6747
6748
6749 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_OFFSET ( 0x00000024 )
6750
6751 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ADDRESS           ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_OFFSET )
6752 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_READ( r )         READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ADDRESS ), (r) )
6753 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_WRITE( v )        WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG_ADDRESS ), (v) )
6754
6755 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6756 typedef struct
6757 {
6758         /* User_Ethertype_2_L3_Offset */
6759         uint32_t ethtype_user_offset_3  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6760
6761         /* User_Ethertype_2_L3_Offset */
6762         uint32_t ethtype_user_offset_2  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6763
6764         /* User_Ethertype_1_L3_Offset */
6765         uint32_t ethtype_user_offset_1  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6766
6767         /* User_Ethertype_0_L3_Offset */
6768         uint32_t ethtype_user_offset_0  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6769
6770         /* RSV */
6771         uint32_t rsv                    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6772
6773         /* User_Ethertype_Enable */
6774         uint32_t ethtype_user_en        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6775
6776         /* User_Ethertype_3 */
6777         uint32_t ethtype_user_prot_3    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6778
6779         /* User_Ethertype_2 */
6780         uint32_t ethtype_user_prot_2    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6781
6782         /* User_Ethertype_1 */
6783         uint32_t ethtype_user_prot_1    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6784
6785         /* User_Ethertype_0_protocol */
6786         uint32_t ethtype_user_prot_0    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6787 }
6788 __PACKING_ATTRIBUTE_STRUCT_END__
6789 IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG ;
6790 #else
6791 typedef struct
6792 {
6793         /* User_Ethertype_0_protocol */
6794         uint32_t ethtype_user_prot_0    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6795
6796         /* User_Ethertype_1 */
6797         uint32_t ethtype_user_prot_1    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6798
6799         /* User_Ethertype_2 */
6800         uint32_t ethtype_user_prot_2    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6801
6802         /* User_Ethertype_3 */
6803         uint32_t ethtype_user_prot_3    : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6804
6805         /* User_Ethertype_Enable */
6806         uint32_t ethtype_user_en        : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6807
6808         /* RSV */
6809         uint32_t rsv                    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6810
6811         /* User_Ethertype_0_L3_Offset */
6812         uint32_t ethtype_user_offset_0  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6813
6814         /* User_Ethertype_1_L3_Offset */
6815         uint32_t ethtype_user_offset_1  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6816
6817         /* User_Ethertype_2_L3_Offset */
6818         uint32_t ethtype_user_offset_2  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6819
6820         /* User_Ethertype_2_L3_Offset */
6821         uint32_t ethtype_user_offset_3  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6822 }
6823 __PACKING_ATTRIBUTE_STRUCT_END__
6824 IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG ;
6825 #endif
6826
6827 /*****************************************************************************************/
6828 /* VID_Configuration_0_1                                                                 */
6829 /* Config VID Filter 0 & 1                                                               */
6830 /*****************************************************************************************/
6831
6832 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_RESET_VALUE               ( 0x0 )
6833 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
6834 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_EN_ENABLE_VALUE              ( 0x1 )
6835 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_1_RESET_VALUE             ( 0x0 )
6836 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
6837 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_RESET_VALUE                  ( 0x0 )
6838 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_1_RESET_VALUE_RESET_VALUE      ( 0x0 )
6839 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_RESET_VALUE               ( 0x0 )
6840 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
6841 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_EN_ENABLE_VALUE              ( 0x1 )
6842 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_0_RESET_VALUE             ( 0x0 )
6843 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
6844 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_RESET_VALUE                  ( 0x0 )
6845 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_VID_0_RESET_VALUE_RESET_VALUE      ( 0x0 )
6846
6847
6848 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_OFFSET ( 0x00000028 )
6849
6850 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_ADDRESS       ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_OFFSET )
6851 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_READ( r )     READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_ADDRESS ), (r) )
6852 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_WRITE( v )    WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1_ADDRESS ), (v) )
6853
6854 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6855 typedef struct
6856 {
6857         /* VID_1_Enable */
6858         uint32_t vid_1_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6859
6860         /* Reserved */
6861         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6862
6863         /* VID_1 */
6864         uint32_t vid_1          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6865
6866         /* VID_0_Enable */
6867         uint32_t vid_0_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6868
6869         /* Reserved */
6870         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6871
6872         /* VID_0 */
6873         uint32_t vid_0          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6874 }
6875 __PACKING_ATTRIBUTE_STRUCT_END__
6876 IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1 ;
6877 #else
6878 typedef struct
6879 {
6880         /* VID_0 */
6881         uint32_t vid_0          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6882
6883         /* Reserved */
6884         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6885
6886         /* VID_0_Enable */
6887         uint32_t vid_0_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6888
6889         /* VID_1 */
6890         uint32_t vid_1          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6891
6892         /* Reserved */
6893         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6894
6895         /* VID_1_Enable */
6896         uint32_t vid_1_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6897 }
6898 __PACKING_ATTRIBUTE_STRUCT_END__
6899 IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1 ;
6900 #endif
6901
6902 /*****************************************************************************************/
6903 /* VID_Configuration_2_3                                                                 */
6904 /* Config VID Filter 2 & 3                                                               */
6905 /*****************************************************************************************/
6906
6907 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_RESET_VALUE               ( 0x0 )
6908 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
6909 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_EN_ENABLE_VALUE              ( 0x1 )
6910 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_1_RESET_VALUE             ( 0x0 )
6911 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
6912 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_RESET_VALUE                  ( 0x0 )
6913 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_3_RESET_VALUE_RESET_VALUE      ( 0x0 )
6914 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_RESET_VALUE               ( 0x0 )
6915 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
6916 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_EN_ENABLE_VALUE              ( 0x1 )
6917 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_0_RESET_VALUE             ( 0x0 )
6918 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
6919 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_RESET_VALUE                  ( 0x0 )
6920 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_VID_2_RESET_VALUE_RESET_VALUE      ( 0x0 )
6921
6922
6923 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_OFFSET ( 0x0000002C )
6924
6925 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_ADDRESS       ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_OFFSET )
6926 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_READ( r )     READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_ADDRESS ), (r) )
6927 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_WRITE( v )    WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3_ADDRESS ), (v) )
6928
6929 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
6930 typedef struct
6931 {
6932         /* VID_3_Enable */
6933         uint32_t vid_3_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6934
6935         /* Reserved */
6936         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6937
6938         /* VID_3 */
6939         uint32_t vid_3          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6940
6941         /* VID_2_Enable */
6942         uint32_t vid_2_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6943
6944         /* Reserved */
6945         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6946
6947         /* VID_2 */
6948         uint32_t vid_2          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6949 }
6950 __PACKING_ATTRIBUTE_STRUCT_END__
6951 IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3 ;
6952 #else
6953 typedef struct
6954 {
6955         /* VID_2 */
6956         uint32_t vid_2          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6957
6958         /* Reserved */
6959         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6960
6961         /* VID_2_Enable */
6962         uint32_t vid_2_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6963
6964         /* VID_3 */
6965         uint32_t vid_3          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6966
6967         /* Reserved */
6968         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6969
6970         /* VID_3_Enable */
6971         uint32_t vid_3_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
6972 }
6973 __PACKING_ATTRIBUTE_STRUCT_END__
6974 IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3 ;
6975 #endif
6976
6977 /*****************************************************************************************/
6978 /* VID_Configuration_4_5                                                                 */
6979 /* Config VID Filter 4 & 5                                                               */
6980 /*****************************************************************************************/
6981
6982 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_RESET_VALUE               ( 0x0 )
6983 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
6984 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_EN_ENABLE_VALUE              ( 0x1 )
6985 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_1_RESET_VALUE             ( 0x0 )
6986 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
6987 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_RESET_VALUE                  ( 0x0 )
6988 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_5_RESET_VALUE_RESET_VALUE      ( 0x0 )
6989 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_RESET_VALUE               ( 0x0 )
6990 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
6991 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_EN_ENABLE_VALUE              ( 0x1 )
6992 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_0_RESET_VALUE             ( 0x0 )
6993 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
6994 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_RESET_VALUE                  ( 0x0 )
6995 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_VID_4_RESET_VALUE_RESET_VALUE      ( 0x0 )
6996
6997
6998 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_OFFSET ( 0x00000030 )
6999
7000 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_ADDRESS       ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_OFFSET )
7001 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_READ( r )     READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_ADDRESS ), (r) )
7002 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_WRITE( v )    WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5_ADDRESS ), (v) )
7003
7004 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7005 typedef struct
7006 {
7007         /* VID_5_Enable */
7008         uint32_t vid_5_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7009
7010         /* Reserved */
7011         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7012
7013         /* VID_5 */
7014         uint32_t vid_5          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7015
7016         /* VID_4_Enable */
7017         uint32_t vid_4_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7018
7019         /* Reserved */
7020         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7021
7022         /* VID_4 */
7023         uint32_t vid_4          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7024 }
7025 __PACKING_ATTRIBUTE_STRUCT_END__
7026 IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5 ;
7027 #else
7028 typedef struct
7029 {
7030         /* VID_4 */
7031         uint32_t vid_4          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7032
7033         /* Reserved */
7034         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7035
7036         /* VID_4_Enable */
7037         uint32_t vid_4_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7038
7039         /* VID_5 */
7040         uint32_t vid_5          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7041
7042         /* Reserved */
7043         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7044
7045         /* VID_5_Enable */
7046         uint32_t vid_5_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7047 }
7048 __PACKING_ATTRIBUTE_STRUCT_END__
7049 IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5 ;
7050 #endif
7051
7052 /*****************************************************************************************/
7053 /* VID_Configuration_6_7                                                                 */
7054 /* Config VID Filter 6 & 7                                                               */
7055 /*****************************************************************************************/
7056
7057 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_RESET_VALUE               ( 0x0 )
7058 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
7059 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_EN_ENABLE_VALUE              ( 0x1 )
7060 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_1_RESET_VALUE             ( 0x0 )
7061 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
7062 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_RESET_VALUE                  ( 0x0 )
7063 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_7_RESET_VALUE_RESET_VALUE      ( 0x0 )
7064 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_RESET_VALUE               ( 0x0 )
7065 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
7066 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_EN_ENABLE_VALUE              ( 0x1 )
7067 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_0_RESET_VALUE             ( 0x0 )
7068 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
7069 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_RESET_VALUE                  ( 0x0 )
7070 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_VID_6_RESET_VALUE_RESET_VALUE      ( 0x0 )
7071
7072
7073 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_OFFSET ( 0x00000034 )
7074
7075 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_ADDRESS       ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_OFFSET )
7076 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_READ( r )     READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_ADDRESS ), (r) )
7077 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_WRITE( v )    WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7_ADDRESS ), (v) )
7078
7079 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7080 typedef struct
7081 {
7082         /* VID_7_Enable */
7083         uint32_t vid_7_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7084
7085         /* Reserved */
7086         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7087
7088         /* VID_7 */
7089         uint32_t vid_7          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7090
7091         /* VID_6_Enable */
7092         uint32_t vid_6_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7093
7094         /* Reserved */
7095         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7096
7097         /* VID_6 */
7098         uint32_t vid_6          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7099 }
7100 __PACKING_ATTRIBUTE_STRUCT_END__
7101 IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7 ;
7102 #else
7103 typedef struct
7104 {
7105         /* VID_6 */
7106         uint32_t vid_6          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7107
7108         /* Reserved */
7109         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7110
7111         /* VID_6_Enable */
7112         uint32_t vid_6_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7113
7114         /* VID_7 */
7115         uint32_t vid_7          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7116
7117         /* Reserved */
7118         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7119
7120         /* VID_7_Enable */
7121         uint32_t vid_7_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7122 }
7123 __PACKING_ATTRIBUTE_STRUCT_END__
7124 IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7 ;
7125 #endif
7126
7127 /*****************************************************************************************/
7128 /* VID_Configuration_8_9                                                                 */
7129 /* Config VID Filter 8 & 9                                                               */
7130 /*****************************************************************************************/
7131
7132 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_EN_RESET_VALUE               ( 0x0 )
7133 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
7134 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_EN_ENABLE_VALUE              ( 0x1 )
7135 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_1_RESET_VALUE             ( 0x0 )
7136 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
7137 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_RESET_VALUE                  ( 0x0 )
7138 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_9_RESET_VALUE_RESET_VALUE      ( 0x0 )
7139 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_EN_RESET_VALUE               ( 0x0 )
7140 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_EN_RESET_VALUE_RESET_VALUE   ( 0x0 )
7141 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_EN_ENABLE_VALUE              ( 0x1 )
7142 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_0_RESET_VALUE             ( 0x0 )
7143 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
7144 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_RESET_VALUE                  ( 0x0 )
7145 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_VID_8_RESET_VALUE_RESET_VALUE      ( 0x0 )
7146
7147
7148 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_OFFSET ( 0x00000038 )
7149
7150 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_ADDRESS       ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_OFFSET )
7151 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_READ( r )     READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_ADDRESS ), (r) )
7152 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_WRITE( v )    WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9_ADDRESS ), (v) )
7153
7154 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7155 typedef struct
7156 {
7157         /* VID_9_Enable */
7158         uint32_t vid_9_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7159
7160         /* Reserved */
7161         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7162
7163         /* VID_9 */
7164         uint32_t vid_9          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7165
7166         /* VID_8_Enable */
7167         uint32_t vid_8_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7168
7169         /* Reserved */
7170         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7171
7172         /* VID_8 */
7173         uint32_t vid_8          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7174 }
7175 __PACKING_ATTRIBUTE_STRUCT_END__
7176 IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9 ;
7177 #else
7178 typedef struct
7179 {
7180         /* VID_8 */
7181         uint32_t vid_8          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7182
7183         /* Reserved */
7184         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7185
7186         /* VID_8_Enable */
7187         uint32_t vid_8_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7188
7189         /* VID_9 */
7190         uint32_t vid_9          : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7191
7192         /* Reserved */
7193         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7194
7195         /* VID_9_Enable */
7196         uint32_t vid_9_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7197 }
7198 __PACKING_ATTRIBUTE_STRUCT_END__
7199 IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9 ;
7200 #endif
7201
7202 /*****************************************************************************************/
7203 /* VID_Configuration_10_11                                                               */
7204 /* Config VID Filter 10 & 11                                                             */
7205 /*****************************************************************************************/
7206
7207 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_EN_RESET_VALUE              ( 0x0 )
7208 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_EN_RESET_VALUE_RESET_VALUE  ( 0x0 )
7209 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_EN_ENABLE_VALUE             ( 0x1 )
7210 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_1_RESET_VALUE             ( 0x0 )
7211 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_1_RESET_VALUE_RESET_VALUE ( 0x0 )
7212 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_RESET_VALUE                 ( 0x0 )
7213 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_11_RESET_VALUE_RESET_VALUE     ( 0x0 )
7214 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_EN_RESET_VALUE              ( 0x0 )
7215 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_EN_RESET_VALUE_RESET_VALUE  ( 0x0 )
7216 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_EN_ENABLE_VALUE             ( 0x1 )
7217 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_0_RESET_VALUE             ( 0x0 )
7218 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_RESERVED_0_RESET_VALUE_RESET_VALUE ( 0x0 )
7219 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_RESET_VALUE                 ( 0x0 )
7220 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_VID_10_RESET_VALUE_RESET_VALUE     ( 0x0 )
7221
7222
7223 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_OFFSET ( 0x0000003C )
7224
7225 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_ADDRESS     ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_OFFSET )
7226 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_READ( r )   READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_ADDRESS ), (r) )
7227 #define IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_WRITE( v )  WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11_ADDRESS ), (v) )
7228
7229 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7230 typedef struct
7231 {
7232         /* VID_11_Enable */
7233         uint32_t vid_11_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7234
7235         /* Reserved */
7236         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7237
7238         /* VID_11 */
7239         uint32_t vid_11         : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7240
7241         /* VID_10_Enable */
7242         uint32_t vid_10_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7243
7244         /* Reserved */
7245         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7246
7247         /* VID_10 */
7248         uint32_t vid_10         : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7249 }
7250 __PACKING_ATTRIBUTE_STRUCT_END__
7251 IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11 ;
7252 #else
7253 typedef struct
7254 {
7255         /* VID_10 */
7256         uint32_t vid_10         : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7257
7258         /* Reserved */
7259         uint32_t reserved_0     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7260
7261         /* VID_10_Enable */
7262         uint32_t vid_10_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7263
7264         /* VID_11 */
7265         uint32_t vid_11         : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7266
7267         /* Reserved */
7268         uint32_t reserved_1     : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7269
7270         /* VID_11_Enable */
7271         uint32_t vid_11_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7272 }
7273 __PACKING_ATTRIBUTE_STRUCT_END__
7274 IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11 ;
7275 #endif
7276
7277 /*****************************************************************************************/
7278 /* User_defined_IP_Protocl                                                               */
7279 /* IP Protocols to be matched to IP Protocol field and to be indicated in the output sum */
7280 /* mary word                                                                             */
7281 /*****************************************************************************************/
7282
7283 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_RESET_VALUE             ( 0x0 )
7284 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_3_RESET_VALUE_RESET_VALUE ( 0x0 )
7285 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_RESET_VALUE             ( 0x0 )
7286 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_2_RESET_VALUE_RESET_VALUE ( 0x0 )
7287 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_RESET_VALUE             ( 0x0 )
7288 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_1_RESET_VALUE_RESET_VALUE ( 0x0 )
7289 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_RESET_VALUE             ( 0x0 )
7290 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_USER_IP_PROT_0_RESET_VALUE_RESET_VALUE ( 0x0 )
7291
7292
7293 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_OFFSET ( 0x00000040 )
7294
7295 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_ADDRESS          ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_OFFSET )
7296 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_READ( r )        READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_ADDRESS ), (r) )
7297 #define IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_WRITE( v )       WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT_ADDRESS ), (v) )
7298
7299 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7300 typedef struct
7301 {
7302         /* USER__IP_protocol_3 */
7303         uint32_t user_ip_prot_3 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7304
7305         /* USER_IP_protocol_2 */
7306         uint32_t user_ip_prot_2 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7307
7308         /* USER_IP_protocol_1 */
7309         uint32_t user_ip_prot_1 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7310
7311         /* USER_IP_protocol_0 */
7312         uint32_t user_ip_prot_0 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7313 }
7314 __PACKING_ATTRIBUTE_STRUCT_END__
7315 IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT ;
7316 #else
7317 typedef struct
7318 {
7319         /* USER_IP_protocol_0 */
7320         uint32_t user_ip_prot_0 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7321
7322         /* USER_IP_protocol_1 */
7323         uint32_t user_ip_prot_1 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7324
7325         /* USER_IP_protocol_2 */
7326         uint32_t user_ip_prot_2 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7327
7328         /* USER__IP_protocol_3 */
7329         uint32_t user_ip_prot_3 : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7330 }
7331 __PACKING_ATTRIBUTE_STRUCT_END__
7332 IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT ;
7333 #endif
7334
7335 /*****************************************************************************************/
7336 /* PPP_IP_Protocol_Code                                                                  */
7337 /* PPP Protocol Code to indicate L3 is IP                                                */
7338 /*****************************************************************************************/
7339
7340 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_RESET_VALUE             ( 0x0 )
7341 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_1_RESET_VALUE_RESET_VALUE ( 0x0 )
7342 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_RESET_VALUE             ( 0x0 )
7343 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_PPP_CODE_0_RESET_VALUE_RESET_VALUE ( 0x0 )
7344
7345
7346 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_OFFSET ( 0x00000044 )
7347
7348 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_OFFSET )
7349 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_ADDRESS ), (r) )
7350 #define IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE_ADDRESS ), (v) )
7351
7352 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7353 typedef struct
7354 {
7355         /* PPP_Protocol_Code_1 */
7356         uint32_t ppp_code_1     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7357
7358         /* PPP_Protocol_Code_0 */
7359         uint32_t ppp_code_0     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7360 }
7361 __PACKING_ATTRIBUTE_STRUCT_END__
7362 IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE ;
7363 #else
7364 typedef struct
7365 {
7366         /* PPP_Protocol_Code_0 */
7367         uint32_t ppp_code_0     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7368
7369         /* PPP_Protocol_Code_1 */
7370         uint32_t ppp_code_1     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7371 }
7372 __PACKING_ATTRIBUTE_STRUCT_END__
7373 IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE ;
7374 #endif
7375
7376 /*****************************************************************************************/
7377 /* IP_FILTER0_CFG                                                                        */
7378 /* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
7379 /* LTERS_CFG[4]                                                                          */
7380 /*****************************************************************************************/
7381
7382 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
7383 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7384
7385
7386 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_OFFSET ( 0x00000048 )
7387
7388 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_OFFSET )
7389 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_ADDRESS ), (r) )
7390 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG_ADDRESS ), (v) )
7391
7392 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7393 typedef struct
7394 {
7395         /* IP_address */
7396         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7397 }
7398 __PACKING_ATTRIBUTE_STRUCT_END__
7399 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG ;
7400 #else
7401 typedef struct
7402 {
7403         /* IP_address */
7404         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7405 }
7406 __PACKING_ATTRIBUTE_STRUCT_END__
7407 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG ;
7408 #endif
7409
7410 /*****************************************************************************************/
7411 /* IP_FILTER1_CFG                                                                        */
7412 /* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
7413 /* LTERS_CFG[5]                                                                          */
7414 /*****************************************************************************************/
7415
7416 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
7417 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7418
7419
7420 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_OFFSET ( 0x0000004C )
7421
7422 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_OFFSET )
7423 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_ADDRESS ), (r) )
7424 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG_ADDRESS ), (v) )
7425
7426 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7427 typedef struct
7428 {
7429         /* IP_address */
7430         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7431 }
7432 __PACKING_ATTRIBUTE_STRUCT_END__
7433 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG ;
7434 #else
7435 typedef struct
7436 {
7437         /* IP_address */
7438         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7439 }
7440 __PACKING_ATTRIBUTE_STRUCT_END__
7441 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG ;
7442 #endif
7443
7444 /*****************************************************************************************/
7445 /* IP_FILTER2_CFG                                                                        */
7446 /* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
7447 /* LTERS_CFG[6]                                                                          */
7448 /*****************************************************************************************/
7449
7450 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
7451 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7452
7453
7454 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_OFFSET ( 0x00000050 )
7455
7456 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_OFFSET )
7457 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_ADDRESS ), (r) )
7458 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG_ADDRESS ), (v) )
7459
7460 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7461 typedef struct
7462 {
7463         /* IP_address */
7464         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7465 }
7466 __PACKING_ATTRIBUTE_STRUCT_END__
7467 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG ;
7468 #else
7469 typedef struct
7470 {
7471         /* IP_address */
7472         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7473 }
7474 __PACKING_ATTRIBUTE_STRUCT_END__
7475 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG ;
7476 #endif
7477
7478 /*****************************************************************************************/
7479 /* IP_FILTER3_CFG                                                                        */
7480 /* Config the IP Address filtering.   Notice that the enable bit is located in the IP_FI */
7481 /* LTERS_CFG[7]                                                                          */
7482 /*****************************************************************************************/
7483
7484 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE             ( 0x0 )
7485 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_IP_ADDRESS_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7486
7487
7488 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_OFFSET ( 0x00000054 )
7489
7490 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_OFFSET )
7491 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_ADDRESS ), (r) )
7492 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG_ADDRESS ), (v) )
7493
7494 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7495 typedef struct
7496 {
7497         /* IP_address */
7498         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7499 }
7500 __PACKING_ATTRIBUTE_STRUCT_END__
7501 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG ;
7502 #else
7503 typedef struct
7504 {
7505         /* IP_address */
7506         uint32_t ip_address     : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7507 }
7508 __PACKING_ATTRIBUTE_STRUCT_END__
7509 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG ;
7510 #endif
7511
7512 /*****************************************************************************************/
7513 /* DA_FILT1_VAL_L                                                                        */
7514 /* Config DA filter1 31:0                                                                */
7515 /*****************************************************************************************/
7516
7517 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
7518 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7519
7520
7521 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_OFFSET ( 0x00000058 )
7522
7523 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_OFFSET )
7524 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_ADDRESS ), (r) )
7525 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L_ADDRESS ), (v) )
7526
7527 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7528 typedef struct
7529 {
7530         /* DA_FILT_LSB */
7531         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7532 }
7533 __PACKING_ATTRIBUTE_STRUCT_END__
7534 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L ;
7535 #else
7536 typedef struct
7537 {
7538         /* DA_FILT_LSB */
7539         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7540 }
7541 __PACKING_ATTRIBUTE_STRUCT_END__
7542 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L ;
7543 #endif
7544
7545 /*****************************************************************************************/
7546 /* DA_FILT1_MASK_L                                                                       */
7547 /* Config DA Filter1 mask 31:0                                                           */
7548 /*****************************************************************************************/
7549
7550 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE             ( 0x0 )
7551 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_DA_FILT0_MASK_L_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7552
7553
7554 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_OFFSET ( 0x0000005C )
7555
7556 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_ADDRESS       ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_OFFSET )
7557 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_READ( r )     READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_ADDRESS ), (r) )
7558 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_WRITE( v )    WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L_ADDRESS ), (v) )
7559
7560 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7561 typedef struct
7562 {
7563         /* DA_FILT_MASK_L */
7564         uint32_t da_filt0_mask_l        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7565 }
7566 __PACKING_ATTRIBUTE_STRUCT_END__
7567 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L ;
7568 #else
7569 typedef struct
7570 {
7571         /* DA_FILT_MASK_L */
7572         uint32_t da_filt0_mask_l        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7573 }
7574 __PACKING_ATTRIBUTE_STRUCT_END__
7575 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L ;
7576 #endif
7577
7578 /*****************************************************************************************/
7579 /* DA_FILT1_CFG_H                                                                        */
7580 /* DA Filter1 Value & Mask highest bits 15:0                                             */
7581 /*****************************************************************************************/
7582
7583 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
7584 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_MASK_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7585 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE              ( 0x0 )
7586 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_DA_FILT_VAL_MSB_FILTER_CONFIG_VALUE_RESET_VALUE  ( 0x0 )
7587
7588
7589 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_OFFSET ( 0x00000060 )
7590
7591 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_OFFSET )
7592 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_ADDRESS ), (r) )
7593 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H_ADDRESS ), (v) )
7594
7595 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7596 typedef struct
7597 {
7598         /* DA_FILT_MASK_MSB */
7599         uint32_t da_filt_mask_msb       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7600
7601         /* DA_FILT_VAL_MSB */
7602         uint32_t da_filt_val_msb        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7603 }
7604 __PACKING_ATTRIBUTE_STRUCT_END__
7605 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H ;
7606 #else
7607 typedef struct
7608 {
7609         /* DA_FILT_VAL_MSB */
7610         uint32_t da_filt_val_msb        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7611
7612         /* DA_FILT_MASK_MSB */
7613         uint32_t da_filt_mask_msb       : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7614 }
7615 __PACKING_ATTRIBUTE_STRUCT_END__
7616 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H ;
7617 #endif
7618
7619 /*****************************************************************************************/
7620 /* DA_FILT2_VAL_L                                                                        */
7621 /* Config DA filter2 31:0                                                                */
7622 /*****************************************************************************************/
7623
7624 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
7625 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7626
7627
7628 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_OFFSET ( 0x00000064 )
7629
7630 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_OFFSET )
7631 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_ADDRESS ), (r) )
7632 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L_ADDRESS ), (v) )
7633
7634 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7635 typedef struct
7636 {
7637         /* DA_FILT_LSB */
7638         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7639 }
7640 __PACKING_ATTRIBUTE_STRUCT_END__
7641 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L ;
7642 #else
7643 typedef struct
7644 {
7645         /* DA_FILT_LSB */
7646         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7647 }
7648 __PACKING_ATTRIBUTE_STRUCT_END__
7649 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L ;
7650 #endif
7651
7652 /*****************************************************************************************/
7653 /* DA_FILT2_VAL_H                                                                        */
7654 /* Config DA filter2 47:32                                                               */
7655 /*****************************************************************************************/
7656
7657 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
7658 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
7659 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
7660 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7661
7662
7663 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_OFFSET ( 0x00000068 )
7664
7665 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_OFFSET )
7666 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_ADDRESS ), (r) )
7667 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H_ADDRESS ), (v) )
7668
7669 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7670 typedef struct
7671 {
7672         /* rsv */
7673         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7674
7675         /* DA_FILT_MSB */
7676         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7677 }
7678 __PACKING_ATTRIBUTE_STRUCT_END__
7679 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H ;
7680 #else
7681 typedef struct
7682 {
7683         /* DA_FILT_MSB */
7684         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7685
7686         /* rsv */
7687         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7688 }
7689 __PACKING_ATTRIBUTE_STRUCT_END__
7690 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H ;
7691 #endif
7692
7693 /*****************************************************************************************/
7694 /* DA_FILT3_VAL_L                                                                        */
7695 /* Config DA filter3 31:0                                                                */
7696 /*****************************************************************************************/
7697
7698 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
7699 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7700
7701
7702 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_OFFSET ( 0x0000006C )
7703
7704 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_OFFSET )
7705 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_ADDRESS ), (r) )
7706 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L_ADDRESS ), (v) )
7707
7708 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7709 typedef struct
7710 {
7711         /* DA_FILT_LSB */
7712         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7713 }
7714 __PACKING_ATTRIBUTE_STRUCT_END__
7715 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L ;
7716 #else
7717 typedef struct
7718 {
7719         /* DA_FILT_LSB */
7720         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7721 }
7722 __PACKING_ATTRIBUTE_STRUCT_END__
7723 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L ;
7724 #endif
7725
7726 /*****************************************************************************************/
7727 /* DA_FILT3_VAL_H                                                                        */
7728 /* Config DA filter3 47:32                                                               */
7729 /*****************************************************************************************/
7730
7731 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
7732 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
7733 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
7734 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7735
7736
7737 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_OFFSET ( 0x00000070 )
7738
7739 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_OFFSET )
7740 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_ADDRESS ), (r) )
7741 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H_ADDRESS ), (v) )
7742
7743 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7744 typedef struct
7745 {
7746         /* rsv */
7747         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7748
7749         /* DA_FILT_MSB */
7750         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7751 }
7752 __PACKING_ATTRIBUTE_STRUCT_END__
7753 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H ;
7754 #else
7755 typedef struct
7756 {
7757         /* DA_FILT_MSB */
7758         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7759
7760         /* rsv */
7761         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7762 }
7763 __PACKING_ATTRIBUTE_STRUCT_END__
7764 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H ;
7765 #endif
7766
7767 /*****************************************************************************************/
7768 /* DA_FILT4_VAL_L                                                                        */
7769 /* Config DA filter4 31:0                                                                */
7770 /*****************************************************************************************/
7771
7772 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
7773 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7774
7775
7776 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_OFFSET ( 0x00000074 )
7777
7778 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_OFFSET )
7779 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_ADDRESS ), (r) )
7780 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L_ADDRESS ), (v) )
7781
7782 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7783 typedef struct
7784 {
7785         /* DA_FILT_LSB */
7786         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7787 }
7788 __PACKING_ATTRIBUTE_STRUCT_END__
7789 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L ;
7790 #else
7791 typedef struct
7792 {
7793         /* DA_FILT_LSB */
7794         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7795 }
7796 __PACKING_ATTRIBUTE_STRUCT_END__
7797 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L ;
7798 #endif
7799
7800 /*****************************************************************************************/
7801 /* DA_FILT4_VAL_H                                                                        */
7802 /* Config DA Filter4 47:32                                                               */
7803 /*****************************************************************************************/
7804
7805 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
7806 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
7807 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
7808 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7809
7810
7811 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_OFFSET ( 0x00000078 )
7812
7813 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_OFFSET )
7814 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_ADDRESS ), (r) )
7815 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H_ADDRESS ), (v) )
7816
7817 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7818 typedef struct
7819 {
7820         /* rsv */
7821         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7822
7823         /* DA_FILT_MSB */
7824         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7825 }
7826 __PACKING_ATTRIBUTE_STRUCT_END__
7827 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H ;
7828 #else
7829 typedef struct
7830 {
7831         /* DA_FILT_MSB */
7832         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7833
7834         /* rsv */
7835         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7836 }
7837 __PACKING_ATTRIBUTE_STRUCT_END__
7838 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H ;
7839 #endif
7840
7841 /*****************************************************************************************/
7842 /* DA_FILT5_VAL_L                                                                        */
7843 /* Config DA filter5 31:0                                                                */
7844 /*****************************************************************************************/
7845
7846 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
7847 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7848
7849
7850 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_OFFSET ( 0x0000007C )
7851
7852 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_OFFSET )
7853 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_ADDRESS ), (r) )
7854 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L_ADDRESS ), (v) )
7855
7856 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7857 typedef struct
7858 {
7859         /* DA_FILT_LSB */
7860         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7861 }
7862 __PACKING_ATTRIBUTE_STRUCT_END__
7863 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L ;
7864 #else
7865 typedef struct
7866 {
7867         /* DA_FILT_LSB */
7868         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7869 }
7870 __PACKING_ATTRIBUTE_STRUCT_END__
7871 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L ;
7872 #endif
7873
7874 /*****************************************************************************************/
7875 /* DA_FILT5_VAL_H                                                                        */
7876 /* Config DA Filter5 47:32                                                               */
7877 /*****************************************************************************************/
7878
7879 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
7880 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
7881 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
7882 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
7883
7884
7885 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_OFFSET ( 0x00000080 )
7886
7887 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_OFFSET )
7888 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_ADDRESS ), (r) )
7889 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H_ADDRESS ), (v) )
7890
7891 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7892 typedef struct
7893 {
7894         /* rsv */
7895         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7896
7897         /* DA_FILT_MSB */
7898         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7899 }
7900 __PACKING_ATTRIBUTE_STRUCT_END__
7901 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H ;
7902 #else
7903 typedef struct
7904 {
7905         /* DA_FILT_MSB */
7906         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7907
7908         /* rsv */
7909         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7910 }
7911 __PACKING_ATTRIBUTE_STRUCT_END__
7912 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H ;
7913 #endif
7914
7915 /*****************************************************************************************/
7916 /* DA_FILT_VALID_CFG                                                                     */
7917 /* Valid configuration of all DA filters: there is a dedicated bit per each DA filter th */
7918 /* at says if the current DA filter is valid or not. Used for on-the-fly DA filter value */
7919 /*  (mask) modifications, since the DA filter parameters are not assigned on single SW r */
7920 /* egister.                                                                              */
7921 /*****************************************************************************************/
7922
7923 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_RSV_FILTER_CONFIG_VALUE                    ( 0x0 )
7924 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_RSV_FILTER_CONFIG_VALUE_RESET_VALUE        ( 0x0 )
7925 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT7_VALID_NON_VALID_VALUE             ( 0x0 )
7926 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT7_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7927 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT7_VALID_VALID_VALUE                 ( 0x1 )
7928 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT6_VALID_NON_VALID_VALUE             ( 0x0 )
7929 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT6_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7930 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT6_VALID_VALID_VALUE                 ( 0x1 )
7931 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT5_VALID_NON_VALID_VALUE             ( 0x0 )
7932 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT5_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7933 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT5_VALID_VALID_VALUE                 ( 0x1 )
7934 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT4_VALID_NON_VALID_VALUE             ( 0x0 )
7935 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT4_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7936 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT4_VALID_VALID_VALUE                 ( 0x1 )
7937 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT3_VALID_NON_VALID_VALUE             ( 0x0 )
7938 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT3_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7939 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT3_VALID_VALID_VALUE                 ( 0x1 )
7940 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT2_VALID_NON_VALID_VALUE             ( 0x0 )
7941 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT2_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7942 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT2_VALID_VALID_VALUE                 ( 0x1 )
7943 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT1_VALID_NON_VALID_VALUE             ( 0x0 )
7944 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT1_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7945 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT1_VALID_VALID_VALUE                 ( 0x1 )
7946 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT0_VALID_NON_VALID_VALUE             ( 0x0 )
7947 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT0_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
7948 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_DA_FILT0_VALID_VALID_VALUE                 ( 0x1 )
7949
7950
7951 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_OFFSET ( 0x00000084 )
7952
7953 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_ADDRESS     ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_OFFSET )
7954 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_READ( r )   READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_ADDRESS ), (r) )
7955 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_WRITE( v )  WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG_ADDRESS ), (v) )
7956
7957 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
7958 typedef struct
7959 {
7960         /* rsv */
7961         uint32_t rsv            : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7962
7963         /* DA_FILT7_VALID */
7964         uint32_t da_filt7_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7965
7966         /* DA_FILT6_VALID */
7967         uint32_t da_filt6_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7968
7969         /* DA_FILT5_VALID */
7970         uint32_t da_filt5_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7971
7972         /* DA_FILT4_VALID */
7973         uint32_t da_filt4_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7974
7975         /* DA_FILT3_VALID */
7976         uint32_t da_filt3_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7977
7978         /* DA_FILT2_VALID */
7979         uint32_t da_filt2_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7980
7981         /* DA_FILT1_VALID */
7982         uint32_t da_filt1_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7983
7984         /* DA_FILT0_VALID */
7985         uint32_t da_filt0_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7986 }
7987 __PACKING_ATTRIBUTE_STRUCT_END__
7988 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG ;
7989 #else
7990 typedef struct
7991 {
7992         /* DA_FILT0_VALID */
7993         uint32_t da_filt0_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7994
7995         /* DA_FILT1_VALID */
7996         uint32_t da_filt1_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
7997
7998         /* DA_FILT2_VALID */
7999         uint32_t da_filt2_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8000
8001         /* DA_FILT3_VALID */
8002         uint32_t da_filt3_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8003
8004         /* DA_FILT4_VALID */
8005         uint32_t da_filt4_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8006
8007         /* DA_FILT5_VALID */
8008         uint32_t da_filt5_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8009
8010         /* DA_FILT6_VALID */
8011         uint32_t da_filt6_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8012
8013         /* DA_FILT7_VALID */
8014         uint32_t da_filt7_valid : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8015
8016         /* rsv */
8017         uint32_t rsv            : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8018 }
8019 __PACKING_ATTRIBUTE_STRUCT_END__
8020 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG ;
8021 #endif
8022
8023 /*****************************************************************************************/
8024 /* IP_FILTER0_MASK_CFG                                                                   */
8025 /* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
8026 /* ERS_CFG[4]                                                                            */
8027 /*****************************************************************************************/
8028
8029 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
8030 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
8031
8032
8033 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_OFFSET ( 0x00000088 )
8034
8035 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_ADDRESS           ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_OFFSET )
8036 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_READ( r )         READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_ADDRESS ), (r) )
8037 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_WRITE( v )        WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG_ADDRESS ), (v) )
8038
8039 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8040 typedef struct
8041 {
8042         /* IP_address_mask */
8043         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8044 }
8045 __PACKING_ATTRIBUTE_STRUCT_END__
8046 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG ;
8047 #else
8048 typedef struct
8049 {
8050         /* IP_address_mask */
8051         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8052 }
8053 __PACKING_ATTRIBUTE_STRUCT_END__
8054 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG ;
8055 #endif
8056
8057 /*****************************************************************************************/
8058 /* IP_FILTER1_MASK_CFG                                                                   */
8059 /* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
8060 /* ERS_CFG[5]                                                                            */
8061 /*****************************************************************************************/
8062
8063 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
8064 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
8065
8066
8067 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_OFFSET ( 0x0000008C )
8068
8069 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_ADDRESS           ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_OFFSET )
8070 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_READ( r )         READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_ADDRESS ), (r) )
8071 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_WRITE( v )        WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG_ADDRESS ), (v) )
8072
8073 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8074 typedef struct
8075 {
8076         /* IP_address_mask */
8077         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8078 }
8079 __PACKING_ATTRIBUTE_STRUCT_END__
8080 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG ;
8081 #else
8082 typedef struct
8083 {
8084         /* IP_address_mask */
8085         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8086 }
8087 __PACKING_ATTRIBUTE_STRUCT_END__
8088 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG ;
8089 #endif
8090
8091 /*****************************************************************************************/
8092 /* IP_FILTER2_MASK_CFG                                                                   */
8093 /* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
8094 /* ERS_CFG[6]                                                                            */
8095 /*****************************************************************************************/
8096
8097 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
8098 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
8099
8100
8101 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_OFFSET ( 0x00000090 )
8102
8103 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_ADDRESS           ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_OFFSET )
8104 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_READ( r )         READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_ADDRESS ), (r) )
8105 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_WRITE( v )        WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG_ADDRESS ), (v) )
8106
8107 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8108 typedef struct
8109 {
8110         /* IP_address_mask */
8111         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8112 }
8113 __PACKING_ATTRIBUTE_STRUCT_END__
8114 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG ;
8115 #else
8116 typedef struct
8117 {
8118         /* IP_address_mask */
8119         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8120 }
8121 __PACKING_ATTRIBUTE_STRUCT_END__
8122 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG ;
8123 #endif
8124
8125 /*****************************************************************************************/
8126 /* IP_FILTER3_MASK_CFG                                                                   */
8127 /* Config the IP Address masking.   Notice that the enable bit is located in the IP_FILT */
8128 /* ERS_CFG[7]                                                                            */
8129 /*****************************************************************************************/
8130
8131 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE             ( 0x0 )
8132 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_IP_ADDRESS_MASK_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
8133
8134
8135 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_OFFSET ( 0x00000094 )
8136
8137 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_ADDRESS           ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_OFFSET )
8138 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_READ( r )         READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_ADDRESS ), (r) )
8139 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_WRITE( v )        WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG_ADDRESS ), (v) )
8140
8141 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8142 typedef struct
8143 {
8144         /* IP_address_mask */
8145         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8146 }
8147 __PACKING_ATTRIBUTE_STRUCT_END__
8148 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG ;
8149 #else
8150 typedef struct
8151 {
8152         /* IP_address_mask */
8153         uint32_t ip_address_mask        : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8154 }
8155 __PACKING_ATTRIBUTE_STRUCT_END__
8156 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG ;
8157 #endif
8158
8159 /*****************************************************************************************/
8160 /* IP_FILTERS_CFG                                                                        */
8161 /* IP Address Filters (0..3) configurations:    (1) SIP or DIP selection config per each */
8162 /*  filter  (1) Valid bit per each filter                                                */
8163 /*****************************************************************************************/
8164
8165 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RSV_NON_VALID_VALUE                          ( 0x0 )
8166 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RSV_NON_VALID_VALUE_RESET_VALUE              ( 0x0 )
8167 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_RSV_VALID_VALUE                              ( 0x1 )
8168 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_NON_VALID_VALUE             ( 0x0 )
8169 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
8170 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_VALID_VALID_VALUE                 ( 0x1 )
8171 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_NON_VALID_VALUE             ( 0x0 )
8172 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
8173 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_VALID_VALID_VALUE                 ( 0x1 )
8174 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_NON_VALID_VALUE             ( 0x0 )
8175 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
8176 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_VALID_VALID_VALUE                 ( 0x1 )
8177 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_NON_VALID_VALUE             ( 0x0 )
8178 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
8179 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_VALID_VALID_VALUE                 ( 0x1 )
8180 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_SIP_VALUE                  ( 0x0 )
8181 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
8182 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_DIP_VALUE                  ( 0x1 )
8183 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_SIP_VALUE                  ( 0x0 )
8184 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
8185 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_DIP_VALUE                  ( 0x1 )
8186 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_SIP_VALUE                  ( 0x0 )
8187 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
8188 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_DIP_VALUE                  ( 0x1 )
8189 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_SIP_VALUE                  ( 0x0 )
8190 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_SIP_VALUE_RESET_VALUE      ( 0x0 )
8191 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_DIP_VALUE                  ( 0x1 )
8192
8193
8194 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_OFFSET ( 0x00000098 )
8195
8196 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_OFFSET )
8197 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_ADDRESS ), (r) )
8198 #define IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG_ADDRESS ), (v) )
8199
8200 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8201 typedef struct
8202 {
8203         /* rsv */
8204         uint32_t rsv                    : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8205
8206         /* IP_FILTER3_VALID */
8207         uint32_t ip_filter3_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8208
8209         /* IP_FILTER2_VALID */
8210         uint32_t ip_filter2_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8211
8212         /* IP_FILTER1_VALID */
8213         uint32_t ip_filter1_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8214
8215         /* IP_FILTER0_VALID */
8216         uint32_t ip_filter0_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8217
8218         /* IP_FILTER3_DIP_EN */
8219         uint32_t ip_filter3_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8220
8221         /* IP_FILTER2_DIP_EN */
8222         uint32_t ip_filter2_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8223
8224         /* IP_FILTER1_DIP_EN */
8225         uint32_t ip_filter1_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8226
8227         /* IP_FILTER0_DIP_EN */
8228         uint32_t ip_filter0_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8229 }
8230 __PACKING_ATTRIBUTE_STRUCT_END__
8231 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG ;
8232 #else
8233 typedef struct
8234 {
8235         /* IP_FILTER0_DIP_EN */
8236         uint32_t ip_filter0_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8237
8238         /* IP_FILTER1_DIP_EN */
8239         uint32_t ip_filter1_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8240
8241         /* IP_FILTER2_DIP_EN */
8242         uint32_t ip_filter2_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8243
8244         /* IP_FILTER3_DIP_EN */
8245         uint32_t ip_filter3_dip_en      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8246
8247         /* IP_FILTER0_VALID */
8248         uint32_t ip_filter0_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8249
8250         /* IP_FILTER1_VALID */
8251         uint32_t ip_filter1_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8252
8253         /* IP_FILTER2_VALID */
8254         uint32_t ip_filter2_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8255
8256         /* IP_FILTER3_VALID */
8257         uint32_t ip_filter3_valid       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8258
8259         /* rsv */
8260         uint32_t rsv                    : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8261 }
8262 __PACKING_ATTRIBUTE_STRUCT_END__
8263 IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG ;
8264 #endif
8265
8266 /*****************************************************************************************/
8267 /* GRE_PROTOCOL_CFG                                                                      */
8268 /* GRE Protocol                                                                          */
8269 /*****************************************************************************************/
8270
8271 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RSV_NON_VALID_VALUE                     ( 0x0 )
8272 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RSV_NON_VALID_VALUE_RESET_VALUE         ( 0x0 )
8273 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_RSV_VALID_VALUE                         ( 0x1 )
8274 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_PROTOCOL_VALUE             ( 0x880B )
8275 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_GRE_PROTOCOL_PROTOCOL_VALUE_RESET_VALUE ( 0x880B )
8276
8277
8278 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_OFFSET ( 0x0000009C )
8279
8280 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_OFFSET )
8281 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_ADDRESS ), (r) )
8282 #define IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG_ADDRESS ), (v) )
8283
8284 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8285 typedef struct
8286 {
8287         /* rsv */
8288         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8289
8290         /* GRE_PROTOCOL */
8291         uint32_t gre_protocol   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8292 }
8293 __PACKING_ATTRIBUTE_STRUCT_END__
8294 IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG ;
8295 #else
8296 typedef struct
8297 {
8298         /* GRE_PROTOCOL */
8299         uint32_t gre_protocol   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8300
8301         /* rsv */
8302         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8303 }
8304 __PACKING_ATTRIBUTE_STRUCT_END__
8305 IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG ;
8306 #endif
8307
8308 /*****************************************************************************************/
8309 /* DSCP2TCI_TBL0_R0                                                                      */
8310 /* DSCP to TCI Conversion Table 0.  Register 0 that stores convetion code for the follow */
8311 /* ing DSCP values: 0x0..0x7.    Used for conversion in case of IP untagged packet    Th */
8312 /* e coding of each field is done in the following way:  TCI converted field should matc */
8313 /* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
8314 /* r_index*8+octet(or field) index                                                       */
8315 /*****************************************************************************************/
8316
8317 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV8_RSV_VALUE                ( 0x0 )
8318 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
8319 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O7_TCI_VALUE             ( 0x0 )
8320 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
8321 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV7_RSV_VALUE                ( 0x0 )
8322 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
8323 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O6_TCI_VALUE             ( 0x0 )
8324 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
8325 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV6_RSV_VALUE                ( 0x0 )
8326 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
8327 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O5_TCI_VALUE             ( 0x0 )
8328 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
8329 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV5_RSV_VALUE                ( 0x0 )
8330 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
8331 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O4_TCI_VALUE             ( 0x0 )
8332 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
8333 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV4_RSV_VALUE                ( 0x0 )
8334 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
8335 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O3_TCI_VALUE             ( 0x0 )
8336 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
8337 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV3_RSV_VALUE                ( 0x0 )
8338 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
8339 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O2_TCI_VALUE             ( 0x0 )
8340 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
8341 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV2_RSV_VALUE                ( 0x0 )
8342 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
8343 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O1_TCI_VALUE             ( 0x0 )
8344 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
8345 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV1_RSV_VALUE                ( 0x0 )
8346 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
8347 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O0_TCI_VALUE             ( 0x0 )
8348 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
8349
8350
8351 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_OFFSET ( 0x00000100 )
8352
8353 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_OFFSET )
8354 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_ADDRESS ), (r) )
8355 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0_ADDRESS ), (v) )
8356
8357 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8358 typedef struct
8359 {
8360         /* rsv8 */
8361         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8362
8363         /* DSCP_O7 */
8364         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8365
8366         /* rsv7 */
8367         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8368
8369         /* DSCP_O6 */
8370         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8371
8372         /* rsv6 */
8373         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8374
8375         /* DSCP_O5 */
8376         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8377
8378         /* rsv5 */
8379         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8380
8381         /* DSCP_O4 */
8382         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8383
8384         /* rsv4 */
8385         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8386
8387         /* DSCP_O3 */
8388         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8389
8390         /* rsv3 */
8391         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8392
8393         /* DSCP_O2 */
8394         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8395
8396         /* rsv2 */
8397         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8398
8399         /* DSCP_O1 */
8400         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8401
8402         /* rsv1 */
8403         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8404
8405         /* DSCP_O0 */
8406         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8407 }
8408 __PACKING_ATTRIBUTE_STRUCT_END__
8409 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0 ;
8410 #else
8411 typedef struct
8412 {
8413         /* DSCP_O0 */
8414         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8415
8416         /* rsv1 */
8417         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8418
8419         /* DSCP_O1 */
8420         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8421
8422         /* rsv2 */
8423         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8424
8425         /* DSCP_O2 */
8426         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8427
8428         /* rsv3 */
8429         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8430
8431         /* DSCP_O3 */
8432         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8433
8434         /* rsv4 */
8435         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8436
8437         /* DSCP_O4 */
8438         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8439
8440         /* rsv5 */
8441         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8442
8443         /* DSCP_O5 */
8444         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8445
8446         /* rsv6 */
8447         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8448
8449         /* DSCP_O6 */
8450         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8451
8452         /* rsv7 */
8453         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8454
8455         /* DSCP_O7 */
8456         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8457
8458         /* rsv8 */
8459         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8460 }
8461 __PACKING_ATTRIBUTE_STRUCT_END__
8462 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0 ;
8463 #endif
8464
8465 /*****************************************************************************************/
8466 /* DSCP2TCI_TBL0_R1                                                                      */
8467 /* DSCP to TCI Conversion Table 0.  Register 1 that stores convetion code for the follow */
8468 /* ing DSCP values: 0x8..0xf.    Used for conversion in case of IP untagged packet    Th */
8469 /* e coding of each field is done in the following way:  TCI converted field should matc */
8470 /* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
8471 /* r_index*8+octet(or field) index                                                       */
8472 /*****************************************************************************************/
8473
8474 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV8_RSV_VALUE                ( 0x0 )
8475 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
8476 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O7_TCI_VALUE             ( 0x0 )
8477 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
8478 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV7_RSV_VALUE                ( 0x0 )
8479 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
8480 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O6_TCI_VALUE             ( 0x0 )
8481 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
8482 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV6_RSV_VALUE                ( 0x0 )
8483 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
8484 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O5_TCI_VALUE             ( 0x0 )
8485 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
8486 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV5_RSV_VALUE                ( 0x0 )
8487 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
8488 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O4_TCI_VALUE             ( 0x0 )
8489 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
8490 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV4_RSV_VALUE                ( 0x0 )
8491 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
8492 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O3_TCI_VALUE             ( 0x0 )
8493 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
8494 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV3_RSV_VALUE                ( 0x0 )
8495 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
8496 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O2_TCI_VALUE             ( 0x0 )
8497 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
8498 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV2_RSV_VALUE                ( 0x0 )
8499 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
8500 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O1_TCI_VALUE             ( 0x0 )
8501 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
8502 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV1_RSV_VALUE                ( 0x0 )
8503 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
8504 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O0_TCI_VALUE             ( 0x0 )
8505 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
8506
8507
8508 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_OFFSET ( 0x00000104 )
8509
8510 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_OFFSET )
8511 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_ADDRESS ), (r) )
8512 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1_ADDRESS ), (v) )
8513
8514 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8515 typedef struct
8516 {
8517         /* rsv8 */
8518         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8519
8520         /* DSCP_O7 */
8521         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8522
8523         /* rsv7 */
8524         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8525
8526         /* DSCP_O6 */
8527         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8528
8529         /* rsv6 */
8530         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8531
8532         /* DSCP_O5 */
8533         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8534
8535         /* rsv5 */
8536         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8537
8538         /* DSCP_O4 */
8539         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8540
8541         /* rsv4 */
8542         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8543
8544         /* DSCP_O3 */
8545         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8546
8547         /* rsv3 */
8548         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8549
8550         /* DSCP_O2 */
8551         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8552
8553         /* rsv2 */
8554         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8555
8556         /* DSCP_O1 */
8557         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8558
8559         /* rsv1 */
8560         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8561
8562         /* DSCP_O0 */
8563         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8564 }
8565 __PACKING_ATTRIBUTE_STRUCT_END__
8566 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1 ;
8567 #else
8568 typedef struct
8569 {
8570         /* DSCP_O0 */
8571         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8572
8573         /* rsv1 */
8574         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8575
8576         /* DSCP_O1 */
8577         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8578
8579         /* rsv2 */
8580         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8581
8582         /* DSCP_O2 */
8583         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8584
8585         /* rsv3 */
8586         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8587
8588         /* DSCP_O3 */
8589         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8590
8591         /* rsv4 */
8592         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8593
8594         /* DSCP_O4 */
8595         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8596
8597         /* rsv5 */
8598         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8599
8600         /* DSCP_O5 */
8601         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8602
8603         /* rsv6 */
8604         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8605
8606         /* DSCP_O6 */
8607         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8608
8609         /* rsv7 */
8610         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8611
8612         /* DSCP_O7 */
8613         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8614
8615         /* rsv8 */
8616         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8617 }
8618 __PACKING_ATTRIBUTE_STRUCT_END__
8619 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1 ;
8620 #endif
8621
8622 /*****************************************************************************************/
8623 /* DSCP2TCI_TBL0_R2                                                                      */
8624 /* DSCP to TCI Conversion Table 0.  Register 2 that stores convetion code for the follow */
8625 /* ing DSCP values: 0x10..0x17.    Used for conversion in case of IP untagged packet     */
8626 /* The coding of each field is done in the following way:  TCI converted field should ma */
8627 /* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
8628 /* ter_index*8+octet(or field) index                                                     */
8629 /*****************************************************************************************/
8630
8631 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV8_RSV_VALUE                ( 0x0 )
8632 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
8633 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O7_TCI_VALUE             ( 0x0 )
8634 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
8635 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV7_RSV_VALUE                ( 0x0 )
8636 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
8637 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O6_TCI_VALUE             ( 0x0 )
8638 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
8639 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV6_RSV_VALUE                ( 0x0 )
8640 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
8641 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O5_TCI_VALUE             ( 0x0 )
8642 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
8643 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV5_RSV_VALUE                ( 0x0 )
8644 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
8645 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O4_TCI_VALUE             ( 0x0 )
8646 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
8647 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV4_RSV_VALUE                ( 0x0 )
8648 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
8649 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O3_TCI_VALUE             ( 0x0 )
8650 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
8651 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV3_RSV_VALUE                ( 0x0 )
8652 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
8653 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O2_TCI_VALUE             ( 0x0 )
8654 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
8655 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV2_RSV_VALUE                ( 0x0 )
8656 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
8657 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O1_TCI_VALUE             ( 0x0 )
8658 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
8659 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV1_RSV_VALUE                ( 0x0 )
8660 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
8661 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O0_TCI_VALUE             ( 0x0 )
8662 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
8663
8664
8665 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_OFFSET ( 0x00000108 )
8666
8667 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_OFFSET )
8668 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_ADDRESS ), (r) )
8669 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2_ADDRESS ), (v) )
8670
8671 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8672 typedef struct
8673 {
8674         /* rsv8 */
8675         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8676
8677         /* DSCP_O7 */
8678         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8679
8680         /* rsv7 */
8681         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8682
8683         /* DSCP_O6 */
8684         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8685
8686         /* rsv6 */
8687         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8688
8689         /* DSCP_O5 */
8690         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8691
8692         /* rsv5 */
8693         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8694
8695         /* DSCP_O4 */
8696         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8697
8698         /* rsv4 */
8699         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8700
8701         /* DSCP_O3 */
8702         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8703
8704         /* rsv3 */
8705         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8706
8707         /* DSCP_O2 */
8708         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8709
8710         /* rsv2 */
8711         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8712
8713         /* DSCP_O1 */
8714         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8715
8716         /* rsv1 */
8717         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8718
8719         /* DSCP_O0 */
8720         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8721 }
8722 __PACKING_ATTRIBUTE_STRUCT_END__
8723 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2 ;
8724 #else
8725 typedef struct
8726 {
8727         /* DSCP_O0 */
8728         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8729
8730         /* rsv1 */
8731         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8732
8733         /* DSCP_O1 */
8734         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8735
8736         /* rsv2 */
8737         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8738
8739         /* DSCP_O2 */
8740         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8741
8742         /* rsv3 */
8743         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8744
8745         /* DSCP_O3 */
8746         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8747
8748         /* rsv4 */
8749         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8750
8751         /* DSCP_O4 */
8752         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8753
8754         /* rsv5 */
8755         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8756
8757         /* DSCP_O5 */
8758         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8759
8760         /* rsv6 */
8761         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8762
8763         /* DSCP_O6 */
8764         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8765
8766         /* rsv7 */
8767         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8768
8769         /* DSCP_O7 */
8770         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8771
8772         /* rsv8 */
8773         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8774 }
8775 __PACKING_ATTRIBUTE_STRUCT_END__
8776 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2 ;
8777 #endif
8778
8779 /*****************************************************************************************/
8780 /* DSCP2TCI_TBL0_R3                                                                      */
8781 /* DSCP to TCI Conversion Table 0.  Register 3 that stores convetion code for the follow */
8782 /* ing DSCP values: 0x18..0x1f.    Used for conversion in case of IP untagged packet     */
8783 /* The coding of each field is done in the following way:  TCI converted field should ma */
8784 /* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
8785 /* ter_index*8+octet(or field) index                                                     */
8786 /*****************************************************************************************/
8787
8788 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV8_RSV_VALUE                ( 0x0 )
8789 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
8790 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O7_TCI_VALUE             ( 0x0 )
8791 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
8792 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV7_RSV_VALUE                ( 0x0 )
8793 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
8794 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O6_TCI_VALUE             ( 0x0 )
8795 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
8796 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV6_RSV_VALUE                ( 0x0 )
8797 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
8798 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O5_TCI_VALUE             ( 0x0 )
8799 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
8800 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV5_RSV_VALUE                ( 0x0 )
8801 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
8802 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O4_TCI_VALUE             ( 0x0 )
8803 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
8804 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV4_RSV_VALUE                ( 0x0 )
8805 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
8806 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O3_TCI_VALUE             ( 0x0 )
8807 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
8808 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV3_RSV_VALUE                ( 0x0 )
8809 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
8810 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O2_TCI_VALUE             ( 0x0 )
8811 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
8812 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV2_RSV_VALUE                ( 0x0 )
8813 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
8814 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O1_TCI_VALUE             ( 0x0 )
8815 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
8816 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV1_RSV_VALUE                ( 0x0 )
8817 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
8818 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O0_TCI_VALUE             ( 0x0 )
8819 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
8820
8821
8822 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_OFFSET ( 0x0000010C )
8823
8824 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_OFFSET )
8825 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_ADDRESS ), (r) )
8826 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3_ADDRESS ), (v) )
8827
8828 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8829 typedef struct
8830 {
8831         /* rsv8 */
8832         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8833
8834         /* DSCP_O7 */
8835         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8836
8837         /* rsv7 */
8838         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8839
8840         /* DSCP_O6 */
8841         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8842
8843         /* rsv6 */
8844         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8845
8846         /* DSCP_O5 */
8847         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8848
8849         /* rsv5 */
8850         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8851
8852         /* DSCP_O4 */
8853         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8854
8855         /* rsv4 */
8856         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8857
8858         /* DSCP_O3 */
8859         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8860
8861         /* rsv3 */
8862         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8863
8864         /* DSCP_O2 */
8865         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8866
8867         /* rsv2 */
8868         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8869
8870         /* DSCP_O1 */
8871         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8872
8873         /* rsv1 */
8874         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8875
8876         /* DSCP_O0 */
8877         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8878 }
8879 __PACKING_ATTRIBUTE_STRUCT_END__
8880 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3 ;
8881 #else
8882 typedef struct
8883 {
8884         /* DSCP_O0 */
8885         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8886
8887         /* rsv1 */
8888         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8889
8890         /* DSCP_O1 */
8891         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8892
8893         /* rsv2 */
8894         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8895
8896         /* DSCP_O2 */
8897         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8898
8899         /* rsv3 */
8900         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8901
8902         /* DSCP_O3 */
8903         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8904
8905         /* rsv4 */
8906         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8907
8908         /* DSCP_O4 */
8909         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8910
8911         /* rsv5 */
8912         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8913
8914         /* DSCP_O5 */
8915         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8916
8917         /* rsv6 */
8918         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8919
8920         /* DSCP_O6 */
8921         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8922
8923         /* rsv7 */
8924         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8925
8926         /* DSCP_O7 */
8927         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8928
8929         /* rsv8 */
8930         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8931 }
8932 __PACKING_ATTRIBUTE_STRUCT_END__
8933 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3 ;
8934 #endif
8935
8936 /*****************************************************************************************/
8937 /* DSCP2TCI_TBL0_R4                                                                      */
8938 /* DSCP to TCI Conversion Table 0.  Register 4 that stores conversion code for the follo */
8939 /* wing DSCP values: 0x20..0x27.    Used for conversion in case of IP untagged packet    */
8940 /*  The coding of each field is done in the following way:  TCI converted field should m */
8941 /* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
8942 /* ster_index*8+octet(or field) index                                                    */
8943 /*****************************************************************************************/
8944
8945 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV8_RSV_VALUE                ( 0x0 )
8946 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
8947 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O7_TCI_VALUE             ( 0x0 )
8948 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
8949 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV7_RSV_VALUE                ( 0x0 )
8950 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
8951 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O6_TCI_VALUE             ( 0x0 )
8952 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
8953 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV6_RSV_VALUE                ( 0x0 )
8954 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
8955 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O5_TCI_VALUE             ( 0x0 )
8956 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
8957 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV5_RSV_VALUE                ( 0x0 )
8958 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
8959 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O4_TCI_VALUE             ( 0x0 )
8960 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
8961 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV4_RSV_VALUE                ( 0x0 )
8962 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
8963 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O3_TCI_VALUE             ( 0x0 )
8964 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
8965 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV3_RSV_VALUE                ( 0x0 )
8966 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
8967 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O2_TCI_VALUE             ( 0x0 )
8968 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
8969 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV2_RSV_VALUE                ( 0x0 )
8970 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
8971 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O1_TCI_VALUE             ( 0x0 )
8972 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
8973 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV1_RSV_VALUE                ( 0x0 )
8974 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
8975 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O0_TCI_VALUE             ( 0x0 )
8976 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
8977
8978
8979 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_OFFSET ( 0x00000110 )
8980
8981 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_OFFSET )
8982 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_ADDRESS ), (r) )
8983 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4_ADDRESS ), (v) )
8984
8985 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
8986 typedef struct
8987 {
8988         /* rsv8 */
8989         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8990
8991         /* DSCP_O7 */
8992         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8993
8994         /* rsv7 */
8995         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8996
8997         /* DSCP_O6 */
8998         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
8999
9000         /* rsv6 */
9001         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9002
9003         /* DSCP_O5 */
9004         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9005
9006         /* rsv5 */
9007         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9008
9009         /* DSCP_O4 */
9010         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9011
9012         /* rsv4 */
9013         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9014
9015         /* DSCP_O3 */
9016         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9017
9018         /* rsv3 */
9019         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9020
9021         /* DSCP_O2 */
9022         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9023
9024         /* rsv2 */
9025         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9026
9027         /* DSCP_O1 */
9028         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9029
9030         /* rsv1 */
9031         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9032
9033         /* DSCP_O0 */
9034         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9035 }
9036 __PACKING_ATTRIBUTE_STRUCT_END__
9037 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4 ;
9038 #else
9039 typedef struct
9040 {
9041         /* DSCP_O0 */
9042         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9043
9044         /* rsv1 */
9045         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9046
9047         /* DSCP_O1 */
9048         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9049
9050         /* rsv2 */
9051         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9052
9053         /* DSCP_O2 */
9054         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9055
9056         /* rsv3 */
9057         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9058
9059         /* DSCP_O3 */
9060         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9061
9062         /* rsv4 */
9063         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9064
9065         /* DSCP_O4 */
9066         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9067
9068         /* rsv5 */
9069         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9070
9071         /* DSCP_O5 */
9072         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9073
9074         /* rsv6 */
9075         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9076
9077         /* DSCP_O6 */
9078         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9079
9080         /* rsv7 */
9081         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9082
9083         /* DSCP_O7 */
9084         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9085
9086         /* rsv8 */
9087         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9088 }
9089 __PACKING_ATTRIBUTE_STRUCT_END__
9090 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4 ;
9091 #endif
9092
9093 /*****************************************************************************************/
9094 /* DSCP2TCI_TBL0_R5                                                                      */
9095 /* DSCP to TCI Conversion Table 0.  Register 5 that stores conversion code for the follo */
9096 /* wing DSCP values: 0x28..0x2f.    Used for conversion in case of IP untagged packet    */
9097 /*  The coding of each field is done in the following way:  TCI converted field should m */
9098 /* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
9099 /* ster_index*8+octet(or field) index                                                    */
9100 /*****************************************************************************************/
9101
9102 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV8_RSV_VALUE                ( 0x0 )
9103 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
9104 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O7_TCI_VALUE             ( 0x0 )
9105 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
9106 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV7_RSV_VALUE                ( 0x0 )
9107 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
9108 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O6_TCI_VALUE             ( 0x0 )
9109 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
9110 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV6_RSV_VALUE                ( 0x0 )
9111 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
9112 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O5_TCI_VALUE             ( 0x0 )
9113 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
9114 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV5_RSV_VALUE                ( 0x0 )
9115 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
9116 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O4_TCI_VALUE             ( 0x0 )
9117 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
9118 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV4_RSV_VALUE                ( 0x0 )
9119 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
9120 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O3_TCI_VALUE             ( 0x0 )
9121 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
9122 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV3_RSV_VALUE                ( 0x0 )
9123 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
9124 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O2_TCI_VALUE             ( 0x0 )
9125 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
9126 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV2_RSV_VALUE                ( 0x0 )
9127 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
9128 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O1_TCI_VALUE             ( 0x0 )
9129 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
9130 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV1_RSV_VALUE                ( 0x0 )
9131 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
9132 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O0_TCI_VALUE             ( 0x0 )
9133 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
9134
9135
9136 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_OFFSET ( 0x00000114 )
9137
9138 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_OFFSET )
9139 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_ADDRESS ), (r) )
9140 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5_ADDRESS ), (v) )
9141
9142 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
9143 typedef struct
9144 {
9145         /* rsv8 */
9146         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9147
9148         /* DSCP_O7 */
9149         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9150
9151         /* rsv7 */
9152         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9153
9154         /* DSCP_O6 */
9155         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9156
9157         /* rsv6 */
9158         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9159
9160         /* DSCP_O5 */
9161         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9162
9163         /* rsv5 */
9164         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9165
9166         /* DSCP_O4 */
9167         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9168
9169         /* rsv4 */
9170         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9171
9172         /* DSCP_O3 */
9173         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9174
9175         /* rsv3 */
9176         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9177
9178         /* DSCP_O2 */
9179         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9180
9181         /* rsv2 */
9182         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9183
9184         /* DSCP_O1 */
9185         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9186
9187         /* rsv1 */
9188         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9189
9190         /* DSCP_O0 */
9191         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9192 }
9193 __PACKING_ATTRIBUTE_STRUCT_END__
9194 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5 ;
9195 #else
9196 typedef struct
9197 {
9198         /* DSCP_O0 */
9199         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9200
9201         /* rsv1 */
9202         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9203
9204         /* DSCP_O1 */
9205         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9206
9207         /* rsv2 */
9208         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9209
9210         /* DSCP_O2 */
9211         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9212
9213         /* rsv3 */
9214         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9215
9216         /* DSCP_O3 */
9217         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9218
9219         /* rsv4 */
9220         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9221
9222         /* DSCP_O4 */
9223         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9224
9225         /* rsv5 */
9226         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9227
9228         /* DSCP_O5 */
9229         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9230
9231         /* rsv6 */
9232         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9233
9234         /* DSCP_O6 */
9235         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9236
9237         /* rsv7 */
9238         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9239
9240         /* DSCP_O7 */
9241         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9242
9243         /* rsv8 */
9244         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9245 }
9246 __PACKING_ATTRIBUTE_STRUCT_END__
9247 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5 ;
9248 #endif
9249
9250 /*****************************************************************************************/
9251 /* DSCP2TCI_TBL0_R6                                                                      */
9252 /* DSCP to TCI Conversion Table 0.  Register 6 that stores conversion code for the follo */
9253 /* wing DSCP values: 0x30..0x37.    Used for conversion in case of IP untagged packet    */
9254 /*  The coding of each field is done in the following way:  TCI converted field should m */
9255 /* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
9256 /* ster_index*8+octet(or field) index                                                    */
9257 /*****************************************************************************************/
9258
9259 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV8_RSV_VALUE                ( 0x0 )
9260 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
9261 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O7_TCI_VALUE             ( 0x0 )
9262 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
9263 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV7_RSV_VALUE                ( 0x0 )
9264 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
9265 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O6_TCI_VALUE             ( 0x0 )
9266 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
9267 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV6_RSV_VALUE                ( 0x0 )
9268 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
9269 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O5_TCI_VALUE             ( 0x0 )
9270 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
9271 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV5_RSV_VALUE                ( 0x0 )
9272 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
9273 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O4_TCI_VALUE             ( 0x0 )
9274 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
9275 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV4_RSV_VALUE                ( 0x0 )
9276 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
9277 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O3_TCI_VALUE             ( 0x0 )
9278 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
9279 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV3_RSV_VALUE                ( 0x0 )
9280 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
9281 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O2_TCI_VALUE             ( 0x0 )
9282 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
9283 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV2_RSV_VALUE                ( 0x0 )
9284 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
9285 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O1_TCI_VALUE             ( 0x0 )
9286 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
9287 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV1_RSV_VALUE                ( 0x0 )
9288 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
9289 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O0_TCI_VALUE             ( 0x0 )
9290 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
9291
9292
9293 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_OFFSET ( 0x00000118 )
9294
9295 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_OFFSET )
9296 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_ADDRESS ), (r) )
9297 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6_ADDRESS ), (v) )
9298
9299 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
9300 typedef struct
9301 {
9302         /* rsv8 */
9303         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9304
9305         /* DSCP_O7 */
9306         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9307
9308         /* rsv7 */
9309         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9310
9311         /* DSCP_O6 */
9312         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9313
9314         /* rsv6 */
9315         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9316
9317         /* DSCP_O5 */
9318         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9319
9320         /* rsv5 */
9321         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9322
9323         /* DSCP_O4 */
9324         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9325
9326         /* rsv4 */
9327         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9328
9329         /* DSCP_O3 */
9330         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9331
9332         /* rsv3 */
9333         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9334
9335         /* DSCP_O2 */
9336         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9337
9338         /* rsv2 */
9339         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9340
9341         /* DSCP_O1 */
9342         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9343
9344         /* rsv1 */
9345         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9346
9347         /* DSCP_O0 */
9348         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9349 }
9350 __PACKING_ATTRIBUTE_STRUCT_END__
9351 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6 ;
9352 #else
9353 typedef struct
9354 {
9355         /* DSCP_O0 */
9356         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9357
9358         /* rsv1 */
9359         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9360
9361         /* DSCP_O1 */
9362         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9363
9364         /* rsv2 */
9365         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9366
9367         /* DSCP_O2 */
9368         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9369
9370         /* rsv3 */
9371         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9372
9373         /* DSCP_O3 */
9374         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9375
9376         /* rsv4 */
9377         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9378
9379         /* DSCP_O4 */
9380         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9381
9382         /* rsv5 */
9383         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9384
9385         /* DSCP_O5 */
9386         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9387
9388         /* rsv6 */
9389         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9390
9391         /* DSCP_O6 */
9392         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9393
9394         /* rsv7 */
9395         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9396
9397         /* DSCP_O7 */
9398         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9399
9400         /* rsv8 */
9401         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9402 }
9403 __PACKING_ATTRIBUTE_STRUCT_END__
9404 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6 ;
9405 #endif
9406
9407 /*****************************************************************************************/
9408 /* DSCP2TCI_TBL0_R7                                                                      */
9409 /* DSCP to TCI Conversion Table 0.  Register 7 that stores conversion code for the follo */
9410 /* wing DSCP values: 0x3c..0x3f.    Used for conversion in case of IP untagged packet    */
9411 /*    The coding of each field is done in the following way:  TCI converted field should */
9412 /*  match DSCP index (from 0 to 63). This index is applied by the following equation: re */
9413 /* gister_index*8+octet(or field) index                                                  */
9414 /*****************************************************************************************/
9415
9416 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV8_RSV_VALUE                ( 0x0 )
9417 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
9418 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O7_TCI_VALUE             ( 0x0 )
9419 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
9420 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV7_RSV_VALUE                ( 0x0 )
9421 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
9422 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O6_TCI_VALUE             ( 0x0 )
9423 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
9424 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV6_RSV_VALUE                ( 0x0 )
9425 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
9426 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O5_TCI_VALUE             ( 0x0 )
9427 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
9428 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV5_RSV_VALUE                ( 0x0 )
9429 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
9430 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O4_TCI_VALUE             ( 0x0 )
9431 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
9432 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV4_RSV_VALUE                ( 0x0 )
9433 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
9434 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O3_TCI_VALUE             ( 0x0 )
9435 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
9436 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV3_RSV_VALUE                ( 0x0 )
9437 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
9438 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O2_TCI_VALUE             ( 0x0 )
9439 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
9440 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV2_RSV_VALUE                ( 0x0 )
9441 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
9442 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O1_TCI_VALUE             ( 0x0 )
9443 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
9444 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV1_RSV_VALUE                ( 0x0 )
9445 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
9446 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O0_TCI_VALUE             ( 0x0 )
9447 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
9448
9449
9450 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_OFFSET ( 0x0000011C )
9451
9452 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_OFFSET )
9453 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_ADDRESS ), (r) )
9454 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7_ADDRESS ), (v) )
9455
9456 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
9457 typedef struct
9458 {
9459         /* rsv8 */
9460         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9461
9462         /* DSCP_O7 */
9463         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9464
9465         /* rsv7 */
9466         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9467
9468         /* DSCP_O6 */
9469         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9470
9471         /* rsv6 */
9472         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9473
9474         /* DSCP_O5 */
9475         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9476
9477         /* rsv5 */
9478         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9479
9480         /* DSCP_O4 */
9481         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9482
9483         /* rsv4 */
9484         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9485
9486         /* DSCP_O3 */
9487         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9488
9489         /* rsv3 */
9490         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9491
9492         /* DSCP_O2 */
9493         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9494
9495         /* rsv2 */
9496         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9497
9498         /* DSCP_O1 */
9499         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9500
9501         /* rsv1 */
9502         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9503
9504         /* DSCP_O0 */
9505         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9506 }
9507 __PACKING_ATTRIBUTE_STRUCT_END__
9508 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7 ;
9509 #else
9510 typedef struct
9511 {
9512         /* DSCP_O0 */
9513         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9514
9515         /* rsv1 */
9516         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9517
9518         /* DSCP_O1 */
9519         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9520
9521         /* rsv2 */
9522         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9523
9524         /* DSCP_O2 */
9525         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9526
9527         /* rsv3 */
9528         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9529
9530         /* DSCP_O3 */
9531         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9532
9533         /* rsv4 */
9534         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9535
9536         /* DSCP_O4 */
9537         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9538
9539         /* rsv5 */
9540         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9541
9542         /* DSCP_O5 */
9543         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9544
9545         /* rsv6 */
9546         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9547
9548         /* DSCP_O6 */
9549         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9550
9551         /* rsv7 */
9552         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9553
9554         /* DSCP_O7 */
9555         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9556
9557         /* rsv8 */
9558         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9559 }
9560 __PACKING_ATTRIBUTE_STRUCT_END__
9561 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7 ;
9562 #endif
9563
9564 /*****************************************************************************************/
9565 /* DSCP2TCI_TBL1_R0                                                                      */
9566 /* DSCP to TCI Conversion Table 1.  Register 0 that stores convetion code for the follow */
9567 /* ing DSCP values: 0x0..0x7.    Used for conversion in case of IP untagged packet    Th */
9568 /* e coding of each field is done in the following way:  TCI converted field should matc */
9569 /* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
9570 /* r_index*8+octet(or field) index                                                       */
9571 /*****************************************************************************************/
9572
9573 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV8_RSV_VALUE                ( 0x0 )
9574 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
9575 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O7_TCI_VALUE             ( 0x0 )
9576 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
9577 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV7_RSV_VALUE                ( 0x0 )
9578 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
9579 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O6_TCI_VALUE             ( 0x0 )
9580 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
9581 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV6_RSV_VALUE                ( 0x0 )
9582 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
9583 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O5_TCI_VALUE             ( 0x0 )
9584 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
9585 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV5_RSV_VALUE                ( 0x0 )
9586 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
9587 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O4_TCI_VALUE             ( 0x0 )
9588 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
9589 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV4_RSV_VALUE                ( 0x0 )
9590 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
9591 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O3_TCI_VALUE             ( 0x0 )
9592 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
9593 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV3_RSV_VALUE                ( 0x0 )
9594 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
9595 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O2_TCI_VALUE             ( 0x0 )
9596 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
9597 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV2_RSV_VALUE                ( 0x0 )
9598 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
9599 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O1_TCI_VALUE             ( 0x0 )
9600 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
9601 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV1_RSV_VALUE                ( 0x0 )
9602 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
9603 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O0_TCI_VALUE             ( 0x0 )
9604 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
9605
9606
9607 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_OFFSET ( 0x00000120 )
9608
9609 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_OFFSET )
9610 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_ADDRESS ), (r) )
9611 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0_ADDRESS ), (v) )
9612
9613 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
9614 typedef struct
9615 {
9616         /* rsv8 */
9617         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9618
9619         /* DSCP_O7 */
9620         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9621
9622         /* rsv7 */
9623         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9624
9625         /* DSCP_O6 */
9626         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9627
9628         /* rsv6 */
9629         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9630
9631         /* DSCP_O5 */
9632         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9633
9634         /* rsv5 */
9635         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9636
9637         /* DSCP_O4 */
9638         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9639
9640         /* rsv4 */
9641         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9642
9643         /* DSCP_O3 */
9644         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9645
9646         /* rsv3 */
9647         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9648
9649         /* DSCP_O2 */
9650         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9651
9652         /* rsv2 */
9653         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9654
9655         /* DSCP_O1 */
9656         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9657
9658         /* rsv1 */
9659         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9660
9661         /* DSCP_O0 */
9662         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9663 }
9664 __PACKING_ATTRIBUTE_STRUCT_END__
9665 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0 ;
9666 #else
9667 typedef struct
9668 {
9669         /* DSCP_O0 */
9670         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9671
9672         /* rsv1 */
9673         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9674
9675         /* DSCP_O1 */
9676         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9677
9678         /* rsv2 */
9679         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9680
9681         /* DSCP_O2 */
9682         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9683
9684         /* rsv3 */
9685         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9686
9687         /* DSCP_O3 */
9688         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9689
9690         /* rsv4 */
9691         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9692
9693         /* DSCP_O4 */
9694         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9695
9696         /* rsv5 */
9697         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9698
9699         /* DSCP_O5 */
9700         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9701
9702         /* rsv6 */
9703         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9704
9705         /* DSCP_O6 */
9706         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9707
9708         /* rsv7 */
9709         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9710
9711         /* DSCP_O7 */
9712         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9713
9714         /* rsv8 */
9715         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9716 }
9717 __PACKING_ATTRIBUTE_STRUCT_END__
9718 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0 ;
9719 #endif
9720
9721 /*****************************************************************************************/
9722 /* DSCP2TCI_TBL1_R1                                                                      */
9723 /* DSCP to TCI Conversion Table 1.  Register 1 that stores convetion code for the follow */
9724 /* ing DSCP values: 0x8..0xf.    Used for conversion in case of IP untagged packet    Th */
9725 /* e coding of each field is done in the following way:  TCI converted field should matc */
9726 /* h DSCP index (from 0 to 63). This index is applied by the following equation: registe */
9727 /* r_index*8+octet(or field) index                                                       */
9728 /*****************************************************************************************/
9729
9730 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV8_RSV_VALUE                ( 0x0 )
9731 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
9732 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O7_TCI_VALUE             ( 0x0 )
9733 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
9734 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV7_RSV_VALUE                ( 0x0 )
9735 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
9736 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O6_TCI_VALUE             ( 0x0 )
9737 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
9738 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV6_RSV_VALUE                ( 0x0 )
9739 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
9740 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O5_TCI_VALUE             ( 0x0 )
9741 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
9742 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV5_RSV_VALUE                ( 0x0 )
9743 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
9744 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O4_TCI_VALUE             ( 0x0 )
9745 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
9746 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV4_RSV_VALUE                ( 0x0 )
9747 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
9748 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O3_TCI_VALUE             ( 0x0 )
9749 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
9750 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV3_RSV_VALUE                ( 0x0 )
9751 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
9752 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O2_TCI_VALUE             ( 0x0 )
9753 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
9754 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV2_RSV_VALUE                ( 0x0 )
9755 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
9756 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O1_TCI_VALUE             ( 0x0 )
9757 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
9758 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV1_RSV_VALUE                ( 0x0 )
9759 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
9760 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O0_TCI_VALUE             ( 0x0 )
9761 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
9762
9763
9764 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_OFFSET ( 0x00000124 )
9765
9766 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_OFFSET )
9767 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_ADDRESS ), (r) )
9768 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1_ADDRESS ), (v) )
9769
9770 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
9771 typedef struct
9772 {
9773         /* rsv8 */
9774         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9775
9776         /* DSCP_O7 */
9777         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9778
9779         /* rsv7 */
9780         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9781
9782         /* DSCP_O6 */
9783         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9784
9785         /* rsv6 */
9786         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9787
9788         /* DSCP_O5 */
9789         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9790
9791         /* rsv5 */
9792         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9793
9794         /* DSCP_O4 */
9795         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9796
9797         /* rsv4 */
9798         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9799
9800         /* DSCP_O3 */
9801         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9802
9803         /* rsv3 */
9804         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9805
9806         /* DSCP_O2 */
9807         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9808
9809         /* rsv2 */
9810         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9811
9812         /* DSCP_O1 */
9813         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9814
9815         /* rsv1 */
9816         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9817
9818         /* DSCP_O0 */
9819         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9820 }
9821 __PACKING_ATTRIBUTE_STRUCT_END__
9822 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1 ;
9823 #else
9824 typedef struct
9825 {
9826         /* DSCP_O0 */
9827         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9828
9829         /* rsv1 */
9830         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9831
9832         /* DSCP_O1 */
9833         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9834
9835         /* rsv2 */
9836         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9837
9838         /* DSCP_O2 */
9839         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9840
9841         /* rsv3 */
9842         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9843
9844         /* DSCP_O3 */
9845         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9846
9847         /* rsv4 */
9848         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9849
9850         /* DSCP_O4 */
9851         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9852
9853         /* rsv5 */
9854         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9855
9856         /* DSCP_O5 */
9857         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9858
9859         /* rsv6 */
9860         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9861
9862         /* DSCP_O6 */
9863         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9864
9865         /* rsv7 */
9866         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9867
9868         /* DSCP_O7 */
9869         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9870
9871         /* rsv8 */
9872         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9873 }
9874 __PACKING_ATTRIBUTE_STRUCT_END__
9875 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1 ;
9876 #endif
9877
9878 /*****************************************************************************************/
9879 /* DSCP2TCI_TBL1_R2                                                                      */
9880 /* DSCP to TCI Conversion Table 1.  Register 2 that stores convetion code for the follow */
9881 /* ing DSCP values: 0x10..0x17.    Used for conversion in case of IP untagged packet     */
9882 /* The coding of each field is done in the following way:  TCI converted field should ma */
9883 /* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
9884 /* ter_index*8+octet(or field) index                                                     */
9885 /*****************************************************************************************/
9886
9887 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV8_RSV_VALUE                ( 0x0 )
9888 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
9889 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O7_TCI_VALUE             ( 0x0 )
9890 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
9891 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV7_RSV_VALUE                ( 0x0 )
9892 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
9893 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O6_TCI_VALUE             ( 0x0 )
9894 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
9895 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV6_RSV_VALUE                ( 0x0 )
9896 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
9897 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O5_TCI_VALUE             ( 0x0 )
9898 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
9899 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV5_RSV_VALUE                ( 0x0 )
9900 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
9901 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O4_TCI_VALUE             ( 0x0 )
9902 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
9903 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV4_RSV_VALUE                ( 0x0 )
9904 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
9905 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O3_TCI_VALUE             ( 0x0 )
9906 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
9907 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV3_RSV_VALUE                ( 0x0 )
9908 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
9909 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O2_TCI_VALUE             ( 0x0 )
9910 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
9911 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV2_RSV_VALUE                ( 0x0 )
9912 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
9913 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O1_TCI_VALUE             ( 0x0 )
9914 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
9915 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV1_RSV_VALUE                ( 0x0 )
9916 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
9917 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O0_TCI_VALUE             ( 0x0 )
9918 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
9919
9920
9921 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_OFFSET ( 0x00000128 )
9922
9923 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_OFFSET )
9924 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_ADDRESS ), (r) )
9925 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2_ADDRESS ), (v) )
9926
9927 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
9928 typedef struct
9929 {
9930         /* rsv8 */
9931         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9932
9933         /* DSCP_O7 */
9934         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9935
9936         /* rsv7 */
9937         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9938
9939         /* DSCP_O6 */
9940         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9941
9942         /* rsv6 */
9943         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9944
9945         /* DSCP_O5 */
9946         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9947
9948         /* rsv5 */
9949         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9950
9951         /* DSCP_O4 */
9952         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9953
9954         /* rsv4 */
9955         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9956
9957         /* DSCP_O3 */
9958         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9959
9960         /* rsv3 */
9961         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9962
9963         /* DSCP_O2 */
9964         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9965
9966         /* rsv2 */
9967         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9968
9969         /* DSCP_O1 */
9970         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9971
9972         /* rsv1 */
9973         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9974
9975         /* DSCP_O0 */
9976         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9977 }
9978 __PACKING_ATTRIBUTE_STRUCT_END__
9979 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2 ;
9980 #else
9981 typedef struct
9982 {
9983         /* DSCP_O0 */
9984         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9985
9986         /* rsv1 */
9987         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9988
9989         /* DSCP_O1 */
9990         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9991
9992         /* rsv2 */
9993         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9994
9995         /* DSCP_O2 */
9996         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
9997
9998         /* rsv3 */
9999         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10000
10001         /* DSCP_O3 */
10002         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10003
10004         /* rsv4 */
10005         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10006
10007         /* DSCP_O4 */
10008         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10009
10010         /* rsv5 */
10011         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10012
10013         /* DSCP_O5 */
10014         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10015
10016         /* rsv6 */
10017         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10018
10019         /* DSCP_O6 */
10020         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10021
10022         /* rsv7 */
10023         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10024
10025         /* DSCP_O7 */
10026         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10027
10028         /* rsv8 */
10029         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10030 }
10031 __PACKING_ATTRIBUTE_STRUCT_END__
10032 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2 ;
10033 #endif
10034
10035 /*****************************************************************************************/
10036 /* DSCP2TCI_TBL1_R3                                                                      */
10037 /* DSCP to TCI Conversion Table 1.  Register 3 that stores convetion code for the follow */
10038 /* ing DSCP values: 0x18..0x1f.    Used for conversion in case of IP untagged packet     */
10039 /* The coding of each field is done in the following way:  TCI converted field should ma */
10040 /* tch DSCP index (from 0 to 63). This index is applied by the following equation: regis */
10041 /* ter_index*8+octet(or field) index                                                     */
10042 /*****************************************************************************************/
10043
10044 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV8_RSV_VALUE                ( 0x0 )
10045 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
10046 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O7_TCI_VALUE             ( 0x0 )
10047 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
10048 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV7_RSV_VALUE                ( 0x0 )
10049 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
10050 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O6_TCI_VALUE             ( 0x0 )
10051 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
10052 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV6_RSV_VALUE                ( 0x0 )
10053 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
10054 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O5_TCI_VALUE             ( 0x0 )
10055 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
10056 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV5_RSV_VALUE                ( 0x0 )
10057 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
10058 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O4_TCI_VALUE             ( 0x0 )
10059 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
10060 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV4_RSV_VALUE                ( 0x0 )
10061 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
10062 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O3_TCI_VALUE             ( 0x0 )
10063 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
10064 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV3_RSV_VALUE                ( 0x0 )
10065 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
10066 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O2_TCI_VALUE             ( 0x0 )
10067 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
10068 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV2_RSV_VALUE                ( 0x0 )
10069 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
10070 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O1_TCI_VALUE             ( 0x0 )
10071 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
10072 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV1_RSV_VALUE                ( 0x0 )
10073 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
10074 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O0_TCI_VALUE             ( 0x0 )
10075 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
10076
10077
10078 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_OFFSET ( 0x0000012C )
10079
10080 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_OFFSET )
10081 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_ADDRESS ), (r) )
10082 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3_ADDRESS ), (v) )
10083
10084 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10085 typedef struct
10086 {
10087         /* rsv8 */
10088         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10089
10090         /* DSCP_O7 */
10091         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10092
10093         /* rsv7 */
10094         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10095
10096         /* DSCP_O6 */
10097         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10098
10099         /* rsv6 */
10100         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10101
10102         /* DSCP_O5 */
10103         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10104
10105         /* rsv5 */
10106         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10107
10108         /* DSCP_O4 */
10109         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10110
10111         /* rsv4 */
10112         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10113
10114         /* DSCP_O3 */
10115         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10116
10117         /* rsv3 */
10118         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10119
10120         /* DSCP_O2 */
10121         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10122
10123         /* rsv2 */
10124         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10125
10126         /* DSCP_O1 */
10127         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10128
10129         /* rsv1 */
10130         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10131
10132         /* DSCP_O0 */
10133         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10134 }
10135 __PACKING_ATTRIBUTE_STRUCT_END__
10136 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3 ;
10137 #else
10138 typedef struct
10139 {
10140         /* DSCP_O0 */
10141         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10142
10143         /* rsv1 */
10144         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10145
10146         /* DSCP_O1 */
10147         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10148
10149         /* rsv2 */
10150         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10151
10152         /* DSCP_O2 */
10153         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10154
10155         /* rsv3 */
10156         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10157
10158         /* DSCP_O3 */
10159         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10160
10161         /* rsv4 */
10162         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10163
10164         /* DSCP_O4 */
10165         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10166
10167         /* rsv5 */
10168         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10169
10170         /* DSCP_O5 */
10171         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10172
10173         /* rsv6 */
10174         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10175
10176         /* DSCP_O6 */
10177         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10178
10179         /* rsv7 */
10180         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10181
10182         /* DSCP_O7 */
10183         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10184
10185         /* rsv8 */
10186         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10187 }
10188 __PACKING_ATTRIBUTE_STRUCT_END__
10189 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3 ;
10190 #endif
10191
10192 /*****************************************************************************************/
10193 /* DSCP2TCI_TBL1_R4                                                                      */
10194 /* DSCP to TCI Conversion Table 1.  Register 4 that stores conversion code for the follo */
10195 /* wing DSCP values: 0x20..0x27.    Used for conversion in case of IP untagged packet    */
10196 /*  The coding of each field is done in the following way:  TCI converted field should m */
10197 /* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
10198 /* ster_index*8+octet(or field) index                                                    */
10199 /*****************************************************************************************/
10200
10201 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV8_RSV_VALUE                ( 0x0 )
10202 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
10203 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O7_TCI_VALUE             ( 0x0 )
10204 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
10205 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV7_RSV_VALUE                ( 0x0 )
10206 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
10207 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O6_TCI_VALUE             ( 0x0 )
10208 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
10209 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV6_RSV_VALUE                ( 0x0 )
10210 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
10211 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O5_TCI_VALUE             ( 0x0 )
10212 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
10213 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV5_RSV_VALUE                ( 0x0 )
10214 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
10215 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O4_TCI_VALUE             ( 0x0 )
10216 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
10217 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV4_RSV_VALUE                ( 0x0 )
10218 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
10219 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O3_TCI_VALUE             ( 0x0 )
10220 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
10221 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV3_RSV_VALUE                ( 0x0 )
10222 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
10223 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O2_TCI_VALUE             ( 0x0 )
10224 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
10225 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV2_RSV_VALUE                ( 0x0 )
10226 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
10227 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O1_TCI_VALUE             ( 0x0 )
10228 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
10229 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV1_RSV_VALUE                ( 0x0 )
10230 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
10231 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O0_TCI_VALUE             ( 0x0 )
10232 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
10233
10234
10235 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_OFFSET ( 0x00000130 )
10236
10237 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_OFFSET )
10238 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_ADDRESS ), (r) )
10239 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4_ADDRESS ), (v) )
10240
10241 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10242 typedef struct
10243 {
10244         /* rsv8 */
10245         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10246
10247         /* DSCP_O7 */
10248         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10249
10250         /* rsv7 */
10251         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10252
10253         /* DSCP_O6 */
10254         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10255
10256         /* rsv6 */
10257         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10258
10259         /* DSCP_O5 */
10260         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10261
10262         /* rsv5 */
10263         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10264
10265         /* DSCP_O4 */
10266         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10267
10268         /* rsv4 */
10269         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10270
10271         /* DSCP_O3 */
10272         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10273
10274         /* rsv3 */
10275         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10276
10277         /* DSCP_O2 */
10278         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10279
10280         /* rsv2 */
10281         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10282
10283         /* DSCP_O1 */
10284         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10285
10286         /* rsv1 */
10287         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10288
10289         /* DSCP_O0 */
10290         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10291 }
10292 __PACKING_ATTRIBUTE_STRUCT_END__
10293 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4 ;
10294 #else
10295 typedef struct
10296 {
10297         /* DSCP_O0 */
10298         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10299
10300         /* rsv1 */
10301         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10302
10303         /* DSCP_O1 */
10304         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10305
10306         /* rsv2 */
10307         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10308
10309         /* DSCP_O2 */
10310         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10311
10312         /* rsv3 */
10313         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10314
10315         /* DSCP_O3 */
10316         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10317
10318         /* rsv4 */
10319         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10320
10321         /* DSCP_O4 */
10322         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10323
10324         /* rsv5 */
10325         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10326
10327         /* DSCP_O5 */
10328         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10329
10330         /* rsv6 */
10331         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10332
10333         /* DSCP_O6 */
10334         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10335
10336         /* rsv7 */
10337         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10338
10339         /* DSCP_O7 */
10340         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10341
10342         /* rsv8 */
10343         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10344 }
10345 __PACKING_ATTRIBUTE_STRUCT_END__
10346 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4 ;
10347 #endif
10348
10349 /*****************************************************************************************/
10350 /* DSCP2TCI_TBL1_R5                                                                      */
10351 /* DSCP to TCI Conversion Table 1.  Register 5 that stores conversion code for the follo */
10352 /* wing DSCP values: 0x28..0x2f.    Used for conversion in case of IP untagged packet    */
10353 /*  The coding of each field is done in the following way:  TCI converted field should m */
10354 /* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
10355 /* ster_index*8+octet(or field) index                                                    */
10356 /*****************************************************************************************/
10357
10358 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV8_RSV_VALUE                ( 0x0 )
10359 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
10360 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O7_TCI_VALUE             ( 0x0 )
10361 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
10362 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV7_RSV_VALUE                ( 0x0 )
10363 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
10364 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O6_TCI_VALUE             ( 0x0 )
10365 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
10366 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV6_RSV_VALUE                ( 0x0 )
10367 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
10368 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O5_TCI_VALUE             ( 0x0 )
10369 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
10370 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV5_RSV_VALUE                ( 0x0 )
10371 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
10372 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O4_TCI_VALUE             ( 0x0 )
10373 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
10374 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV4_RSV_VALUE                ( 0x0 )
10375 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
10376 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O3_TCI_VALUE             ( 0x0 )
10377 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
10378 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV3_RSV_VALUE                ( 0x0 )
10379 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
10380 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O2_TCI_VALUE             ( 0x0 )
10381 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
10382 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV2_RSV_VALUE                ( 0x0 )
10383 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
10384 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O1_TCI_VALUE             ( 0x0 )
10385 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
10386 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV1_RSV_VALUE                ( 0x0 )
10387 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
10388 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O0_TCI_VALUE             ( 0x0 )
10389 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
10390
10391
10392 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_OFFSET ( 0x00000134 )
10393
10394 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_OFFSET )
10395 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_ADDRESS ), (r) )
10396 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5_ADDRESS ), (v) )
10397
10398 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10399 typedef struct
10400 {
10401         /* rsv8 */
10402         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10403
10404         /* DSCP_O7 */
10405         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10406
10407         /* rsv7 */
10408         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10409
10410         /* DSCP_O6 */
10411         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10412
10413         /* rsv6 */
10414         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10415
10416         /* DSCP_O5 */
10417         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10418
10419         /* rsv5 */
10420         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10421
10422         /* DSCP_O4 */
10423         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10424
10425         /* rsv4 */
10426         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10427
10428         /* DSCP_O3 */
10429         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10430
10431         /* rsv3 */
10432         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10433
10434         /* DSCP_O2 */
10435         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10436
10437         /* rsv2 */
10438         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10439
10440         /* DSCP_O1 */
10441         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10442
10443         /* rsv1 */
10444         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10445
10446         /* DSCP_O0 */
10447         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10448 }
10449 __PACKING_ATTRIBUTE_STRUCT_END__
10450 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5 ;
10451 #else
10452 typedef struct
10453 {
10454         /* DSCP_O0 */
10455         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10456
10457         /* rsv1 */
10458         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10459
10460         /* DSCP_O1 */
10461         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10462
10463         /* rsv2 */
10464         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10465
10466         /* DSCP_O2 */
10467         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10468
10469         /* rsv3 */
10470         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10471
10472         /* DSCP_O3 */
10473         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10474
10475         /* rsv4 */
10476         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10477
10478         /* DSCP_O4 */
10479         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10480
10481         /* rsv5 */
10482         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10483
10484         /* DSCP_O5 */
10485         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10486
10487         /* rsv6 */
10488         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10489
10490         /* DSCP_O6 */
10491         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10492
10493         /* rsv7 */
10494         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10495
10496         /* DSCP_O7 */
10497         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10498
10499         /* rsv8 */
10500         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10501 }
10502 __PACKING_ATTRIBUTE_STRUCT_END__
10503 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5 ;
10504 #endif
10505
10506 /*****************************************************************************************/
10507 /* DSCP2TCI_TBL1_R6                                                                      */
10508 /* DSCP to TCI Conversion Table 1.  Register 6 that stores conversion code for the follo */
10509 /* wing DSCP values: 0x30..0x37.    Used for conversion in case of IP untagged packet    */
10510 /*  The coding of each field is done in the following way:  TCI converted field should m */
10511 /* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
10512 /* ster_index*8+octet(or field) index                                                    */
10513 /*****************************************************************************************/
10514
10515 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV8_RSV_VALUE                ( 0x0 )
10516 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
10517 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O7_TCI_VALUE             ( 0x0 )
10518 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
10519 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV7_RSV_VALUE                ( 0x0 )
10520 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
10521 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O6_TCI_VALUE             ( 0x0 )
10522 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
10523 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV6_RSV_VALUE                ( 0x0 )
10524 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
10525 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O5_TCI_VALUE             ( 0x0 )
10526 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
10527 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV5_RSV_VALUE                ( 0x0 )
10528 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
10529 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O4_TCI_VALUE             ( 0x0 )
10530 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
10531 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV4_RSV_VALUE                ( 0x0 )
10532 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
10533 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O3_TCI_VALUE             ( 0x0 )
10534 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
10535 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV3_RSV_VALUE                ( 0x0 )
10536 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
10537 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O2_TCI_VALUE             ( 0x0 )
10538 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
10539 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV2_RSV_VALUE                ( 0x0 )
10540 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
10541 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O1_TCI_VALUE             ( 0x0 )
10542 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
10543 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV1_RSV_VALUE                ( 0x0 )
10544 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
10545 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O0_TCI_VALUE             ( 0x0 )
10546 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
10547
10548
10549 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_OFFSET ( 0x00000138 )
10550
10551 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_OFFSET )
10552 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_ADDRESS ), (r) )
10553 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6_ADDRESS ), (v) )
10554
10555 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10556 typedef struct
10557 {
10558         /* rsv8 */
10559         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10560
10561         /* DSCP_O7 */
10562         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10563
10564         /* rsv7 */
10565         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10566
10567         /* DSCP_O6 */
10568         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10569
10570         /* rsv6 */
10571         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10572
10573         /* DSCP_O5 */
10574         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10575
10576         /* rsv5 */
10577         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10578
10579         /* DSCP_O4 */
10580         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10581
10582         /* rsv4 */
10583         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10584
10585         /* DSCP_O3 */
10586         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10587
10588         /* rsv3 */
10589         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10590
10591         /* DSCP_O2 */
10592         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10593
10594         /* rsv2 */
10595         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10596
10597         /* DSCP_O1 */
10598         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10599
10600         /* rsv1 */
10601         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10602
10603         /* DSCP_O0 */
10604         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10605 }
10606 __PACKING_ATTRIBUTE_STRUCT_END__
10607 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6 ;
10608 #else
10609 typedef struct
10610 {
10611         /* DSCP_O0 */
10612         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10613
10614         /* rsv1 */
10615         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10616
10617         /* DSCP_O1 */
10618         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10619
10620         /* rsv2 */
10621         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10622
10623         /* DSCP_O2 */
10624         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10625
10626         /* rsv3 */
10627         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10628
10629         /* DSCP_O3 */
10630         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10631
10632         /* rsv4 */
10633         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10634
10635         /* DSCP_O4 */
10636         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10637
10638         /* rsv5 */
10639         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10640
10641         /* DSCP_O5 */
10642         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10643
10644         /* rsv6 */
10645         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10646
10647         /* DSCP_O6 */
10648         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10649
10650         /* rsv7 */
10651         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10652
10653         /* DSCP_O7 */
10654         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10655
10656         /* rsv8 */
10657         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10658 }
10659 __PACKING_ATTRIBUTE_STRUCT_END__
10660 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6 ;
10661 #endif
10662
10663 /*****************************************************************************************/
10664 /* DSCP2TCI_TBL1_R7                                                                      */
10665 /* DSCP to TCI Conversion Table 1.  Register 7 that stores conversion code for the follo */
10666 /* wing DSCP values: 0x3c..0x3f.    Used for conversion in case of IP untagged packet    */
10667 /*  The coding of each field is done in the following way:  TCI converted field should m */
10668 /* atch DSCP index (from 0 to 63). This index is applied by the following equation: regi */
10669 /* ster_index*8+octet(or field) index                                                    */
10670 /*****************************************************************************************/
10671
10672 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV8_RSV_VALUE                ( 0x0 )
10673 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV8_RSV_VALUE_RESET_VALUE    ( 0x0 )
10674 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O7_TCI_VALUE             ( 0x0 )
10675 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O7_TCI_VALUE_RESET_VALUE ( 0x0 )
10676 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV7_RSV_VALUE                ( 0x0 )
10677 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV7_RSV_VALUE_RESET_VALUE    ( 0x0 )
10678 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O6_TCI_VALUE             ( 0x0 )
10679 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O6_TCI_VALUE_RESET_VALUE ( 0x0 )
10680 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV6_RSV_VALUE                ( 0x0 )
10681 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV6_RSV_VALUE_RESET_VALUE    ( 0x0 )
10682 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O5_TCI_VALUE             ( 0x0 )
10683 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O5_TCI_VALUE_RESET_VALUE ( 0x0 )
10684 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV5_RSV_VALUE                ( 0x0 )
10685 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV5_RSV_VALUE_RESET_VALUE    ( 0x0 )
10686 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O4_TCI_VALUE             ( 0x0 )
10687 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O4_TCI_VALUE_RESET_VALUE ( 0x0 )
10688 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV4_RSV_VALUE                ( 0x0 )
10689 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV4_RSV_VALUE_RESET_VALUE    ( 0x0 )
10690 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O3_TCI_VALUE             ( 0x0 )
10691 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O3_TCI_VALUE_RESET_VALUE ( 0x0 )
10692 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV3_RSV_VALUE                ( 0x0 )
10693 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV3_RSV_VALUE_RESET_VALUE    ( 0x0 )
10694 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O2_TCI_VALUE             ( 0x0 )
10695 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O2_TCI_VALUE_RESET_VALUE ( 0x0 )
10696 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV2_RSV_VALUE                ( 0x0 )
10697 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV2_RSV_VALUE_RESET_VALUE    ( 0x0 )
10698 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O1_TCI_VALUE             ( 0x0 )
10699 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O1_TCI_VALUE_RESET_VALUE ( 0x0 )
10700 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV1_RSV_VALUE                ( 0x0 )
10701 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_RSV1_RSV_VALUE_RESET_VALUE    ( 0x0 )
10702 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O0_TCI_VALUE             ( 0x0 )
10703 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_DSCP_O0_TCI_VALUE_RESET_VALUE ( 0x0 )
10704
10705
10706 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_OFFSET ( 0x0000013C )
10707
10708 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_OFFSET )
10709 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_ADDRESS ), (r) )
10710 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7_ADDRESS ), (v) )
10711
10712 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10713 typedef struct
10714 {
10715         /* rsv8 */
10716         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10717
10718         /* DSCP_O7 */
10719         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10720
10721         /* rsv7 */
10722         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10723
10724         /* DSCP_O6 */
10725         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10726
10727         /* rsv6 */
10728         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10729
10730         /* DSCP_O5 */
10731         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10732
10733         /* rsv5 */
10734         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10735
10736         /* DSCP_O4 */
10737         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10738
10739         /* rsv4 */
10740         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10741
10742         /* DSCP_O3 */
10743         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10744
10745         /* rsv3 */
10746         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10747
10748         /* DSCP_O2 */
10749         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10750
10751         /* rsv2 */
10752         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10753
10754         /* DSCP_O1 */
10755         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10756
10757         /* rsv1 */
10758         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10759
10760         /* DSCP_O0 */
10761         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10762 }
10763 __PACKING_ATTRIBUTE_STRUCT_END__
10764 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7 ;
10765 #else
10766 typedef struct
10767 {
10768         /* DSCP_O0 */
10769         uint32_t dscp_o0        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10770
10771         /* rsv1 */
10772         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10773
10774         /* DSCP_O1 */
10775         uint32_t dscp_o1        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10776
10777         /* rsv2 */
10778         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10779
10780         /* DSCP_O2 */
10781         uint32_t dscp_o2        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10782
10783         /* rsv3 */
10784         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10785
10786         /* DSCP_O3 */
10787         uint32_t dscp_o3        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10788
10789         /* rsv4 */
10790         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10791
10792         /* DSCP_O4 */
10793         uint32_t dscp_o4        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10794
10795         /* rsv5 */
10796         uint32_t rsv5           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10797
10798         /* DSCP_O5 */
10799         uint32_t dscp_o5        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10800
10801         /* rsv6 */
10802         uint32_t rsv6           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10803
10804         /* DSCP_O6 */
10805         uint32_t dscp_o6        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10806
10807         /* rsv7 */
10808         uint32_t rsv7           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10809
10810         /* DSCP_O7 */
10811         uint32_t dscp_o7        : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10812
10813         /* rsv8 */
10814         uint32_t rsv8           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10815 }
10816 __PACKING_ATTRIBUTE_STRUCT_END__
10817 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7 ;
10818 #endif
10819
10820 /*****************************************************************************************/
10821 /* DEFAULT_TCI_TBL0                                                                      */
10822 /* Default TCI Table 0.  Used for conversion in case of non-IP untagged packet           */
10823 /*****************************************************************************************/
10824
10825 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_RSV_RSV_VALUE                     ( 0x0 )
10826 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
10827 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_DEFAULT_TCI_TCI_VALUE             ( 0x0 )
10828 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_DEFAULT_TCI_TCI_VALUE_RESET_VALUE ( 0x0 )
10829
10830
10831 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_OFFSET ( 0x00000140 )
10832
10833 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_OFFSET )
10834 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_ADDRESS ), (r) )
10835 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0_ADDRESS ), (v) )
10836
10837 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10838 typedef struct
10839 {
10840         /* rsv */
10841         uint32_t rsv            : 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10842
10843         /* DEFAULT_TCI */
10844         uint32_t default_tci    : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10845 }
10846 __PACKING_ATTRIBUTE_STRUCT_END__
10847 IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0 ;
10848 #else
10849 typedef struct
10850 {
10851         /* DEFAULT_TCI */
10852         uint32_t default_tci    : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10853
10854         /* rsv */
10855         uint32_t rsv            : 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10856 }
10857 __PACKING_ATTRIBUTE_STRUCT_END__
10858 IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0 ;
10859 #endif
10860
10861 /*****************************************************************************************/
10862 /* DEFAULT_TCI_TBL1                                                                      */
10863 /* Default TCI Table 1.  Used for conversion in case of non-IP untagged packet           */
10864 /*****************************************************************************************/
10865
10866 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_RSV_RSV_VALUE                     ( 0x0 )
10867 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
10868 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_DEFAULT_TCI_TCI_VALUE             ( 0x0 )
10869 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_DEFAULT_TCI_TCI_VALUE_RESET_VALUE ( 0x0 )
10870
10871
10872 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_OFFSET ( 0x00000144 )
10873
10874 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_ADDRESS      ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_OFFSET )
10875 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_READ( r )    READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_ADDRESS ), (r) )
10876 #define IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_WRITE( v )   WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1_ADDRESS ), (v) )
10877
10878 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10879 typedef struct
10880 {
10881         /* rsv */
10882         uint32_t rsv            : 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10883
10884         /* DEFAULT_TCI */
10885         uint32_t default_tci    : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10886 }
10887 __PACKING_ATTRIBUTE_STRUCT_END__
10888 IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1 ;
10889 #else
10890 typedef struct
10891 {
10892         /* DEFAULT_TCI */
10893         uint32_t default_tci    : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10894
10895         /* rsv */
10896         uint32_t rsv            : 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10897 }
10898 __PACKING_ATTRIBUTE_STRUCT_END__
10899 IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1 ;
10900 #endif
10901
10902 /*****************************************************************************************/
10903 /* DSCP_TBL_VALID_CFG                                                                    */
10904 /* Valid configuration of DSCP Tables                                                    */
10905 /*****************************************************************************************/
10906
10907 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_RSV_FILTER_CONFIG_VALUE                ( 0x0 )
10908 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_RSV_FILTER_CONFIG_VALUE_RESET_VALUE    ( 0x0 )
10909 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL1_VALID_NON_VALID_VALUE             ( 0x0 )
10910 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL1_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
10911 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL1_VALID_VALID_VALUE                 ( 0x1 )
10912 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL0_VALID_NON_VALID_VALUE             ( 0x0 )
10913 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL0_VALID_NON_VALID_VALUE_RESET_VALUE ( 0x0 )
10914 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_TBL0_VALID_VALID_VALUE                 ( 0x1 )
10915
10916
10917 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_OFFSET ( 0x00000148 )
10918
10919 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_ADDRESS    ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_OFFSET )
10920 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_READ( r )  READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_ADDRESS ), (r) )
10921 #define IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_WRITE( v ) WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG_ADDRESS ), (v) )
10922
10923 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10924 typedef struct
10925 {
10926         /* rsv */
10927         uint32_t rsv            : 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10928
10929         /* TBL1_VALID */
10930         uint32_t tbl1_valid     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10931
10932         /* TBL0_VALID */
10933         uint32_t tbl0_valid     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10934 }
10935 __PACKING_ATTRIBUTE_STRUCT_END__
10936 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG ;
10937 #else
10938 typedef struct
10939 {
10940         /* TBL0_VALID */
10941         uint32_t tbl0_valid     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10942
10943         /* TBL1_VALID */
10944         uint32_t tbl1_valid     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10945
10946         /* rsv */
10947         uint32_t rsv            : 30 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10948 }
10949 __PACKING_ATTRIBUTE_STRUCT_END__
10950 IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG ;
10951 #endif
10952
10953 /*****************************************************************************************/
10954 /* DA_FILT6_VAL_L                                                                        */
10955 /* Config DA filter6 31:0                                                                */
10956 /*****************************************************************************************/
10957
10958 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
10959 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
10960
10961
10962 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_OFFSET ( 0x0000014C )
10963
10964 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_OFFSET )
10965 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_ADDRESS ), (r) )
10966 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L_ADDRESS ), (v) )
10967
10968 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
10969 typedef struct
10970 {
10971         /* DA_FILT_LSB */
10972         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10973 }
10974 __PACKING_ATTRIBUTE_STRUCT_END__
10975 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L ;
10976 #else
10977 typedef struct
10978 {
10979         /* DA_FILT_LSB */
10980         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
10981 }
10982 __PACKING_ATTRIBUTE_STRUCT_END__
10983 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L ;
10984 #endif
10985
10986 /*****************************************************************************************/
10987 /* DA_FILT6_VAL_H                                                                        */
10988 /* Config DA Filter6 47:32                                                               */
10989 /*****************************************************************************************/
10990
10991 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
10992 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
10993 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
10994 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
10995
10996
10997 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_OFFSET ( 0x00000150 )
10998
10999 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_OFFSET )
11000 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_ADDRESS ), (r) )
11001 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H_ADDRESS ), (v) )
11002
11003 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11004 typedef struct
11005 {
11006         /* rsv */
11007         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11008
11009         /* DA_FILT_MSB */
11010         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11011 }
11012 __PACKING_ATTRIBUTE_STRUCT_END__
11013 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H ;
11014 #else
11015 typedef struct
11016 {
11017         /* DA_FILT_MSB */
11018         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11019
11020         /* rsv */
11021         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11022 }
11023 __PACKING_ATTRIBUTE_STRUCT_END__
11024 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H ;
11025 #endif
11026
11027 /*****************************************************************************************/
11028 /* DA_FILT7_VAL_L                                                                        */
11029 /* Config DA filter7 31:0                                                                */
11030 /*****************************************************************************************/
11031
11032 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE             ( 0x0 )
11033 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_DA_FILT_LSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
11034
11035
11036 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_OFFSET ( 0x00000154 )
11037
11038 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_OFFSET )
11039 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_ADDRESS ), (r) )
11040 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L_ADDRESS ), (v) )
11041
11042 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11043 typedef struct
11044 {
11045         /* DA_FILT_LSB */
11046         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11047 }
11048 __PACKING_ATTRIBUTE_STRUCT_END__
11049 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L ;
11050 #else
11051 typedef struct
11052 {
11053         /* DA_FILT_LSB */
11054         uint32_t da_filt_lsb    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11055 }
11056 __PACKING_ATTRIBUTE_STRUCT_END__
11057 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L ;
11058 #endif
11059
11060 /*****************************************************************************************/
11061 /* DA_FILT7_VAL_H                                                                        */
11062 /* Config DA Filter7 47:32                                                               */
11063 /*****************************************************************************************/
11064
11065 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RSV_FILTER_CONFIG_VALUE                     ( 0x0 )
11066 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_RSV_FILTER_CONFIG_VALUE_RESET_VALUE         ( 0x0 )
11067 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE             ( 0x0 )
11068 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_DA_FILT_MSB_FILTER_CONFIG_VALUE_RESET_VALUE ( 0x0 )
11069
11070
11071 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_OFFSET ( 0x00000158 )
11072
11073 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_ADDRESS        ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_OFFSET )
11074 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_READ( r )      READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_ADDRESS ), (r) )
11075 #define IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_WRITE( v )     WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H_ADDRESS ), (v) )
11076
11077 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11078 typedef struct
11079 {
11080         /* rsv */
11081         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11082
11083         /* DA_FILT_MSB */
11084         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11085 }
11086 __PACKING_ATTRIBUTE_STRUCT_END__
11087 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H ;
11088 #else
11089 typedef struct
11090 {
11091         /* DA_FILT_MSB */
11092         uint32_t da_filt_msb    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11093
11094         /* rsv */
11095         uint32_t rsv            : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11096 }
11097 __PACKING_ATTRIBUTE_STRUCT_END__
11098 IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H ;
11099 #endif
11100
11101 /*****************************************************************************************/
11102 /* IPV6_HDR_EXT_FLTR_MASK_CFG                                                            */
11103 /* IPV6 Header Extension Filter Mask register                                            */
11104 /*****************************************************************************************/
11105
11106 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RSV_FILTER_CONFIG_VALUE                 ( 0x0 )
11107 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_RSV_FILTER_CONFIG_VALUE_RESET_VALUE     ( 0x0 )
11108 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_MASK_VALUE                  ( 0x0 )
11109 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_MASK_VALUE_RESET_VALUE      ( 0x0 )
11110 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_UNMASK_VALUE                ( 0x1 )
11111 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_MASK_VALUE                   ( 0x0 )
11112 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_MASK_VALUE_RESET_VALUE       ( 0x0 )
11113 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_UNMASK_VALUE                 ( 0x1 )
11114 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_MASK_VALUE             ( 0x0 )
11115 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_MASK_VALUE_RESET_VALUE ( 0x0 )
11116 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_UNMASK_VALUE           ( 0x1 )
11117
11118
11119 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_OFFSET ( 0x0000015C )
11120
11121 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ADDRESS    ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_OFFSET )
11122 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_READ( r )  READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ADDRESS ), (r) )
11123 #define IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_WRITE( v ) WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG_ADDRESS ), (v) )
11124
11125 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11126 typedef struct
11127 {
11128         /* rsv */
11129         uint32_t rsv                    : 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11130
11131         /* dest_opt_eh */
11132         uint32_t dest_opt_eh            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11133
11134         /* routing_eh */
11135         uint32_t routing_eh             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11136
11137         /* hop_by_hop_match */
11138         uint32_t hop_by_hop_match       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11139 }
11140 __PACKING_ATTRIBUTE_STRUCT_END__
11141 IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG ;
11142 #else
11143 typedef struct
11144 {
11145         /* hop_by_hop_match */
11146         uint32_t hop_by_hop_match       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11147
11148         /* routing_eh */
11149         uint32_t routing_eh             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11150
11151         /* dest_opt_eh */
11152         uint32_t dest_opt_eh            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11153
11154         /* rsv */
11155         uint32_t rsv                    : 29 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11156 }
11157 __PACKING_ATTRIBUTE_STRUCT_END__
11158 IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG ;
11159 #endif
11160
11161 /*****************************************************************************************/
11162 /* ENG                                                                                   */
11163 /* Engineering Configuration reserved for Broadlight use                                 */
11164 /*****************************************************************************************/
11165
11166 #define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_CFG_RESET_VALUE             ( 0x0 )
11167 #define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_CFG_RESET_VALUE_RESET_VALUE ( 0x0 )
11168
11169
11170 #define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_OFFSET ( 0x00000160 )
11171
11172 #define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_ADDRESS           ( IH_REGS_PARSER_CORE_CONFIGURATION_ADDRESS + IH_REGS_PARSER_CORE_CONFIGURATION_ENG_OFFSET )
11173 #define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_READ( r )         READ_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_ENG_ADDRESS ), (r) )
11174 #define IH_REGS_PARSER_CORE_CONFIGURATION_ENG_WRITE( v )        WRITE_32( ( IH_REGS_PARSER_CORE_CONFIGURATION_ENG_ADDRESS ), (v) )
11175
11176 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11177 typedef struct
11178 {
11179         /* CFG */
11180         uint32_t cfg    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11181 }
11182 __PACKING_ATTRIBUTE_STRUCT_END__
11183 IH_REGS_PARSER_CORE_CONFIGURATION_ENG ;
11184 #else
11185 typedef struct
11186 {
11187         /* CFG */
11188         uint32_t cfg    : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11189 }
11190 __PACKING_ATTRIBUTE_STRUCT_END__
11191 IH_REGS_PARSER_CORE_CONFIGURATION_ENG ;
11192 #endif
11193
11194 /*****************************************************************************************/
11195 /* SP2IQ_MAP_CFG                                                                         */
11196 /* Source Port mapping to IH Ingress Queue num, says per physical port to which IQ it be */
11197 /* longs (from 0 to 7)                                                                   */
11198 /*****************************************************************************************/
11199
11200 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRB_IQ_MAP_MAP_VALUE_VALUE             ( 0x7 )
11201 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRB_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x7 )
11202 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRA_IQ_MAP_MAP_VALUE_VALUE             ( 0x6 )
11203 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_RNRA_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x6 )
11204 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_GPON_IQ_MAP_MAP_VALUE_VALUE             ( 0x5 )
11205 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_GPON_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x5 )
11206 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH4_IQ_MAP_MAP_VALUE_VALUE             ( 0x4 )
11207 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH4_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x4 )
11208 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH3_IQ_MAP_MAP_VALUE_VALUE             ( 0x3 )
11209 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH3_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x3 )
11210 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH2_IQ_MAP_MAP_VALUE_VALUE             ( 0x2 )
11211 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH2_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x2 )
11212 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH1_IQ_MAP_MAP_VALUE_VALUE             ( 0x1 )
11213 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH1_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x1 )
11214 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH0_IQ_MAP_MAP_VALUE_VALUE             ( 0x0 )
11215 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ETH0_IQ_MAP_MAP_VALUE_VALUE_RESET_VALUE ( 0x0 )
11216
11217
11218 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_OFFSET ( 0x00000000 )
11219
11220 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_OFFSET )
11221 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ADDRESS ), (r) )
11222 #define IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG_ADDRESS ), (v) )
11223
11224 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11225 typedef struct
11226 {
11227         /* RNRB_IQ_MAP */
11228         uint32_t rnrb_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11229
11230         /* RNRA_IQ_MAP */
11231         uint32_t rnra_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11232
11233         /* GPON_IQ_MAP */
11234         uint32_t gpon_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11235
11236         /* ETH4_IQ_MAP */
11237         uint32_t eth4_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11238
11239         /* ETH3_IQ_MAP */
11240         uint32_t eth3_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11241
11242         /* ETH2_IQ_MAP */
11243         uint32_t eth2_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11244
11245         /* ETH1_IQ_MAP */
11246         uint32_t eth1_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11247
11248         /* ETH0_IQ_MAP */
11249         uint32_t eth0_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11250 }
11251 __PACKING_ATTRIBUTE_STRUCT_END__
11252 IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG ;
11253 #else
11254 typedef struct
11255 {
11256         /* ETH0_IQ_MAP */
11257         uint32_t eth0_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11258
11259         /* ETH1_IQ_MAP */
11260         uint32_t eth1_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11261
11262         /* ETH2_IQ_MAP */
11263         uint32_t eth2_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11264
11265         /* ETH3_IQ_MAP */
11266         uint32_t eth3_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11267
11268         /* ETH4_IQ_MAP */
11269         uint32_t eth4_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11270
11271         /* GPON_IQ_MAP */
11272         uint32_t gpon_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11273
11274         /* RNRA_IQ_MAP */
11275         uint32_t rnra_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11276
11277         /* RNRB_IQ_MAP */
11278         uint32_t rnrb_iq_map    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11279 }
11280 __PACKING_ATTRIBUTE_STRUCT_END__
11281 IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG ;
11282 #endif
11283
11284 /*****************************************************************************************/
11285 /* IQ_BASE_CFG                                                                           */
11286 /* Base location of each Ingres Queue in 16-entry IQ array.  Note: this configuration sh */
11287 /* ould be aligned with configuration of IQ size.    Default configuration of IQ array:  */
11288 /*    IQ#  Port   Num of Ingres Buffers  ==================================  0  : Eth0 : */
11289 /*     2   1  : Eth1 :    2   2  : Eth2 :    2   3  : Eth3 :    2   4  : Eth4 :    2  5  */
11290 /*  : GPON :    4  6  : RNRA :    1  7  : RNRB :    1                                    */
11291 /*****************************************************************************************/
11292
11293 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ7_BASE_BASE_VALUE_VALUE             ( 0xF )
11294 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ7_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0xF )
11295 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ6_BASE_BASE_VALUE_VALUE             ( 0xE )
11296 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ6_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0xE )
11297 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ5_BASE_BASE_VALUE_VALUE             ( 0xA )
11298 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ5_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0xA )
11299 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ4_BASE_BASE_VALUE_VALUE             ( 0x8 )
11300 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ4_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x8 )
11301 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ3_BASE_BASE_VALUE_VALUE             ( 0x6 )
11302 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ3_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x6 )
11303 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ2_BASE_BASE_VALUE_VALUE             ( 0x4 )
11304 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ2_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x4 )
11305 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ1_BASE_BASE_VALUE_VALUE             ( 0x2 )
11306 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ1_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x2 )
11307 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ0_BASE_BASE_VALUE_VALUE             ( 0x0 )
11308 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_IQ0_BASE_BASE_VALUE_VALUE_RESET_VALUE ( 0x0 )
11309
11310
11311 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_OFFSET ( 0x00000004 )
11312
11313 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_ADDRESS       ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_OFFSET )
11314 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_READ( r )     READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_ADDRESS ), (r) )
11315 #define IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_WRITE( v )    WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG_ADDRESS ), (v) )
11316
11317 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11318 typedef struct
11319 {
11320         /* IQ7_BASE */
11321         uint32_t iq7_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11322
11323         /* IQ6_BASE */
11324         uint32_t iq6_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11325
11326         /* IQ5_BASE */
11327         uint32_t iq5_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11328
11329         /* IQ4_BASE */
11330         uint32_t iq4_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11331
11332         /* IQ3_BASE */
11333         uint32_t iq3_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11334
11335         /* IQ2_BASE */
11336         uint32_t iq2_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11337
11338         /* IQ1_BASE */
11339         uint32_t iq1_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11340
11341         /* IQ0_BASE */
11342         uint32_t iq0_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11343 }
11344 __PACKING_ATTRIBUTE_STRUCT_END__
11345 IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG ;
11346 #else
11347 typedef struct
11348 {
11349         /* IQ0_BASE */
11350         uint32_t iq0_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11351
11352         /* IQ1_BASE */
11353         uint32_t iq1_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11354
11355         /* IQ2_BASE */
11356         uint32_t iq2_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11357
11358         /* IQ3_BASE */
11359         uint32_t iq3_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11360
11361         /* IQ4_BASE */
11362         uint32_t iq4_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11363
11364         /* IQ5_BASE */
11365         uint32_t iq5_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11366
11367         /* IQ6_BASE */
11368         uint32_t iq6_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11369
11370         /* IQ7_BASE */
11371         uint32_t iq7_base       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11372 }
11373 __PACKING_ATTRIBUTE_STRUCT_END__
11374 IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG ;
11375 #endif
11376
11377 /*****************************************************************************************/
11378 /* IQ_SIZE_CFG                                                                           */
11379 /* Size (= num of ingress buffers) per each Ingres Queue in 16-entry IQ array.    Note:  */
11380 /* this configuration should be aligned with configuration of IQ base.  Total num of ent */
11381 /* eties should be <= 16  Note: value 0x0 means that number of entries is sixteen!!    D */
11382 /* efault configuration of IQ array:    IQ#  Port   Num of Ingres Buffers  ============= */
11383 /* =====================  0  : Eth0 :    2   1  : Eth1 :    2   2  : Eth2 :    2   3  :  */
11384 /* Eth3 :    2   4  : Eth4 :    2  5  : GPON :    4  6  : RNRA :    1  7  : RNRB :    1  */
11385 /*                                                                                       */
11386 /*****************************************************************************************/
11387
11388 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ7_SIZE_SIZE_VALUE_VALUE             ( 0x1 )
11389 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ7_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x1 )
11390 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ6_SIZE_SIZE_VALUE_VALUE             ( 0x1 )
11391 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ6_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x1 )
11392 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ5_SIZE_SIZE_VALUE_VALUE             ( 0x4 )
11393 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ5_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x4 )
11394 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ4_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
11395 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ4_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
11396 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ3_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
11397 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ3_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
11398 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ2_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
11399 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ2_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
11400 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ1_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
11401 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ1_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
11402 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ0_SIZE_SIZE_VALUE_VALUE             ( 0x2 )
11403 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_IQ0_SIZE_SIZE_VALUE_VALUE_RESET_VALUE ( 0x2 )
11404
11405
11406 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_OFFSET ( 0x00000008 )
11407
11408 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_ADDRESS       ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_OFFSET )
11409 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_READ( r )     READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_ADDRESS ), (r) )
11410 #define IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_WRITE( v )    WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG_ADDRESS ), (v) )
11411
11412 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11413 typedef struct
11414 {
11415         /* IQ7_SIZE */
11416         uint32_t iq7_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11417
11418         /* IQ6_SIZE */
11419         uint32_t iq6_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11420
11421         /* IQ5_SIZE */
11422         uint32_t iq5_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11423
11424         /* IQ4_SIZE */
11425         uint32_t iq4_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11426
11427         /* IQ3_SIZE */
11428         uint32_t iq3_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11429
11430         /* IQ2_SIZE */
11431         uint32_t iq2_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11432
11433         /* IQ1_SIZE */
11434         uint32_t iq1_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11435
11436         /* IQ0_SIZE */
11437         uint32_t iq0_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11438 }
11439 __PACKING_ATTRIBUTE_STRUCT_END__
11440 IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG ;
11441 #else
11442 typedef struct
11443 {
11444         /* IQ0_SIZE */
11445         uint32_t iq0_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11446
11447         /* IQ1_SIZE */
11448         uint32_t iq1_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11449
11450         /* IQ2_SIZE */
11451         uint32_t iq2_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11452
11453         /* IQ3_SIZE */
11454         uint32_t iq3_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11455
11456         /* IQ4_SIZE */
11457         uint32_t iq4_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11458
11459         /* IQ5_SIZE */
11460         uint32_t iq5_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11461
11462         /* IQ6_SIZE */
11463         uint32_t iq6_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11464
11465         /* IQ7_SIZE */
11466         uint32_t iq7_size       : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11467 }
11468 __PACKING_ATTRIBUTE_STRUCT_END__
11469 IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG ;
11470 #endif
11471
11472 /*****************************************************************************************/
11473 /* IQL_PRIOR_CFG                                                                         */
11474 /* Priority of each Ingres Queues [3...0].    Note: this configuration defined by one ho */
11475 /* t (8 bits max)    Default configuration of IQ array:    IQ#  Port   Priority  ======= */
11476 /* ===========================  0  : Eth0 :    8b010   1  : Eth1 :    8b010   2  : Eth2  */
11477 /* :    8b010   3  : Eth3 :    8b010   4  : Eth4 :    8b010  5  : GPON :    8b100  6  :  */
11478 /* RNRA :    8b001  7  : RNRB :    8b001                                                 */
11479 /*****************************************************************************************/
11480
11481 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ3_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
11482 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ3_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
11483 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ2_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
11484 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ2_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
11485 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ1_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
11486 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ1_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
11487 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ0_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
11488 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_IQ0_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
11489
11490
11491 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_OFFSET ( 0x0000000C )
11492
11493 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_OFFSET )
11494 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_ADDRESS ), (r) )
11495 #define IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG_ADDRESS ), (v) )
11496
11497 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11498 typedef struct
11499 {
11500         /* IQ3_PRIOR */
11501         uint32_t iq3_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11502
11503         /* IQ2_PRIOR */
11504         uint32_t iq2_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11505
11506         /* IQ1_PRIOR */
11507         uint32_t iq1_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11508
11509         /* IQ0_PRIOR */
11510         uint32_t iq0_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11511 }
11512 __PACKING_ATTRIBUTE_STRUCT_END__
11513 IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG ;
11514 #else
11515 typedef struct
11516 {
11517         /* IQ0_PRIOR */
11518         uint32_t iq0_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11519
11520         /* IQ1_PRIOR */
11521         uint32_t iq1_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11522
11523         /* IQ2_PRIOR */
11524         uint32_t iq2_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11525
11526         /* IQ3_PRIOR */
11527         uint32_t iq3_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11528 }
11529 __PACKING_ATTRIBUTE_STRUCT_END__
11530 IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG ;
11531 #endif
11532
11533 /*****************************************************************************************/
11534 /* IQH_PRIOR_CFG                                                                         */
11535 /* Priority of each Ingres Queues [7...4].    Note: this configuration defined by one ho */
11536 /* t (8 bits max)    Default configuration of IQ array:    IQ#  Port   Priority  ======= */
11537 /* ===========================  0  : Eth0 :    8b010   1  : Eth1 :    8b010   2  : Eth2  */
11538 /* :    8b010   3  : Eth3 :    8b010   4  : Eth4 :    8b010  5  : GPON :    8b100  6  :  */
11539 /* RNRA :    8b001  7  : RNRB :    8b001                                                 */
11540 /*****************************************************************************************/
11541
11542 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ7_PRIOR_PRIOR_VALUE_VALUE             ( 0x1 )
11543 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ7_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x1 )
11544 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ6_PRIOR_PRIOR_VALUE_VALUE             ( 0x1 )
11545 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ6_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x1 )
11546 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ5_PRIOR_PRIOR_VALUE_VALUE             ( 0x4 )
11547 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ5_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x4 )
11548 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ4_PRIOR_PRIOR_VALUE_VALUE             ( 0x2 )
11549 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_IQ4_PRIOR_PRIOR_VALUE_VALUE_RESET_VALUE ( 0x2 )
11550
11551
11552 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_OFFSET ( 0x00000010 )
11553
11554 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_OFFSET )
11555 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_ADDRESS ), (r) )
11556 #define IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG_ADDRESS ), (v) )
11557
11558 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11559 typedef struct
11560 {
11561         /* IQ7_PRIOR */
11562         uint32_t iq7_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11563
11564         /* IQ6_PRIOR */
11565         uint32_t iq6_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11566
11567         /* IQ5_PRIOR */
11568         uint32_t iq5_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11569
11570         /* IQ4_PRIOR */
11571         uint32_t iq4_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11572 }
11573 __PACKING_ATTRIBUTE_STRUCT_END__
11574 IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG ;
11575 #else
11576 typedef struct
11577 {
11578         /* IQ4_PRIOR */
11579         uint32_t iq4_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11580
11581         /* IQ5_PRIOR */
11582         uint32_t iq5_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11583
11584         /* IQ6_PRIOR */
11585         uint32_t iq6_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11586
11587         /* IQ7_PRIOR */
11588         uint32_t iq7_prior      : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11589 }
11590 __PACKING_ATTRIBUTE_STRUCT_END__
11591 IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG ;
11592 #endif
11593
11594 /*****************************************************************************************/
11595 /* PHL_OFFSET_CFG                                                                        */
11596 /* Packet Header offset per Ingres Physical port in byte resolution    Note: this config */
11597 /* uration says where the Header of packet is started. This configuration is used both b */
11598 /* y Parser and by Egress Queue DMA. The motivation: store room in the beginning of Runn */
11599 /* er Buffer for FW    Default configuration of Packet Header offset is 0x0.             */
11600 /*****************************************************************************************/
11601
11602 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV4_RSV_VALUE                                   ( 0x0 )
11603 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV4_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11604 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH3_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11605 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH3_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11606 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV3_RSV_VALUE                                   ( 0x0 )
11607 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV3_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11608 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH2_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11609 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH2_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11610 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV2_RSV_VALUE                                   ( 0x0 )
11611 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV2_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11612 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH1_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11613 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH1_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11614 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV1_RSV_VALUE                                   ( 0x0 )
11615 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_RSV1_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11616 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH0_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11617 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ETH0_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11618
11619
11620 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_OFFSET ( 0x00000014 )
11621
11622 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_OFFSET )
11623 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ADDRESS ), (r) )
11624 #define IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG_ADDRESS ), (v) )
11625
11626 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11627 typedef struct
11628 {
11629         /* RSV4 */
11630         uint32_t rsv4           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11631
11632         /* ETH3_PH_OFFSET */
11633         uint32_t eth3_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11634
11635         /* RSV3 */
11636         uint32_t rsv3           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11637
11638         /* ETH2_PH_OFFSET */
11639         uint32_t eth2_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11640
11641         /* RSV2 */
11642         uint32_t rsv2           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11643
11644         /* ETH1_PH_OFFSET */
11645         uint32_t eth1_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11646
11647         /* RSV1 */
11648         uint32_t rsv1           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11649
11650         /* ETH0_PH_OFFSET */
11651         uint32_t eth0_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11652 }
11653 __PACKING_ATTRIBUTE_STRUCT_END__
11654 IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG ;
11655 #else
11656 typedef struct
11657 {
11658         /* ETH0_PH_OFFSET */
11659         uint32_t eth0_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11660
11661         /* RSV1 */
11662         uint32_t rsv1           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11663
11664         /* ETH1_PH_OFFSET */
11665         uint32_t eth1_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11666
11667         /* RSV2 */
11668         uint32_t rsv2           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11669
11670         /* ETH2_PH_OFFSET */
11671         uint32_t eth2_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11672
11673         /* RSV3 */
11674         uint32_t rsv3           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11675
11676         /* ETH3_PH_OFFSET */
11677         uint32_t eth3_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11678
11679         /* RSV4 */
11680         uint32_t rsv4           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11681 }
11682 __PACKING_ATTRIBUTE_STRUCT_END__
11683 IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG ;
11684 #endif
11685
11686 /*****************************************************************************************/
11687 /* PHH_OFFSET_CFG                                                                        */
11688 /* Packet Header offset per Ingres Physical port in byte resolution    Note: this config */
11689 /* uration says where the Header of packet is started. This configuration is used both b */
11690 /* y Parser and by Egress Queue DMA. The motivation: store room in the beginning of Runn */
11691 /* er Buffer for FW    Default configuration of Packet Header offset is 0x0.             */
11692 /*****************************************************************************************/
11693
11694 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV4_RSV_VALUE                                   ( 0x0 )
11695 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV4_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11696 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRB_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11697 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRB_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11698 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV3_RSV_VALUE                                   ( 0x0 )
11699 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV3_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11700 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRA_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11701 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RNRA_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11702 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV2_RSV_VALUE                                   ( 0x0 )
11703 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV2_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11704 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_GPON_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11705 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_GPON_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11706 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV1_RSV_VALUE                                   ( 0x0 )
11707 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_RSV1_RSV_VALUE_RESET_VALUE                       ( 0x0 )
11708 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ETH4_PH_OFFSET_PH_OFFSET_VALUE_VALUE             ( 0x0 )
11709 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ETH4_PH_OFFSET_PH_OFFSET_VALUE_VALUE_RESET_VALUE ( 0x0 )
11710
11711
11712 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_OFFSET ( 0x00000018 )
11713
11714 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_OFFSET )
11715 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ADDRESS ), (r) )
11716 #define IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG_ADDRESS ), (v) )
11717
11718 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11719 typedef struct
11720 {
11721         /* RSV4 */
11722         uint32_t rsv4           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11723
11724         /* RNRB_PH_OFFSET */
11725         uint32_t rnrb_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11726
11727         /* RSV3 */
11728         uint32_t rsv3           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11729
11730         /* RNRA_PH_OFFSET */
11731         uint32_t rnra_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11732
11733         /* RSV2 */
11734         uint32_t rsv2           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11735
11736         /* GPON_PH_OFFSET */
11737         uint32_t gpon_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11738
11739         /* RSV1 */
11740         uint32_t rsv1           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11741
11742         /* ETH4_PH_OFFSET */
11743         uint32_t eth4_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11744 }
11745 __PACKING_ATTRIBUTE_STRUCT_END__
11746 IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG ;
11747 #else
11748 typedef struct
11749 {
11750         /* ETH4_PH_OFFSET */
11751         uint32_t eth4_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11752
11753         /* RSV1 */
11754         uint32_t rsv1           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11755
11756         /* GPON_PH_OFFSET */
11757         uint32_t gpon_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11758
11759         /* RSV2 */
11760         uint32_t rsv2           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11761
11762         /* RNRA_PH_OFFSET */
11763         uint32_t rnra_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11764
11765         /* RSV3 */
11766         uint32_t rsv3           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11767
11768         /* RNRB_PH_OFFSET */
11769         uint32_t rnrb_ph_offset : 6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11770
11771         /* RSV4 */
11772         uint32_t rsv4           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11773 }
11774 __PACKING_ATTRIBUTE_STRUCT_END__
11775 IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG ;
11776 #endif
11777
11778 /*****************************************************************************************/
11779 /* IQ_WEIGHT_CFG                                                                         */
11780 /* Weight Arbiration of each Ingres Queue     Note: this configuration has a meaning oly */
11781 /*  for two or more  queus with the same priority     Default configuration of IQ array: */
11782 /*     IQ#  Port   Weight  ==================================  0  : Eth0 :    1   1  : E */
11783 /* th1 :    1   2  : Eth2 :    1   3  : Eth3 :    1   4  : Eth4 :    1  5  : GPON :    1 */
11784 /*   6  : RNRA :    1  7  : RNRB :    1                                                  */
11785 /*****************************************************************************************/
11786
11787 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ7_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11788 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ7_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11789 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ6_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11790 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ6_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11791 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ5_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11792 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ5_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11793 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ4_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11794 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ4_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11795 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ3_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11796 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ3_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11797 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ2_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11798 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ2_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11799 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ1_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11800 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ1_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11801 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ0_WEIGHT_WEIGHT_VALUE_VALUE             ( 0x1 )
11802 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_IQ0_WEIGHT_WEIGHT_VALUE_VALUE_RESET_VALUE ( 0x1 )
11803
11804
11805 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_OFFSET ( 0x00000020 )
11806
11807 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_OFFSET )
11808 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_ADDRESS ), (r) )
11809 #define IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG_ADDRESS ), (v) )
11810
11811 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11812 typedef struct
11813 {
11814         /* IQ7_WEIGHT */
11815         uint32_t iq7_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11816
11817         /* IQ6_WEIGHT */
11818         uint32_t iq6_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11819
11820         /* IQ5_WEIGHT */
11821         uint32_t iq5_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11822
11823         /* IQ4_WEIGHT */
11824         uint32_t iq4_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11825
11826         /* IQ3_WEIGHT */
11827         uint32_t iq3_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11828
11829         /* IQ2_WEIGHT */
11830         uint32_t iq2_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11831
11832         /* IQ1_WEIGHT */
11833         uint32_t iq1_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11834
11835         /* IQ0_WEIGHT */
11836         uint32_t iq0_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11837 }
11838 __PACKING_ATTRIBUTE_STRUCT_END__
11839 IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG ;
11840 #else
11841 typedef struct
11842 {
11843         /* IQ0_WEIGHT */
11844         uint32_t iq0_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11845
11846         /* IQ1_WEIGHT */
11847         uint32_t iq1_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11848
11849         /* IQ2_WEIGHT */
11850         uint32_t iq2_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11851
11852         /* IQ3_WEIGHT */
11853         uint32_t iq3_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11854
11855         /* IQ4_WEIGHT */
11856         uint32_t iq4_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11857
11858         /* IQ5_WEIGHT */
11859         uint32_t iq5_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11860
11861         /* IQ6_WEIGHT */
11862         uint32_t iq6_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11863
11864         /* IQ7_WEIGHT */
11865         uint32_t iq7_weight     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11866 }
11867 __PACKING_ATTRIBUTE_STRUCT_END__
11868 IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG ;
11869 #endif
11870
11871 /*****************************************************************************************/
11872 /* IQL_CNGS_THRS_CFG                                                                     */
11873 /* Ingres  congestion threshold of Low Ingres Queues[ 3...0].     When the number of tot */
11874 /* al Runner Buffers (eigher Runner A or Runner B) reachs the defined threshold per queu */
11875 /* e  - Ingres Handler stops serving this queue till one of two events will occur:  (1)  */
11876 /* num of Runner buffers is decreased down to threshold  (2) one of BBH clients that ass */
11877 /* igned to the queue will get Service Enable message initiated in appropriate MAC (by r */
11878 /* eaching predefined threshold in Data FIFO).    Note: this configuration should be ali */
11879 /* gned with a threshold of max runner buffers (per each Runner)    Default configuratio */
11880 /* n of IQ array (always allow servecing, do not stop on ingress congestion):    IQ#  Po */
11881 /* rt   Priority  ==================================  0  : Eth0 :   32   1  : Eth1 :   3 */
11882 /* 2    2  : Eth2 :   32    3  : Eth3 :   32    4  : Eth4 :   32   5  : GPON :   32   6  */
11883 /*  : RNRA :   32   7  : RNRB :   32                                                     */
11884 /*****************************************************************************************/
11885
11886 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV4_RSV_VALUE                                  ( 0x0 )
11887 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV4_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11888 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ3_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
11889 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ3_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
11890 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV3_RSV_VALUE                                  ( 0x0 )
11891 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV3_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11892 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ2_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
11893 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ2_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
11894 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV2_RSV_VALUE                                  ( 0x0 )
11895 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV2_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11896 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ1_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
11897 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ1_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
11898 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV1_RSV_VALUE                                  ( 0x0 )
11899 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_RSV1_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11900 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ0_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
11901 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_IQ0_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
11902
11903
11904 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_OFFSET ( 0x00000024 )
11905
11906 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_ADDRESS         ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_OFFSET )
11907 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_READ( r )       READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_ADDRESS ), (r) )
11908 #define IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_WRITE( v )      WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG_ADDRESS ), (v) )
11909
11910 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
11911 typedef struct
11912 {
11913         /* RSV4 */
11914         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11915
11916         /* IQ3_CNGS_THRS */
11917         uint32_t iq3_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11918
11919         /* RSV3 */
11920         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11921
11922         /* IQ2_CNGS_THRS */
11923         uint32_t iq2_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11924
11925         /* RSV2 */
11926         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11927
11928         /* IQ1_CNGS_THRS */
11929         uint32_t iq1_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11930
11931         /* rsv1 */
11932         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11933
11934         /* IQ0_CNGS_THRS */
11935         uint32_t iq0_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11936 }
11937 __PACKING_ATTRIBUTE_STRUCT_END__
11938 IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG ;
11939 #else
11940 typedef struct
11941 {
11942         /* IQ0_CNGS_THRS */
11943         uint32_t iq0_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11944
11945         /* rsv1 */
11946         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11947
11948         /* IQ1_CNGS_THRS */
11949         uint32_t iq1_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11950
11951         /* RSV2 */
11952         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11953
11954         /* IQ2_CNGS_THRS */
11955         uint32_t iq2_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11956
11957         /* RSV3 */
11958         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11959
11960         /* IQ3_CNGS_THRS */
11961         uint32_t iq3_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11962
11963         /* RSV4 */
11964         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
11965 }
11966 __PACKING_ATTRIBUTE_STRUCT_END__
11967 IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG ;
11968 #endif
11969
11970 /*****************************************************************************************/
11971 /* IQH_CNGS_THRS_CFG                                                                     */
11972 /* Ingres  congestion threshold of Low Ingres Queues[ 7...4].     When the number of tot */
11973 /* al Runner Buffers (eigher Runner A or Runner B) reachs the defined threshold per queu */
11974 /* e  - Ingres Handler stops serving this queue till one of two events will occur:  (1)  */
11975 /* num of Runner buffers is decreased down to threshold  (2) one of BBH clients that ass */
11976 /* igned to the queue will get Service Enable message initiated in appropriate MAC (by r */
11977 /* eaching predefined threshold in Data FIFO).    Note: this configuration should be ali */
11978 /* gned with a threshold of max runner buffers (per each Runner)    Default configuratio */
11979 /* n of IQ array (always allow servecing, do not stop on ingress congestion):    IQ#  Po */
11980 /* rt   Priority  ==================================  0  : Eth0 :   32   1  : Eth1 :   3 */
11981 /* 2    2  : Eth2 :   32    3  : Eth3 :   32    4  : Eth4 :   32   5  : GPON :   32   6  */
11982 /*  : RNRA :   32   7  : RNRB :   32                                                     */
11983 /*****************************************************************************************/
11984
11985 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV4_RSV_VALUE                                  ( 0x0 )
11986 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV4_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11987 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ7_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
11988 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ7_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
11989 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV3_RSV_VALUE                                  ( 0x0 )
11990 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV3_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11991 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ6_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
11992 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ6_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
11993 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV2_RSV_VALUE                                  ( 0x0 )
11994 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV2_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11995 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ5_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
11996 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ5_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
11997 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV1_RSV_VALUE                                  ( 0x0 )
11998 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_RSV1_RSV_VALUE_RESET_VALUE                      ( 0x0 )
11999 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ4_CNGS_THRS_CNGS_THRS_VALUE_VALUE             ( 0x40 )
12000 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_IQ4_CNGS_THRS_CNGS_THRS_VALUE_VALUE_RESET_VALUE ( 0x40 )
12001
12002
12003 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_OFFSET ( 0x00000028 )
12004
12005 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_ADDRESS         ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_OFFSET )
12006 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_READ( r )       READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_ADDRESS ), (r) )
12007 #define IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_WRITE( v )      WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG_ADDRESS ), (v) )
12008
12009 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12010 typedef struct
12011 {
12012         /* RSV4 */
12013         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12014
12015         /* IQ7_CNGS_THRS */
12016         uint32_t iq7_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12017
12018         /* RSV3 */
12019         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12020
12021         /* IQ6_CNGS_THRS */
12022         uint32_t iq6_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12023
12024         /* RSV2 */
12025         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12026
12027         /* IQ5_CNGS_THRS */
12028         uint32_t iq5_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12029
12030         /* rsv1 */
12031         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12032
12033         /* IQ4_CNGS_THRS */
12034         uint32_t iq4_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12035 }
12036 __PACKING_ATTRIBUTE_STRUCT_END__
12037 IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG ;
12038 #else
12039 typedef struct
12040 {
12041         /* IQ4_CNGS_THRS */
12042         uint32_t iq4_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12043
12044         /* rsv1 */
12045         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12046
12047         /* IQ5_CNGS_THRS */
12048         uint32_t iq5_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12049
12050         /* RSV2 */
12051         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12052
12053         /* IQ6_CNGS_THRS */
12054         uint32_t iq6_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12055
12056         /* RSV3 */
12057         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12058
12059         /* IQ7_CNGS_THRS */
12060         uint32_t iq7_cngs_thrs  : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12061
12062         /* RSV4 */
12063         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12064 }
12065 __PACKING_ATTRIBUTE_STRUCT_END__
12066 IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG ;
12067 #endif
12068
12069 /*****************************************************************************************/
12070 /* RNRA_RB_BASE                                                                          */
12071 /* Base Address of Runner Buffers sending for Runner A     The major part of Runner Buff */
12072 /* ers are managed by Ingres Handler per Runner.  The number of Runner Buffers is define */
12073 /* d per Runner, max number of managed buffers is 64; default is 32    However there are */
12074 /*  assigned Runner Buffers managed by Runner itself (FW pipe), the number of assigned n */
12075 /* on-managed Runner Buffer is up to FW control(up to 4 RIBs)  The base address of assig */
12076 /* ned buffers is different from the common managed buffers.    Each Runner Buffer has o */
12077 /* ffset of 0x32 according to its on number.     Note: Default configuration of base add */
12078 /* ress is 0x0.                                                                          */
12079 /*****************************************************************************************/
12080
12081 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE             ( 0x0 )
12082 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
12083 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE              ( 0x0 )
12084 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_RNRA_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE  ( 0x0 )
12085
12086
12087 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_OFFSET ( 0x00000030 )
12088
12089 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_OFFSET )
12090 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_ADDRESS ), (r) )
12091 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE_ADDRESS ), (v) )
12092
12093 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12094 typedef struct
12095 {
12096         /* RNRA_ASIGNED_RB_BASE */
12097         uint32_t rnra_asigned_rb_base   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12098
12099         /* RNRA_COMMON_RB_BASE */
12100         uint32_t rnra_common_rb_base    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12101 }
12102 __PACKING_ATTRIBUTE_STRUCT_END__
12103 IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE ;
12104 #else
12105 typedef struct
12106 {
12107         /* RNRA_COMMON_RB_BASE */
12108         uint32_t rnra_common_rb_base    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12109
12110         /* RNRA_ASIGNED_RB_BASE */
12111         uint32_t rnra_asigned_rb_base   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12112 }
12113 __PACKING_ATTRIBUTE_STRUCT_END__
12114 IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE ;
12115 #endif
12116
12117 /*****************************************************************************************/
12118 /* RNRB_RB_BASE                                                                          */
12119 /* Base Address of Runner Buffers sending for Runner B     The major part of Runner Buff */
12120 /* ers are managed by Ingres Handler per Runner.  The number of Runner Buffers is define */
12121 /* d per Runner, max number of managed buffers is 64; default is 32    However there are */
12122 /*  assigned Runner Buffers managed by Runner itself (FW pipe), the number of assigned n */
12123 /* on-managed Runner Buffer is up to FW control(up to 4 RIBs)  The base address of assig */
12124 /* ned buffers is different from the common managed buffers.    Each Runner Buffer has o */
12125 /* ffset of 0x32 according to its on number.     Note: Default configuration of base add */
12126 /* ress is 0x0.                                                                          */
12127 /*****************************************************************************************/
12128
12129 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE             ( 0x0 )
12130 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_ASIGNED_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
12131 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE              ( 0x0 )
12132 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_RNRB_COMMON_RB_BASE_BASE_ADDRESS_OFFSET_VALUE_RESET_VALUE  ( 0x0 )
12133
12134
12135 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_OFFSET ( 0x00000034 )
12136
12137 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_OFFSET )
12138 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_ADDRESS ), (r) )
12139 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE_ADDRESS ), (v) )
12140
12141 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12142 typedef struct
12143 {
12144         /* RNRB_ASIGNED_RB_BASE */
12145         uint32_t rnrb_asigned_rb_base   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12146
12147         /* RNRB_COMMON_RB_BASE */
12148         uint32_t rnrb_common_rb_base    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12149 }
12150 __PACKING_ATTRIBUTE_STRUCT_END__
12151 IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE ;
12152 #else
12153 typedef struct
12154 {
12155         /* RNRB_COMMON_RB_BASE */
12156         uint32_t rnrb_common_rb_base    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12157
12158         /* RNRB_ASIGNED_RB_BASE */
12159         uint32_t rnrb_asigned_rb_base   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12160 }
12161 __PACKING_ATTRIBUTE_STRUCT_END__
12162 IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE ;
12163 #endif
12164
12165 /*****************************************************************************************/
12166 /* RNRA_IHRSP_ADDR                                                                       */
12167 /* Address of IH response for Runner A     The content of IH Response is defined in chap */
12168 /* ter 3.1.3.15 in strpublicLilacArchTMIHmicro_archLilac_IH_LLD_v0.5.doc                 */
12169 /*****************************************************************************************/
12170
12171 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RSV_RSV_VALUE                                    ( 0x0 )
12172 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
12173 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RNRA_IHRSP_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
12174 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_RNRA_IHRSP_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
12175
12176
12177 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_OFFSET ( 0x00000038 )
12178
12179 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_OFFSET )
12180 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_ADDRESS ), (r) )
12181 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR_ADDRESS ), (v) )
12182
12183 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12184 typedef struct
12185 {
12186         /* rsv */
12187         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12188
12189         /* RNRA_IHRSP_ADDR */
12190         uint32_t rnra_ihrsp_addr        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12191 }
12192 __PACKING_ATTRIBUTE_STRUCT_END__
12193 IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR ;
12194 #else
12195 typedef struct
12196 {
12197         /* RNRA_IHRSP_ADDR */
12198         uint32_t rnra_ihrsp_addr        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12199
12200         /* rsv */
12201         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12202 }
12203 __PACKING_ATTRIBUTE_STRUCT_END__
12204 IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR ;
12205 #endif
12206
12207 /*****************************************************************************************/
12208 /* RNRB_IHRSP_ADDR                                                                       */
12209 /* Address of IH response for Runner B     The content of IH Response is defined in chap */
12210 /* ter 3.1.3.15 in strpublicLilacArchTMIHmicro_archLilac_IH_LLD_v0.5.doc                 */
12211 /*****************************************************************************************/
12212
12213 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RSV_RSV_VALUE                                    ( 0x0 )
12214 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
12215 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RNRB_IHRSP_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
12216 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_RNRB_IHRSP_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
12217
12218
12219 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_OFFSET ( 0x0000003C )
12220
12221 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_OFFSET )
12222 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_ADDRESS ), (r) )
12223 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR_ADDRESS ), (v) )
12224
12225 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12226 typedef struct
12227 {
12228         /* rsv */
12229         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12230
12231         /* RNRB_IHRSP_ADDR */
12232         uint32_t rnrb_ihrsp_addr        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12233 }
12234 __PACKING_ATTRIBUTE_STRUCT_END__
12235 IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR ;
12236 #else
12237 typedef struct
12238 {
12239         /* RNRB_IHRSP_ADDR */
12240         uint32_t rnrb_ihrsp_addr        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12241
12242         /* rsv */
12243         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12244 }
12245 __PACKING_ATTRIBUTE_STRUCT_END__
12246 IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR ;
12247 #endif
12248
12249 /*****************************************************************************************/
12250 /* RNRA_CNGS_RPT_ADDR                                                                    */
12251 /* Address of IH congestion report for Runner A     IH sends the total number of the Run */
12252 /* ner when the congestion state is changed.    Default address is 0x0                   */
12253 /*****************************************************************************************/
12254
12255 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RSV_RSV_VALUE                                       ( 0x0 )
12256 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RSV_RSV_VALUE_RESET_VALUE                           ( 0x0 )
12257 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RNRA_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
12258 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_RNRA_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
12259
12260
12261 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_OFFSET ( 0x00000040 )
12262
12263 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_OFFSET )
12264 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_ADDRESS ), (r) )
12265 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR_ADDRESS ), (v) )
12266
12267 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12268 typedef struct
12269 {
12270         /* rsv */
12271         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12272
12273         /* RNRA_CNGS_RPT_ADDR */
12274         uint32_t rnra_cngs_rpt_addr     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12275 }
12276 __PACKING_ATTRIBUTE_STRUCT_END__
12277 IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR ;
12278 #else
12279 typedef struct
12280 {
12281         /* RNRA_CNGS_RPT_ADDR */
12282         uint32_t rnra_cngs_rpt_addr     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12283
12284         /* rsv */
12285         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12286 }
12287 __PACKING_ATTRIBUTE_STRUCT_END__
12288 IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR ;
12289 #endif
12290
12291 /*****************************************************************************************/
12292 /* RNRB_CNGS_RPT_ADDR                                                                    */
12293 /* Address of IH congestion report for Runner B     IH sends the total number of the Run */
12294 /* ner when the congestion state is changed.    Default address is 0x0                   */
12295 /*****************************************************************************************/
12296
12297 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RSV_RSV_VALUE                                       ( 0x0 )
12298 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RSV_RSV_VALUE_RESET_VALUE                           ( 0x0 )
12299 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RNRB_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE             ( 0x0 )
12300 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_RNRB_CNGS_RPT_ADDR_ADDRESS_OFFSET_VALUE_RESET_VALUE ( 0x0 )
12301
12302
12303 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_OFFSET ( 0x00000044 )
12304
12305 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_OFFSET )
12306 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_ADDRESS ), (r) )
12307 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR_ADDRESS ), (v) )
12308
12309 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12310 typedef struct
12311 {
12312         /* rsv */
12313         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12314
12315         /* RNRB_CNGS_RPT_ADDR */
12316         uint32_t rnrb_cngs_rpt_addr     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12317 }
12318 __PACKING_ATTRIBUTE_STRUCT_END__
12319 IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR ;
12320 #else
12321 typedef struct
12322 {
12323         /* RNRB_CNGS_RPT_ADDR */
12324         uint32_t rnrb_cngs_rpt_addr     : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12325
12326         /* rsv */
12327         uint32_t rsv                    : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12328 }
12329 __PACKING_ATTRIBUTE_STRUCT_END__
12330 IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR ;
12331 #endif
12332
12333 /*****************************************************************************************/
12334 /* RNR_CNGS_RPT_CFG                                                                      */
12335 /* Enable of sending Congestion Report per each Runner.    IH sends the total number of  */
12336 /* the Runner when the congestion state is changed. The sending of this report is upon t */
12337 /* o enabled per Runner.    Default address is 0x0 (not to send report)                  */
12338 /*****************************************************************************************/
12339
12340 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_THRESHOLD_DISABLE_DIS_CNGS_RPT_SEND_VALUE             ( 0x0 )
12341 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_THRESHOLD_DISABLE_DIS_CNGS_RPT_SEND_VALUE_RESET_VALUE ( 0x0 )
12342 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_THRESHOLD_DISABLE_EN_CNGS_RPT_SEND_VALUE              ( 0x1 )
12343 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RSV_RSV_VALUE                                         ( 0x0 )
12344 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RSV_RSV_VALUE_RESET_VALUE                             ( 0x0 )
12345 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRB_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE              ( 0x0 )
12346 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRB_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE_RESET_VALUE  ( 0x0 )
12347 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRB_CNGS_RPT_EN_EN_CNGS_RPT_SEND_VALUE               ( 0x1 )
12348 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRA_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE              ( 0x0 )
12349 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRA_CNGS_RPT_EN_DIS_CNGS_RPT_SEND_VALUE_RESET_VALUE  ( 0x0 )
12350 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_RNRA_CNGS_RPT_EN_EN_CNGS_RPT_SEND_VALUE               ( 0x1 )
12351
12352
12353 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_OFFSET ( 0x00000048 )
12354
12355 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_OFFSET )
12356 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_ADDRESS ), (r) )
12357 #define IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG_ADDRESS ), (v) )
12358
12359 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12360 typedef struct
12361 {
12362         /* THRESHOLD_DISABLE */
12363         uint32_t threshold_disable      : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12364
12365         /* rsv */
12366         uint32_t rsv                    : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12367
12368         /* RNRB_CNGS_RPT_EN */
12369         uint32_t rnrb_cngs_rpt_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12370
12371         /* RNRA_CNGS_RPT_EN */
12372         uint32_t rnra_cngs_rpt_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12373 }
12374 __PACKING_ATTRIBUTE_STRUCT_END__
12375 IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG ;
12376 #else
12377 typedef struct
12378 {
12379         /* RNRA_CNGS_RPT_EN */
12380         uint32_t rnra_cngs_rpt_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12381
12382         /* RNRB_CNGS_RPT_EN */
12383         uint32_t rnrb_cngs_rpt_en       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12384
12385         /* rsv */
12386         uint32_t rsv                    : 14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12387
12388         /* THRESHOLD_DISABLE */
12389         uint32_t threshold_disable      : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12390 }
12391 __PACKING_ATTRIBUTE_STRUCT_END__
12392 IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG ;
12393 #endif
12394
12395 /*****************************************************************************************/
12396 /* RADDR0_CFG                                                                            */
12397 /* Route Addres configuration of following ports: Eth0, Eth1, Eth2, Eth3.    Used for br */
12398 /* oadbus access for the following ports: for sending responses, message and data.       */
12399 /*****************************************************************************************/
12400
12401 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV4_RSV_VALUE                             ( 0x0 )
12402 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12403 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH3_RADDR_ROUTE_ADDRESS_VALUE             ( 0x48 )
12404 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH3_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x48 )
12405 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV3_RSV_VALUE                             ( 0x0 )
12406 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12407 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH2_RADDR_ROUTE_ADDRESS_VALUE             ( 0x54 )
12408 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH2_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x54 )
12409 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV2_RSV_VALUE                             ( 0x0 )
12410 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12411 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH1_RADDR_ROUTE_ADDRESS_VALUE             ( 0x4C )
12412 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH1_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x4C )
12413 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV1_RSV_VALUE                             ( 0x0 )
12414 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12415 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH0_RADDR_ROUTE_ADDRESS_VALUE             ( 0x5C )
12416 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ETH0_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x5C )
12417
12418
12419 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_OFFSET ( 0x0000004C )
12420
12421 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_OFFSET )
12422 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ADDRESS ), (r) )
12423 #define IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG_ADDRESS ), (v) )
12424
12425 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12426 typedef struct
12427 {
12428         /* RSV4 */
12429         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12430
12431         /* ETH3_RADDR */
12432         uint32_t eth3_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12433
12434         /* rsv3 */
12435         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12436
12437         /* ETH2_RADDR */
12438         uint32_t eth2_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12439
12440         /* rsv2 */
12441         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12442
12443         /* ETH1_RADDR */
12444         uint32_t eth1_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12445
12446         /* rsv1 */
12447         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12448
12449         /* ETH0_RADDR */
12450         uint32_t eth0_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12451 }
12452 __PACKING_ATTRIBUTE_STRUCT_END__
12453 IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG ;
12454 #else
12455 typedef struct
12456 {
12457         /* ETH0_RADDR */
12458         uint32_t eth0_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12459
12460         /* rsv1 */
12461         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12462
12463         /* ETH1_RADDR */
12464         uint32_t eth1_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12465
12466         /* rsv2 */
12467         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12468
12469         /* ETH2_RADDR */
12470         uint32_t eth2_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12471
12472         /* rsv3 */
12473         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12474
12475         /* ETH3_RADDR */
12476         uint32_t eth3_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12477
12478         /* RSV4 */
12479         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12480 }
12481 __PACKING_ATTRIBUTE_STRUCT_END__
12482 IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG ;
12483 #endif
12484
12485 /*****************************************************************************************/
12486 /* RADDR1_CFG                                                                            */
12487 /* Route Addres configuration of following ports: Eth4, GPON, Runner A, Runner B    Used */
12488 /*  for broadbus access for the following ports: for sending responses, message and data */
12489 /* .                                                                                     */
12490 /*****************************************************************************************/
12491
12492 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV4_RSV_VALUE                             ( 0x0 )
12493 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12494 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRB_RADDR_ROUTE_ADDRESS_VALUE             ( 0x2 )
12495 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRB_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x2 )
12496 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV3_RSV_VALUE                             ( 0x0 )
12497 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12498 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRA_RADDR_ROUTE_ADDRESS_VALUE             ( 0x3 )
12499 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RNRA_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x3 )
12500 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV2_RSV_VALUE                             ( 0x0 )
12501 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12502 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_GPON_RADDR_ROUTE_ADDRESS_VALUE             ( 0x40 )
12503 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_GPON_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x40 )
12504 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV1_RSV_VALUE                             ( 0x0 )
12505 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
12506 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ETH4_RADDR_ROUTE_ADDRESS_VALUE             ( 0x50 )
12507 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ETH4_RADDR_ROUTE_ADDRESS_VALUE_RESET_VALUE ( 0x50 )
12508
12509
12510 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_OFFSET ( 0x00000050 )
12511
12512 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_OFFSET )
12513 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ADDRESS ), (r) )
12514 #define IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG_ADDRESS ), (v) )
12515
12516 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12517 typedef struct
12518 {
12519         /* RSV4 */
12520         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12521
12522         /* RNRB_RADDR */
12523         uint32_t rnrb_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12524
12525         /* rsv3 */
12526         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12527
12528         /* RNRA_RADDR */
12529         uint32_t rnra_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12530
12531         /* rsv2 */
12532         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12533
12534         /* GPON_RADDR */
12535         uint32_t gpon_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12536
12537         /* rsv1 */
12538         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12539
12540         /* ETH4_RADDR */
12541         uint32_t eth4_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12542 }
12543 __PACKING_ATTRIBUTE_STRUCT_END__
12544 IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG ;
12545 #else
12546 typedef struct
12547 {
12548         /* ETH4_RADDR */
12549         uint32_t eth4_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12550
12551         /* rsv1 */
12552         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12553
12554         /* GPON_RADDR */
12555         uint32_t gpon_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12556
12557         /* rsv2 */
12558         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12559
12560         /* RNRA_RADDR */
12561         uint32_t rnra_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12562
12563         /* rsv3 */
12564         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12565
12566         /* RNRB_RADDR */
12567         uint32_t rnrb_raddr     : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12568
12569         /* RSV4 */
12570         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12571 }
12572 __PACKING_ATTRIBUTE_STRUCT_END__
12573 IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG ;
12574 #endif
12575
12576 /*****************************************************************************************/
12577 /* RBPM_BAT_CFG                                                                          */
12578 /* Runner Buffer Allocation Threshold (per Runner)    IH manages pool of common Runner B */
12579 /* uffers per each Runner. The maximal number of buffers is defined by the following opt */
12580 /* ions:  0x0 - 16 max buffers  0x1 - 24 max buffers  0x2 - 32 max buffers  0x3 - 48 max */
12581 /*  buffers  0x4 - 64 max buffers    Default is 0x0 (32 buffers)                         */
12582 /*****************************************************************************************/
12583
12584 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV2_RSV_VALUE                        ( 0x0 )
12585 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV2_RSV_VALUE_RESET_VALUE            ( 0x0 )
12586 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_16_VALUE             ( 0x0 )
12587 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_24_VALUE             ( 0x1 )
12588 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_32_VALUE             ( 0x2 )
12589 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_32_VALUE_RESET_VALUE ( 0x2 )
12590 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_48_VALUE             ( 0x3 )
12591 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRB_BPM_BAT_MAX_64_VALUE             ( 0x4 )
12592 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV1_RSV_VALUE                        ( 0x0 )
12593 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RSV1_RSV_VALUE_RESET_VALUE            ( 0x0 )
12594 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_16_VALUE             ( 0x0 )
12595 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_24_VALUE             ( 0x1 )
12596 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_32_VALUE             ( 0x2 )
12597 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_32_VALUE_RESET_VALUE ( 0x2 )
12598 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_48_VALUE             ( 0x3 )
12599 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_RNRA_BPM_BAT_MAX_64_VALUE             ( 0x4 )
12600
12601
12602 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_OFFSET ( 0x00000054 )
12603
12604 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_OFFSET )
12605 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_ADDRESS ), (r) )
12606 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG_ADDRESS ), (v) )
12607
12608 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12609 typedef struct
12610 {
12611         /* RSV2 */
12612         uint32_t rsv2           : 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12613
12614         /* RNRB_BPM_BAT */
12615         uint32_t rnrb_bpm_bat   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12616
12617         /* RSV1 */
12618         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12619
12620         /* RNRA_BPM_BAT */
12621         uint32_t rnra_bpm_bat   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12622 }
12623 __PACKING_ATTRIBUTE_STRUCT_END__
12624 IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG ;
12625 #else
12626 typedef struct
12627 {
12628         /* RNRA_BPM_BAT */
12629         uint32_t rnra_bpm_bat   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12630
12631         /* RSV1 */
12632         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12633
12634         /* RNRB_BPM_BAT */
12635         uint32_t rnrb_bpm_bat   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12636
12637         /* RSV2 */
12638         uint32_t rsv2           : 25 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12639 }
12640 __PACKING_ATTRIBUTE_STRUCT_END__
12641 IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG ;
12642 #endif
12643
12644 /*****************************************************************************************/
12645 /* RBPM_BAC_STAT                                                                         */
12646 /* Runner Buffer Allocated Counter (per Runner) - represents the status of allocated buf */
12647 /* fers at moment of read access to register    Background:  IH manages pool of common R */
12648 /* unner Buffers per each Runner. The maximal number of buffers is defined by the follow */
12649 /* ing options:  0x0 - 16 max buffers  0x1 - 24 max buffers  0x2 - 32 max buffers  0x3 - */
12650 /*  48 max buffers  0x4 - 64 max buffers    Default is 0x0 (no buffers)                  */
12651 /*****************************************************************************************/
12652
12653 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RSV2_RSV_VALUE                     ( 0x0 )
12654 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RSV2_RSV_VALUE_RESET_VALUE         ( 0x0 )
12655 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRB_BPM_BAC_BAC_VALUE             ( 0x0 )
12656 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRB_BPM_BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
12657 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRA_BPM_BAC_BAC_VALUE             ( 0x0 )
12658 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_RNRA_BPM_BAC_BAC_VALUE_RESET_VALUE ( 0x0 )
12659
12660
12661 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_OFFSET ( 0x00000058 )
12662
12663 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_OFFSET )
12664 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_ADDRESS ), (r) )
12665 #define IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT_ADDRESS ), (v) )
12666
12667 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12668 typedef struct
12669 {
12670         /* rsv2 */
12671         uint32_t rsv2           : 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12672
12673         /* RNRB_BPM_BAC */
12674         uint32_t rnrb_bpm_bac   : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12675
12676         /* RNRA_BPM_BAC */
12677         uint32_t rnra_bpm_bac   : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12678 }
12679 __PACKING_ATTRIBUTE_STRUCT_END__
12680 IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT ;
12681 #else
12682 typedef struct
12683 {
12684         /* RNRA_BPM_BAC */
12685         uint32_t rnra_bpm_bac   : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12686
12687         /* RNRB_BPM_BAC */
12688         uint32_t rnrb_bpm_bac   : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12689
12690         /* rsv2 */
12691         uint32_t rsv2           : 18 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12692 }
12693 __PACKING_ATTRIBUTE_STRUCT_END__
12694 IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT ;
12695 #endif
12696
12697 /*****************************************************************************************/
12698 /* TRGT_MTRX_ETH0_SP_CFG                                                                 */
12699 /* Target matrix configuration for Source Port Eth0    Used for decision on Target memor */
12700 /* y and Local switch as function of extracted destination port that can be as following */
12701 /* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe  - Multicast (MC)  - CPU  - */
12702 /*  Always DDR (relevant for local switch info)  - Always SRAM(relevant for local switch */
12703 /*  info)                                                                                */
12704 /*****************************************************************************************/
12705
12706 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
12707 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
12708 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
12709 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
12710 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
12711 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
12712 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
12713 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
12714 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
12715 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12716 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
12717 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
12718 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
12719 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
12720 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
12721 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
12722 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
12723 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
12724 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
12725 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
12726 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
12727 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
12728 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
12729 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
12730 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12731 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
12732 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
12733 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12734 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
12735 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
12736 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12737 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
12738 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
12739 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12740 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
12741 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
12742 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12743 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
12744 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
12745 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12746 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
12747 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
12748 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
12749 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
12750 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
12751 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
12752 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
12753 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
12754 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
12755 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
12756 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
12757 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
12758 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
12759 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
12760 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
12761 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
12762 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
12763 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
12764 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
12765 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
12766 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
12767 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
12768 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
12769 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
12770 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
12771 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
12772 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
12773 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
12774 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
12775 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
12776 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
12777 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
12778 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
12779 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
12780 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
12781 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
12782
12783
12784 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_OFFSET ( 0x0000005C )
12785
12786 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_OFFSET )
12787 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_ADDRESS ), (r) )
12788 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG_ADDRESS ), (v) )
12789
12790 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
12791 typedef struct
12792 {
12793         /* RSV2 */
12794         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12795
12796         /* DP_SPARE_LS_CFG */
12797         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12798
12799         /* DP_PCIE1_LS_CFG */
12800         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12801
12802         /* DP_SRAM_LS_CFG */
12803         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12804
12805         /* DP_DDR_LS_CFG */
12806         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12807
12808         /* DP_MC_LS_CFG */
12809         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12810
12811         /* DP_CPU_LS_CFG */
12812         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12813
12814         /* DP_PCIE0_LS_CFG */
12815         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12816
12817         /* DP_GPON_LS_CFG */
12818         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12819
12820         /* DP_ETH4_LS_CFG */
12821         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12822
12823         /* DP_ETH3_LS_CFG */
12824         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12825
12826         /* DP_ETH2_LS_CFG */
12827         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12828
12829         /* DP_ETH1_LS_CFG */
12830         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12831
12832         /* DP_ETH0_LS_CFG */
12833         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12834
12835         /* rsv1 */
12836         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12837
12838         /* DP_SPARE_TM_CFG */
12839         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12840
12841         /* DP_PCIE1_TM_CFG */
12842         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12843
12844         /* DP_MC_TM_CFG */
12845         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12846
12847         /* DP_CPU_TM_CFG */
12848         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12849
12850         /* DP_PCIE0_TM_CFG */
12851         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12852
12853         /* DP_GPON_TM_CFG */
12854         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12855
12856         /* DP_ETH4_TM_CFG */
12857         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12858
12859         /* DP_ETH3_TM_CFG */
12860         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12861
12862         /* DP_ETH2_TM_CFG */
12863         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12864
12865         /* DP_ETH1_TM_CFG */
12866         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12867
12868         /* DP_ETH0_TM_CFG */
12869         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12870 }
12871 __PACKING_ATTRIBUTE_STRUCT_END__
12872 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG ;
12873 #else
12874 typedef struct
12875 {
12876         /* DP_ETH0_TM_CFG */
12877         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12878
12879         /* DP_ETH1_TM_CFG */
12880         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12881
12882         /* DP_ETH2_TM_CFG */
12883         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12884
12885         /* DP_ETH3_TM_CFG */
12886         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12887
12888         /* DP_ETH4_TM_CFG */
12889         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12890
12891         /* DP_GPON_TM_CFG */
12892         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12893
12894         /* DP_PCIE0_TM_CFG */
12895         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12896
12897         /* DP_CPU_TM_CFG */
12898         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12899
12900         /* DP_MC_TM_CFG */
12901         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12902
12903         /* DP_PCIE1_TM_CFG */
12904         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12905
12906         /* DP_SPARE_TM_CFG */
12907         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12908
12909         /* rsv1 */
12910         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12911
12912         /* DP_ETH0_LS_CFG */
12913         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12914
12915         /* DP_ETH1_LS_CFG */
12916         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12917
12918         /* DP_ETH2_LS_CFG */
12919         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12920
12921         /* DP_ETH3_LS_CFG */
12922         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12923
12924         /* DP_ETH4_LS_CFG */
12925         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12926
12927         /* DP_GPON_LS_CFG */
12928         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12929
12930         /* DP_PCIE0_LS_CFG */
12931         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12932
12933         /* DP_CPU_LS_CFG */
12934         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12935
12936         /* DP_MC_LS_CFG */
12937         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12938
12939         /* DP_DDR_LS_CFG */
12940         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12941
12942         /* DP_SRAM_LS_CFG */
12943         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12944
12945         /* DP_PCIE1_LS_CFG */
12946         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12947
12948         /* DP_SPARE_LS_CFG */
12949         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12950
12951         /* RSV2 */
12952         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
12953 }
12954 __PACKING_ATTRIBUTE_STRUCT_END__
12955 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG ;
12956 #endif
12957
12958 /*****************************************************************************************/
12959 /* TRGT_MTRX_ETH1_SP_CFG                                                                 */
12960 /* Target matrix configuration for Source Port Eth1    Used for decision on Target memor */
12961 /* y and Local switch as function of extracted destination port that can be as following */
12962 /* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
12963 /*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
12964 /* tch info)  -Spare                                                                     */
12965 /*****************************************************************************************/
12966
12967 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
12968 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
12969 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
12970 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
12971 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
12972 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
12973 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
12974 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
12975 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
12976 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12977 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
12978 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
12979 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
12980 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
12981 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
12982 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
12983 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
12984 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
12985 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
12986 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
12987 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
12988 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
12989 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
12990 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
12991 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12992 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
12993 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
12994 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12995 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
12996 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
12997 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
12998 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
12999 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
13000 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13001 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
13002 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
13003 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13004 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
13005 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
13006 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13007 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
13008 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
13009 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
13010 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13011 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13012 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13013 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13014 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13015 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13016 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
13017 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
13018 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
13019 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
13020 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
13021 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
13022 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13023 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13024 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13025 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13026 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13027 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13028 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13029 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13030 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13031 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13032 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13033 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13034 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13035 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13036 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13037 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13038 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13039 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13040 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13041 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13042 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13043
13044
13045 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_OFFSET ( 0x00000060 )
13046
13047 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_OFFSET )
13048 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_ADDRESS ), (r) )
13049 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG_ADDRESS ), (v) )
13050
13051 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
13052 typedef struct
13053 {
13054         /* RSV2 */
13055         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13056
13057         /* DP_SPARE_LS_CFG */
13058         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13059
13060         /* DP_PCIE1_LS_CFG */
13061         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13062
13063         /* DP_SRAM_LS_CFG */
13064         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13065
13066         /* DP_DDR_LS_CFG */
13067         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13068
13069         /* DP_MC_LS_CFG */
13070         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13071
13072         /* DP_CPU_LS_CFG */
13073         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13074
13075         /* DP_PCIE0_LS_CFG */
13076         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13077
13078         /* DP_GPON_LS_CFG */
13079         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13080
13081         /* DP_ETH4_LS_CFG */
13082         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13083
13084         /* DP_ETH3_LS_CFG */
13085         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13086
13087         /* DP_ETH2_LS_CFG */
13088         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13089
13090         /* DP_ETH1_LS_CFG */
13091         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13092
13093         /* DP_ETH0_LS_CFG */
13094         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13095
13096         /* rsv1 */
13097         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13098
13099         /* DP_SPARE_TM_CFG */
13100         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13101
13102         /* DP_PCIE1_TM_CFG */
13103         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13104
13105         /* DP_MC_TM_CFG */
13106         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13107
13108         /* DP_CPU_TM_CFG */
13109         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13110
13111         /* DP_PCIE0_TM_CFG */
13112         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13113
13114         /* DP_GPON_TM_CFG */
13115         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13116
13117         /* DP_ETH4_TM_CFG */
13118         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13119
13120         /* DP_ETH3_TM_CFG */
13121         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13122
13123         /* DP_ETH2_TM_CFG */
13124         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13125
13126         /* DP_ETH1_TM_CFG */
13127         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13128
13129         /* DP_ETH0_TM_CFG */
13130         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13131 }
13132 __PACKING_ATTRIBUTE_STRUCT_END__
13133 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG ;
13134 #else
13135 typedef struct
13136 {
13137         /* DP_ETH0_TM_CFG */
13138         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13139
13140         /* DP_ETH1_TM_CFG */
13141         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13142
13143         /* DP_ETH2_TM_CFG */
13144         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13145
13146         /* DP_ETH3_TM_CFG */
13147         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13148
13149         /* DP_ETH4_TM_CFG */
13150         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13151
13152         /* DP_GPON_TM_CFG */
13153         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13154
13155         /* DP_PCIE0_TM_CFG */
13156         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13157
13158         /* DP_CPU_TM_CFG */
13159         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13160
13161         /* DP_MC_TM_CFG */
13162         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13163
13164         /* DP_PCIE1_TM_CFG */
13165         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13166
13167         /* DP_SPARE_TM_CFG */
13168         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13169
13170         /* rsv1 */
13171         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13172
13173         /* DP_ETH0_LS_CFG */
13174         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13175
13176         /* DP_ETH1_LS_CFG */
13177         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13178
13179         /* DP_ETH2_LS_CFG */
13180         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13181
13182         /* DP_ETH3_LS_CFG */
13183         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13184
13185         /* DP_ETH4_LS_CFG */
13186         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13187
13188         /* DP_GPON_LS_CFG */
13189         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13190
13191         /* DP_PCIE0_LS_CFG */
13192         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13193
13194         /* DP_CPU_LS_CFG */
13195         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13196
13197         /* DP_MC_LS_CFG */
13198         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13199
13200         /* DP_DDR_LS_CFG */
13201         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13202
13203         /* DP_SRAM_LS_CFG */
13204         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13205
13206         /* DP_PCIE1_LS_CFG */
13207         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13208
13209         /* DP_SPARE_LS_CFG */
13210         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13211
13212         /* RSV2 */
13213         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13214 }
13215 __PACKING_ATTRIBUTE_STRUCT_END__
13216 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG ;
13217 #endif
13218
13219 /*****************************************************************************************/
13220 /* TRGT_MTRX_ETH2_SP_CFG                                                                 */
13221 /* Target matrix configuration for Source Port Eth2    Used for decision on Target memor */
13222 /* y and Local switch as function of extracted destination port that can be as following */
13223 /* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
13224 /*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
13225 /* tch info)  -Spare                                                                     */
13226 /*****************************************************************************************/
13227
13228 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
13229 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
13230 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
13231 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13232 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
13233 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
13234 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13235 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
13236 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
13237 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13238 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
13239 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
13240 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
13241 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
13242 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
13243 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
13244 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
13245 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
13246 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
13247 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
13248 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
13249 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13250 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
13251 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
13252 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13253 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
13254 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
13255 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13256 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
13257 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
13258 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13259 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
13260 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
13261 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13262 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
13263 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
13264 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13265 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
13266 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
13267 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13268 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
13269 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
13270 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
13271 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13272 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13273 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13274 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13275 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13276 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13277 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
13278 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
13279 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
13280 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
13281 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
13282 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
13283 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13284 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13285 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13286 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13287 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13288 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13289 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13290 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13291 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13292 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13293 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13294 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13295 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13296 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13297 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13298 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13299 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13300 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13301 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13302 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13303 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13304
13305
13306 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_OFFSET ( 0x00000064 )
13307
13308 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_OFFSET )
13309 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_ADDRESS ), (r) )
13310 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG_ADDRESS ), (v) )
13311
13312 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
13313 typedef struct
13314 {
13315         /* RSV2 */
13316         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13317
13318         /* DP_SPARE_LS_CFG */
13319         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13320
13321         /* DP_PCIE1_LS_CFG */
13322         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13323
13324         /* DP_SRAM_LS_CFG */
13325         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13326
13327         /* DP_DDR_LS_CFG */
13328         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13329
13330         /* DP_MC_LS_CFG */
13331         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13332
13333         /* DP_CPU_LS_CFG */
13334         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13335
13336         /* DP_PCIE0_LS_CFG */
13337         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13338
13339         /* DP_GPON_LS_CFG */
13340         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13341
13342         /* DP_ETH4_LS_CFG */
13343         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13344
13345         /* DP_ETH3_LS_CFG */
13346         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13347
13348         /* DP_ETH2_LS_CFG */
13349         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13350
13351         /* DP_ETH1_LS_CFG */
13352         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13353
13354         /* DP_ETH0_LS_CFG */
13355         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13356
13357         /* rsv1 */
13358         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13359
13360         /* DP_SPARE_TM_CFG */
13361         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13362
13363         /* DP_PCIE1_TM_CFG */
13364         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13365
13366         /* DP_MC_TM_CFG */
13367         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13368
13369         /* DP_CPU_TM_CFG */
13370         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13371
13372         /* DP_PCIE0_TM_CFG */
13373         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13374
13375         /* DP_GPON_TM_CFG */
13376         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13377
13378         /* DP_ETH4_TM_CFG */
13379         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13380
13381         /* DP_ETH3_TM_CFG */
13382         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13383
13384         /* DP_ETH2_TM_CFG */
13385         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13386
13387         /* DP_ETH1_TM_CFG */
13388         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13389
13390         /* DP_ETH0_TM_CFG */
13391         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13392 }
13393 __PACKING_ATTRIBUTE_STRUCT_END__
13394 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG ;
13395 #else
13396 typedef struct
13397 {
13398         /* DP_ETH0_TM_CFG */
13399         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13400
13401         /* DP_ETH1_TM_CFG */
13402         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13403
13404         /* DP_ETH2_TM_CFG */
13405         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13406
13407         /* DP_ETH3_TM_CFG */
13408         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13409
13410         /* DP_ETH4_TM_CFG */
13411         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13412
13413         /* DP_GPON_TM_CFG */
13414         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13415
13416         /* DP_PCIE0_TM_CFG */
13417         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13418
13419         /* DP_CPU_TM_CFG */
13420         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13421
13422         /* DP_MC_TM_CFG */
13423         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13424
13425         /* DP_PCIE1_TM_CFG */
13426         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13427
13428         /* DP_SPARE_TM_CFG */
13429         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13430
13431         /* rsv1 */
13432         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13433
13434         /* DP_ETH0_LS_CFG */
13435         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13436
13437         /* DP_ETH1_LS_CFG */
13438         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13439
13440         /* DP_ETH2_LS_CFG */
13441         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13442
13443         /* DP_ETH3_LS_CFG */
13444         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13445
13446         /* DP_ETH4_LS_CFG */
13447         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13448
13449         /* DP_GPON_LS_CFG */
13450         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13451
13452         /* DP_PCIE0_LS_CFG */
13453         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13454
13455         /* DP_CPU_LS_CFG */
13456         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13457
13458         /* DP_MC_LS_CFG */
13459         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13460
13461         /* DP_DDR_LS_CFG */
13462         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13463
13464         /* DP_SRAM_LS_CFG */
13465         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13466
13467         /* DP_PCIE1_LS_CFG */
13468         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13469
13470         /* DP_SPARE_LS_CFG */
13471         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13472
13473         /* RSV2 */
13474         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13475 }
13476 __PACKING_ATTRIBUTE_STRUCT_END__
13477 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG ;
13478 #endif
13479
13480 /*****************************************************************************************/
13481 /* TRGT_MTRX_ETH3_SP_CFG                                                                 */
13482 /* Target matrix configuration for Source Port Eth3    Used for decision on Target memor */
13483 /* y and Local switch as function of extracted destination port that can be as following */
13484 /* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
13485 /*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
13486 /* tch info)  -Spare                                                                     */
13487 /*****************************************************************************************/
13488
13489 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
13490 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
13491 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
13492 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13493 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
13494 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
13495 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13496 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
13497 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
13498 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13499 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
13500 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
13501 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
13502 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
13503 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
13504 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
13505 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
13506 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
13507 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
13508 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
13509 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
13510 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13511 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
13512 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
13513 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13514 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
13515 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
13516 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13517 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
13518 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
13519 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13520 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
13521 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
13522 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13523 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
13524 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
13525 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13526 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
13527 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
13528 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13529 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
13530 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
13531 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
13532 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13533 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13534 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13535 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13536 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13537 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13538 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
13539 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
13540 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
13541 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
13542 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
13543 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
13544 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13545 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13546 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13547 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13548 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13549 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13550 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13551 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13552 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13553 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13554 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13555 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13556 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13557 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13558 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13559 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13560 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13561 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13562 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13563 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13564 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13565
13566
13567 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_OFFSET ( 0x00000068 )
13568
13569 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_OFFSET )
13570 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_ADDRESS ), (r) )
13571 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG_ADDRESS ), (v) )
13572
13573 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
13574 typedef struct
13575 {
13576         /* RSV2 */
13577         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13578
13579         /* DP_SPARE_LS_CFG */
13580         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13581
13582         /* DP_PCIE1_LS_CFG */
13583         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13584
13585         /* DP_SRAM_LS_CFG */
13586         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13587
13588         /* DP_DDR_LS_CFG */
13589         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13590
13591         /* DP_MC_LS_CFG */
13592         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13593
13594         /* DP_CPU_LS_CFG */
13595         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13596
13597         /* DP_PCIE0_LS_CFG */
13598         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13599
13600         /* DP_GPON_LS_CFG */
13601         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13602
13603         /* DP_ETH4_LS_CFG */
13604         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13605
13606         /* DP_ETH3_LS_CFG */
13607         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13608
13609         /* DP_ETH2_LS_CFG */
13610         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13611
13612         /* DP_ETH1_LS_CFG */
13613         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13614
13615         /* DP_ETH0_LS_CFG */
13616         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13617
13618         /* rsv1 */
13619         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13620
13621         /* DP_SPARE_TM_CFG */
13622         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13623
13624         /* DP_PCIE1_TM_CFG */
13625         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13626
13627         /* DP_MC_TM_CFG */
13628         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13629
13630         /* DP_CPU_TM_CFG */
13631         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13632
13633         /* DP_PCIE0_TM_CFG */
13634         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13635
13636         /* DP_GPON_TM_CFG */
13637         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13638
13639         /* DP_ETH4_TM_CFG */
13640         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13641
13642         /* DP_ETH3_TM_CFG */
13643         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13644
13645         /* DP_ETH2_TM_CFG */
13646         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13647
13648         /* DP_ETH1_TM_CFG */
13649         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13650
13651         /* DP_ETH0_TM_CFG */
13652         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13653 }
13654 __PACKING_ATTRIBUTE_STRUCT_END__
13655 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG ;
13656 #else
13657 typedef struct
13658 {
13659         /* DP_ETH0_TM_CFG */
13660         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13661
13662         /* DP_ETH1_TM_CFG */
13663         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13664
13665         /* DP_ETH2_TM_CFG */
13666         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13667
13668         /* DP_ETH3_TM_CFG */
13669         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13670
13671         /* DP_ETH4_TM_CFG */
13672         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13673
13674         /* DP_GPON_TM_CFG */
13675         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13676
13677         /* DP_PCIE0_TM_CFG */
13678         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13679
13680         /* DP_CPU_TM_CFG */
13681         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13682
13683         /* DP_MC_TM_CFG */
13684         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13685
13686         /* DP_PCIE1_TM_CFG */
13687         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13688
13689         /* DP_SPARE_TM_CFG */
13690         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13691
13692         /* rsv1 */
13693         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13694
13695         /* DP_ETH0_LS_CFG */
13696         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13697
13698         /* DP_ETH1_LS_CFG */
13699         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13700
13701         /* DP_ETH2_LS_CFG */
13702         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13703
13704         /* DP_ETH3_LS_CFG */
13705         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13706
13707         /* DP_ETH4_LS_CFG */
13708         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13709
13710         /* DP_GPON_LS_CFG */
13711         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13712
13713         /* DP_PCIE0_LS_CFG */
13714         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13715
13716         /* DP_CPU_LS_CFG */
13717         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13718
13719         /* DP_MC_LS_CFG */
13720         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13721
13722         /* DP_DDR_LS_CFG */
13723         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13724
13725         /* DP_SRAM_LS_CFG */
13726         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13727
13728         /* DP_PCIE1_LS_CFG */
13729         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13730
13731         /* DP_SPARE_LS_CFG */
13732         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13733
13734         /* RSV2 */
13735         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13736 }
13737 __PACKING_ATTRIBUTE_STRUCT_END__
13738 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG ;
13739 #endif
13740
13741 /*****************************************************************************************/
13742 /* TRGT_MTRX_ETH4_SP_CFG                                                                 */
13743 /* Target matrix configuration for Source Port Eth4    Used for decision on Target memor */
13744 /* y and Local switch as function of extracted destination port that can be as following */
13745 /* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
13746 /*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
13747 /* tch info)  -Spare                                                                     */
13748 /*****************************************************************************************/
13749
13750 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
13751 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
13752 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
13753 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13754 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
13755 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
13756 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13757 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
13758 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
13759 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13760 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
13761 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
13762 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
13763 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
13764 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
13765 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
13766 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
13767 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
13768 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
13769 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
13770 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
13771 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
13772 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
13773 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
13774 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13775 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
13776 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
13777 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13778 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
13779 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
13780 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13781 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
13782 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
13783 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13784 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
13785 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
13786 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13787 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
13788 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
13789 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
13790 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
13791 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
13792 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
13793 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13794 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13795 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13796 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13797 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13798 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13799 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
13800 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
13801 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
13802 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
13803 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
13804 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
13805 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
13806 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
13807 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
13808 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13809 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13810 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13811 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13812 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13813 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13814 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13815 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13816 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13817 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13818 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13819 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13820 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13821 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13822 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13823 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
13824 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
13825 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
13826
13827
13828 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_OFFSET ( 0x0000006C )
13829
13830 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_OFFSET )
13831 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_ADDRESS ), (r) )
13832 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG_ADDRESS ), (v) )
13833
13834 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
13835 typedef struct
13836 {
13837         /* RSV2 */
13838         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13839
13840         /* DP_SPARE_LS_CFG */
13841         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13842
13843         /* DP_PCIE1_LS_CFG */
13844         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13845
13846         /* DP_SRAM_LS_CFG */
13847         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13848
13849         /* DP_DDR_LS_CFG */
13850         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13851
13852         /* DP_MC_LS_CFG */
13853         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13854
13855         /* DP_CPU_LS_CFG */
13856         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13857
13858         /* DP_PCIE0_LS_CFG */
13859         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13860
13861         /* DP_GPON_LS_CFG */
13862         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13863
13864         /* DP_ETH4_LS_CFG */
13865         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13866
13867         /* DP_ETH3_LS_CFG */
13868         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13869
13870         /* DP_ETH2_LS_CFG */
13871         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13872
13873         /* DP_ETH1_LS_CFG */
13874         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13875
13876         /* DP_ETH0_LS_CFG */
13877         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13878
13879         /* rsv1 */
13880         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13881
13882         /* DP_SPARE_TM_CFG */
13883         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13884
13885         /* DP_PCIE1_TM_CFG */
13886         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13887
13888         /* DP_MC_TM_CFG */
13889         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13890
13891         /* DP_CPU_TM_CFG */
13892         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13893
13894         /* DP_PCIE0_TM_CFG */
13895         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13896
13897         /* DP_GPON_TM_CFG */
13898         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13899
13900         /* DP_ETH4_TM_CFG */
13901         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13902
13903         /* DP_ETH3_TM_CFG */
13904         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13905
13906         /* DP_ETH2_TM_CFG */
13907         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13908
13909         /* DP_ETH1_TM_CFG */
13910         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13911
13912         /* DP_ETH0_TM_CFG */
13913         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13914 }
13915 __PACKING_ATTRIBUTE_STRUCT_END__
13916 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG ;
13917 #else
13918 typedef struct
13919 {
13920         /* DP_ETH0_TM_CFG */
13921         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13922
13923         /* DP_ETH1_TM_CFG */
13924         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13925
13926         /* DP_ETH2_TM_CFG */
13927         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13928
13929         /* DP_ETH3_TM_CFG */
13930         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13931
13932         /* DP_ETH4_TM_CFG */
13933         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13934
13935         /* DP_GPON_TM_CFG */
13936         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13937
13938         /* DP_PCIE0_TM_CFG */
13939         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13940
13941         /* DP_CPU_TM_CFG */
13942         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13943
13944         /* DP_MC_TM_CFG */
13945         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13946
13947         /* DP_PCIE1_TM_CFG */
13948         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13949
13950         /* DP_SPARE_TM_CFG */
13951         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13952
13953         /* rsv1 */
13954         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13955
13956         /* DP_ETH0_LS_CFG */
13957         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13958
13959         /* DP_ETH1_LS_CFG */
13960         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13961
13962         /* DP_ETH2_LS_CFG */
13963         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13964
13965         /* DP_ETH3_LS_CFG */
13966         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13967
13968         /* DP_ETH4_LS_CFG */
13969         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13970
13971         /* DP_GPON_LS_CFG */
13972         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13973
13974         /* DP_PCIE0_LS_CFG */
13975         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13976
13977         /* DP_CPU_LS_CFG */
13978         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13979
13980         /* DP_MC_LS_CFG */
13981         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13982
13983         /* DP_DDR_LS_CFG */
13984         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13985
13986         /* DP_SRAM_LS_CFG */
13987         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13988
13989         /* DP_PCIE1_LS_CFG */
13990         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13991
13992         /* DP_SPARE_LS_CFG */
13993         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13994
13995         /* RSV2 */
13996         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
13997 }
13998 __PACKING_ATTRIBUTE_STRUCT_END__
13999 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG ;
14000 #endif
14001
14002 /*****************************************************************************************/
14003 /* TRGT_MTRX_GPON_SP_CFG                                                                 */
14004 /* Target matrix configuration for Source Port GPON    Used for decision on Target memor */
14005 /* y and Local switch as function of extracted destination port that can be as following */
14006 /* :  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU */
14007 /*   - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local swi */
14008 /* tch info)  -Spare                                                                     */
14009 /*****************************************************************************************/
14010
14011 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
14012 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
14013 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
14014 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
14015 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
14016 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
14017 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
14018 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
14019 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
14020 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
14021 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
14022 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
14023 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
14024 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
14025 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
14026 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
14027 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
14028 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
14029 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
14030 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
14031 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
14032 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
14033 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
14034 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
14035 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
14036 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
14037 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
14038 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
14039 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
14040 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
14041 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
14042 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
14043 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
14044 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
14045 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
14046 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
14047 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
14048 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
14049 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
14050 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
14051 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
14052 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
14053 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
14054 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
14055 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
14056 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
14057 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
14058 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
14059 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
14060 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
14061 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
14062 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
14063 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
14064 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
14065 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
14066 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
14067 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
14068 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
14069 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
14070 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
14071 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
14072 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
14073 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
14074 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
14075 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
14076 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
14077 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
14078 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
14079 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
14080 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
14081 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
14082 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
14083 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
14084 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
14085 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
14086 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
14087
14088
14089 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_OFFSET ( 0x00000070 )
14090
14091 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_OFFSET )
14092 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_ADDRESS ), (r) )
14093 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG_ADDRESS ), (v) )
14094
14095 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
14096 typedef struct
14097 {
14098         /* RSV2 */
14099         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14100
14101         /* DP_SPARE_LS_CFG */
14102         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14103
14104         /* DP_PCIE1_LS_CFG */
14105         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14106
14107         /* DP_SRAM_LS_CFG */
14108         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14109
14110         /* DP_DDR_LS_CFG */
14111         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14112
14113         /* DP_MC_LS_CFG */
14114         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14115
14116         /* DP_CPU_LS_CFG */
14117         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14118
14119         /* DP_PCIE0_LS_CFG */
14120         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14121
14122         /* DP_GPON_LS_CFG */
14123         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14124
14125         /* DP_ETH4_LS_CFG */
14126         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14127
14128         /* DP_ETH3_LS_CFG */
14129         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14130
14131         /* DP_ETH2_LS_CFG */
14132         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14133
14134         /* DP_ETH1_LS_CFG */
14135         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14136
14137         /* DP_ETH0_LS_CFG */
14138         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14139
14140         /* rsv1 */
14141         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14142
14143         /* DP_SPARE_TM_CFG */
14144         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14145
14146         /* DP_PCIE1_TM_CFG */
14147         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14148
14149         /* DP_MC_TM_CFG */
14150         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14151
14152         /* DP_CPU_TM_CFG */
14153         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14154
14155         /* DP_PCIE0_TM_CFG */
14156         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14157
14158         /* DP_GPON_TM_CFG */
14159         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14160
14161         /* DP_ETH4_TM_CFG */
14162         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14163
14164         /* DP_ETH3_TM_CFG */
14165         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14166
14167         /* DP_ETH2_TM_CFG */
14168         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14169
14170         /* DP_ETH1_TM_CFG */
14171         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14172
14173         /* DP_ETH0_TM_CFG */
14174         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14175 }
14176 __PACKING_ATTRIBUTE_STRUCT_END__
14177 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG ;
14178 #else
14179 typedef struct
14180 {
14181         /* DP_ETH0_TM_CFG */
14182         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14183
14184         /* DP_ETH1_TM_CFG */
14185         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14186
14187         /* DP_ETH2_TM_CFG */
14188         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14189
14190         /* DP_ETH3_TM_CFG */
14191         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14192
14193         /* DP_ETH4_TM_CFG */
14194         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14195
14196         /* DP_GPON_TM_CFG */
14197         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14198
14199         /* DP_PCIE0_TM_CFG */
14200         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14201
14202         /* DP_CPU_TM_CFG */
14203         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14204
14205         /* DP_MC_TM_CFG */
14206         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14207
14208         /* DP_PCIE1_TM_CFG */
14209         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14210
14211         /* DP_SPARE_TM_CFG */
14212         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14213
14214         /* rsv1 */
14215         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14216
14217         /* DP_ETH0_LS_CFG */
14218         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14219
14220         /* DP_ETH1_LS_CFG */
14221         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14222
14223         /* DP_ETH2_LS_CFG */
14224         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14225
14226         /* DP_ETH3_LS_CFG */
14227         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14228
14229         /* DP_ETH4_LS_CFG */
14230         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14231
14232         /* DP_GPON_LS_CFG */
14233         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14234
14235         /* DP_PCIE0_LS_CFG */
14236         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14237
14238         /* DP_CPU_LS_CFG */
14239         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14240
14241         /* DP_MC_LS_CFG */
14242         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14243
14244         /* DP_DDR_LS_CFG */
14245         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14246
14247         /* DP_SRAM_LS_CFG */
14248         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14249
14250         /* DP_PCIE1_LS_CFG */
14251         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14252
14253         /* DP_SPARE_LS_CFG */
14254         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14255
14256         /* RSV2 */
14257         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14258 }
14259 __PACKING_ATTRIBUTE_STRUCT_END__
14260 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG ;
14261 #endif
14262
14263 /*****************************************************************************************/
14264 /* IH_MISC_CFG                                                                           */
14265 /* Ingres handler Miscellenous Control:    - Look-up enable in Direct Mode  - Serail Num */
14266 /* ber stamping enable for Short Packets                                                 */
14267 /*****************************************************************************************/
14268
14269 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_RSV_RSV_VALUE                                                      ( 0x0 )
14270 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_RSV_RSV_VALUE_RESET_VALUE                                          ( 0x0 )
14271 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_NVAL_CAM_SEARCH_EN_DIS_SEARCH_IN_CAM_AFTER_INVAL_VALUE             ( 0x0 )
14272 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_NVAL_CAM_SEARCH_EN_DIS_SEARCH_IN_CAM_AFTER_INVAL_VALUE_RESET_VALUE ( 0x0 )
14273 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_NVAL_CAM_SEARCH_EN_EN_SEARCH_IN_CAM_AFTER_INVAL_VALUE              ( 0x1 )
14274 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_CNGS_DSCRD_DIS_CNGS_DISCARD_EN_VALUE                               ( 0x0 )
14275 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_CNGS_DSCRD_DIS_CNGS_DISCARD_EN_VALUE_RESET_VALUE                   ( 0x0 )
14276 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_CNGS_DSCRD_DIS_CNGS_DISCARD_DIS_VALUE                              ( 0x1 )
14277 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_HLENGTH_MIN_TRSH_HLENGTH_MIN_TRSH_VAL_VALUE                        ( 0x40 )
14278 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_HLENGTH_MIN_TRSH_HLENGTH_MIN_TRSH_VAL_VALUE_RESET_VALUE            ( 0x40 )
14279 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_SN_STAMP_DM_PKT_DIS_STAMPING_SN_VALUE                              ( 0x0 )
14280 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_SN_STAMP_DM_PKT_DIS_STAMPING_SN_VALUE_RESET_VALUE                  ( 0x0 )
14281 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_SN_STAMP_DM_PKT_EN_STAMPING_SN_VALUE                               ( 0x1 )
14282 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_LUT_EN_DIRECT_MODE_DISABLE_LOOKUP_VALUE                            ( 0x0 )
14283 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_LUT_EN_DIRECT_MODE_ENABLE_LOOKUP_VALUE                             ( 0x1 )
14284 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_LUT_EN_DIRECT_MODE_ENABLE_LOOKUP_VALUE_RESET_VALUE                 ( 0x1 )
14285
14286
14287 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_OFFSET ( 0x00000074 )
14288
14289 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_ADDRESS       ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_OFFSET )
14290 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_READ( r )     READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_ADDRESS ), (r) )
14291 #define IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_WRITE( v )    WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG_ADDRESS ), (v) )
14292
14293 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
14294 typedef struct
14295 {
14296         /* rsv */
14297         uint32_t rsv                    : 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14298
14299         /* NVAL_CAM_SEARCH_EN */
14300         uint32_t nval_cam_search_en     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14301
14302         /* CNGS_DSCRD_DIS */
14303         uint32_t cngs_dscrd_dis         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14304
14305         /* HLENGTH_MIN_TRSH */
14306         uint32_t hlength_min_trsh       : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14307
14308         /* SN_STAMP_DM_PKT */
14309         uint32_t sn_stamp_dm_pkt        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14310
14311         /* LUT_EN_DIRECT_MODE */
14312         uint32_t lut_en_direct_mode     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14313 }
14314 __PACKING_ATTRIBUTE_STRUCT_END__
14315 IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG ;
14316 #else
14317 typedef struct
14318 {
14319         /* LUT_EN_DIRECT_MODE */
14320         uint32_t lut_en_direct_mode     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14321
14322         /* SN_STAMP_DM_PKT */
14323         uint32_t sn_stamp_dm_pkt        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14324
14325         /* HLENGTH_MIN_TRSH */
14326         uint32_t hlength_min_trsh       : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14327
14328         /* CNGS_DSCRD_DIS */
14329         uint32_t cngs_dscrd_dis         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14330
14331         /* NVAL_CAM_SEARCH_EN */
14332         uint32_t nval_cam_search_en     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14333
14334         /* rsv */
14335         uint32_t rsv                    : 20 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14336 }
14337 __PACKING_ATTRIBUTE_STRUCT_END__
14338 IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG ;
14339 #endif
14340
14341 /*****************************************************************************************/
14342 /* IH_CLASS_KEY0                                                                         */
14343 /* IH Class - Key0 configuration    Note: used for IH class identification by Parser Cla */
14344 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
14345 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
14346 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
14347 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
14348 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
14349 /*****************************************************************************************/
14350
14351 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
14352 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
14353 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
14354 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
14355 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
14356 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
14357 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
14358 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
14359 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
14360 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
14361 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
14362 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
14363 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
14364 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
14365 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
14366 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
14367 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
14368 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
14369 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
14370 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
14371 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
14372 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
14373 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
14374 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
14375 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
14376 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
14377 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
14378 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
14379 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
14380 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
14381 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
14382 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
14383 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
14384 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
14385 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
14386 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
14387 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
14388 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
14389 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
14390 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
14391 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
14392 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
14393 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
14394 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
14395 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
14396 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
14397 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
14398 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
14399 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
14400 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
14401 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
14402 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
14403 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
14404 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
14405 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
14406 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
14407 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
14408 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
14409 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
14410 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
14411 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
14412 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
14413 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
14414 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
14415 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
14416 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
14417 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
14418 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
14419 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
14420 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
14421 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
14422 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
14423 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
14424 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
14425 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
14426 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
14427 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
14428 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
14429 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
14430 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
14431 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
14432 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
14433 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
14434 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
14435 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
14436 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
14437 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
14438 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
14439 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
14440 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
14441 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
14442 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
14443 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
14444 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
14445 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
14446 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
14447 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
14448 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
14449 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
14450 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
14451 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
14452 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
14453 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
14454
14455
14456 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_OFFSET ( 0x00000078 )
14457
14458 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_OFFSET )
14459 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_ADDRESS ), (r) )
14460 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0_ADDRESS ), (v) )
14461
14462 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
14463 typedef struct
14464 {
14465         /* IH_CLASS_KEY_ERR */
14466         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14467
14468         /* IH_CLASS_KEY_SP */
14469         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14470
14471         /* IH_CLASS_KEY_5TPL_FLTR */
14472         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14473
14474         /* IH_CLASS_KEY_WAN_FLTR */
14475         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14476
14477         /* IH_CLASS_KEY_IP_ANYHIT */
14478         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14479
14480         /* IH_CLASS_KEY_IP_FLTR */
14481         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14482
14483         /* IH_CLASS_KEY_VID_ANYHIT */
14484         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14485
14486         /* IH_CLASS_KEY_VID_FLTR */
14487         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14488
14489         /* IH_CLASS_KEY_BC_FLTR */
14490         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14491
14492         /* IH_CLASS_KEY_MC_FLTR */
14493         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14494
14495         /* IH_CLASS_KEY_DA_ANYHIT */
14496         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14497
14498         /* IH_CLASS_KEY_DA_FLTR */
14499         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14500
14501         /* IH_CLASS_KEY_L4 */
14502         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14503
14504         /* IH_CLASS_KEY_L3 */
14505         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14506
14507         /* IH_CLASS_KEY_L2 */
14508         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14509 }
14510 __PACKING_ATTRIBUTE_STRUCT_END__
14511 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0 ;
14512 #else
14513 typedef struct
14514 {
14515         /* IH_CLASS_KEY_L2 */
14516         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14517
14518         /* IH_CLASS_KEY_L3 */
14519         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14520
14521         /* IH_CLASS_KEY_L4 */
14522         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14523
14524         /* IH_CLASS_KEY_DA_FLTR */
14525         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14526
14527         /* IH_CLASS_KEY_DA_ANYHIT */
14528         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14529
14530         /* IH_CLASS_KEY_MC_FLTR */
14531         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14532
14533         /* IH_CLASS_KEY_BC_FLTR */
14534         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14535
14536         /* IH_CLASS_KEY_VID_FLTR */
14537         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14538
14539         /* IH_CLASS_KEY_VID_ANYHIT */
14540         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14541
14542         /* IH_CLASS_KEY_IP_FLTR */
14543         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14544
14545         /* IH_CLASS_KEY_IP_ANYHIT */
14546         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14547
14548         /* IH_CLASS_KEY_WAN_FLTR */
14549         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14550
14551         /* IH_CLASS_KEY_5TPL_FLTR */
14552         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14553
14554         /* IH_CLASS_KEY_SP */
14555         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14556
14557         /* IH_CLASS_KEY_ERR */
14558         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14559 }
14560 __PACKING_ATTRIBUTE_STRUCT_END__
14561 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0 ;
14562 #endif
14563
14564 /*****************************************************************************************/
14565 /* IH_CLASS_KEY1                                                                         */
14566 /* IH Class - Key1 configuration    Note: used for IH class identification by Parser Cla */
14567 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
14568 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
14569 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
14570 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
14571 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
14572 /*****************************************************************************************/
14573
14574 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
14575 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
14576 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
14577 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
14578 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
14579 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
14580 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
14581 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
14582 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
14583 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
14584 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
14585 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
14586 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
14587 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
14588 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
14589 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
14590 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
14591 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
14592 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
14593 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
14594 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
14595 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
14596 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
14597 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
14598 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
14599 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
14600 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
14601 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
14602 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
14603 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
14604 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
14605 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
14606 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
14607 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
14608 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
14609 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
14610 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
14611 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
14612 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
14613 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
14614 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
14615 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
14616 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
14617 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
14618 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
14619 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
14620 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
14621 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
14622 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
14623 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
14624 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
14625 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
14626 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
14627 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
14628 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
14629 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
14630 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
14631 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
14632 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
14633 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
14634 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
14635 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
14636 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
14637 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
14638 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
14639 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
14640 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
14641 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
14642 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
14643 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
14644 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
14645 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
14646 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
14647 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
14648 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
14649 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
14650 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
14651 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
14652 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
14653 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
14654 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
14655 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
14656 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
14657 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
14658 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
14659 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
14660 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
14661 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
14662 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
14663 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
14664 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
14665 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
14666 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
14667 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
14668 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
14669 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
14670 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
14671 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
14672 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
14673 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
14674 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
14675 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
14676 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
14677
14678
14679 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_OFFSET ( 0x0000007C )
14680
14681 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_OFFSET )
14682 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_ADDRESS ), (r) )
14683 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1_ADDRESS ), (v) )
14684
14685 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
14686 typedef struct
14687 {
14688         /* IH_CLASS_KEY_ERR */
14689         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14690
14691         /* IH_CLASS_KEY_SP */
14692         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14693
14694         /* IH_CLASS_KEY_5TPL_FLTR */
14695         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14696
14697         /* IH_CLASS_KEY_WAN_FLTR */
14698         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14699
14700         /* IH_CLASS_KEY_IP_ANYHIT */
14701         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14702
14703         /* IH_CLASS_KEY_IP_FLTR */
14704         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14705
14706         /* IH_CLASS_KEY_VID_ANYHIT */
14707         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14708
14709         /* IH_CLASS_KEY_VID_FLTR */
14710         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14711
14712         /* IH_CLASS_KEY_BC_FLTR */
14713         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14714
14715         /* IH_CLASS_KEY_MC_FLTR */
14716         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14717
14718         /* IH_CLASS_KEY_DA_ANYHIT */
14719         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14720
14721         /* IH_CLASS_KEY_DA_FLTR */
14722         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14723
14724         /* IH_CLASS_KEY_L4 */
14725         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14726
14727         /* IH_CLASS_KEY_L3 */
14728         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14729
14730         /* IH_CLASS_KEY_L2 */
14731         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14732 }
14733 __PACKING_ATTRIBUTE_STRUCT_END__
14734 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1 ;
14735 #else
14736 typedef struct
14737 {
14738         /* IH_CLASS_KEY_L2 */
14739         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14740
14741         /* IH_CLASS_KEY_L3 */
14742         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14743
14744         /* IH_CLASS_KEY_L4 */
14745         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14746
14747         /* IH_CLASS_KEY_DA_FLTR */
14748         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14749
14750         /* IH_CLASS_KEY_DA_ANYHIT */
14751         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14752
14753         /* IH_CLASS_KEY_MC_FLTR */
14754         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14755
14756         /* IH_CLASS_KEY_BC_FLTR */
14757         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14758
14759         /* IH_CLASS_KEY_VID_FLTR */
14760         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14761
14762         /* IH_CLASS_KEY_VID_ANYHIT */
14763         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14764
14765         /* IH_CLASS_KEY_IP_FLTR */
14766         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14767
14768         /* IH_CLASS_KEY_IP_ANYHIT */
14769         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14770
14771         /* IH_CLASS_KEY_WAN_FLTR */
14772         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14773
14774         /* IH_CLASS_KEY_5TPL_FLTR */
14775         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14776
14777         /* IH_CLASS_KEY_SP */
14778         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14779
14780         /* IH_CLASS_KEY_ERR */
14781         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14782 }
14783 __PACKING_ATTRIBUTE_STRUCT_END__
14784 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1 ;
14785 #endif
14786
14787 /*****************************************************************************************/
14788 /* IH_CLASS_KEY2                                                                         */
14789 /* IH Class - Key2 configuration    Note: used for IH class identification by Parser Cla */
14790 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
14791 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
14792 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
14793 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
14794 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
14795 /*****************************************************************************************/
14796
14797 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
14798 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
14799 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
14800 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
14801 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
14802 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
14803 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
14804 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
14805 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
14806 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
14807 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
14808 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
14809 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
14810 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
14811 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
14812 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
14813 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
14814 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
14815 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
14816 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
14817 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
14818 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
14819 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
14820 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
14821 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
14822 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
14823 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
14824 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
14825 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
14826 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
14827 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
14828 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
14829 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
14830 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
14831 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
14832 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
14833 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
14834 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
14835 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
14836 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
14837 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
14838 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
14839 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
14840 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
14841 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
14842 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
14843 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
14844 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
14845 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
14846 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
14847 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
14848 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
14849 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
14850 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
14851 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
14852 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
14853 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
14854 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
14855 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
14856 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
14857 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
14858 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
14859 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
14860 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
14861 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
14862 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
14863 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
14864 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
14865 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
14866 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
14867 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
14868 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
14869 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
14870 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
14871 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
14872 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
14873 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
14874 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
14875 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
14876 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
14877 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
14878 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
14879 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
14880 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
14881 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
14882 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
14883 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
14884 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
14885 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
14886 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
14887 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
14888 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
14889 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
14890 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
14891 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
14892 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
14893 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
14894 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
14895 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
14896 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
14897 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
14898 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
14899 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
14900
14901
14902 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_OFFSET ( 0x00000080 )
14903
14904 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_OFFSET )
14905 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_ADDRESS ), (r) )
14906 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2_ADDRESS ), (v) )
14907
14908 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
14909 typedef struct
14910 {
14911         /* IH_CLASS_KEY_ERR */
14912         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14913
14914         /* IH_CLASS_KEY_SP */
14915         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14916
14917         /* IH_CLASS_KEY_5TPL_FLTR */
14918         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14919
14920         /* IH_CLASS_KEY_WAN_FLTR */
14921         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14922
14923         /* IH_CLASS_KEY_IP_ANYHIT */
14924         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14925
14926         /* IH_CLASS_KEY_IP_FLTR */
14927         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14928
14929         /* IH_CLASS_KEY_VID_ANYHIT */
14930         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14931
14932         /* IH_CLASS_KEY_VID_FLTR */
14933         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14934
14935         /* IH_CLASS_KEY_BC_FLTR */
14936         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14937
14938         /* IH_CLASS_KEY_MC_FLTR */
14939         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14940
14941         /* IH_CLASS_KEY_DA_ANYHIT */
14942         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14943
14944         /* IH_CLASS_KEY_DA_FLTR */
14945         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14946
14947         /* IH_CLASS_KEY_L4 */
14948         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14949
14950         /* IH_CLASS_KEY_L3 */
14951         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14952
14953         /* IH_CLASS_KEY_L2 */
14954         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14955 }
14956 __PACKING_ATTRIBUTE_STRUCT_END__
14957 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2 ;
14958 #else
14959 typedef struct
14960 {
14961         /* IH_CLASS_KEY_L2 */
14962         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14963
14964         /* IH_CLASS_KEY_L3 */
14965         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14966
14967         /* IH_CLASS_KEY_L4 */
14968         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14969
14970         /* IH_CLASS_KEY_DA_FLTR */
14971         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14972
14973         /* IH_CLASS_KEY_DA_ANYHIT */
14974         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14975
14976         /* IH_CLASS_KEY_MC_FLTR */
14977         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14978
14979         /* IH_CLASS_KEY_BC_FLTR */
14980         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14981
14982         /* IH_CLASS_KEY_VID_FLTR */
14983         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14984
14985         /* IH_CLASS_KEY_VID_ANYHIT */
14986         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14987
14988         /* IH_CLASS_KEY_IP_FLTR */
14989         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14990
14991         /* IH_CLASS_KEY_IP_ANYHIT */
14992         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14993
14994         /* IH_CLASS_KEY_WAN_FLTR */
14995         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14996
14997         /* IH_CLASS_KEY_5TPL_FLTR */
14998         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
14999
15000         /* IH_CLASS_KEY_SP */
15001         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15002
15003         /* IH_CLASS_KEY_ERR */
15004         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15005 }
15006 __PACKING_ATTRIBUTE_STRUCT_END__
15007 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2 ;
15008 #endif
15009
15010 /*****************************************************************************************/
15011 /* IH_CLASS_KEY3                                                                         */
15012 /* IH Class - Key3 configuration    Note: used for IH class identification by Parser Cla */
15013 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
15014 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
15015 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
15016 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
15017 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
15018 /*****************************************************************************************/
15019
15020 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
15021 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
15022 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
15023 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
15024 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
15025 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
15026 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
15027 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
15028 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
15029 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
15030 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
15031 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
15032 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
15033 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
15034 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
15035 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
15036 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
15037 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
15038 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
15039 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
15040 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
15041 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15042 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
15043 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15044 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
15045 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
15046 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
15047 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
15048 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
15049 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
15050 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
15051 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
15052 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
15053 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
15054 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
15055 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
15056 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
15057 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
15058 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
15059 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
15060 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
15061 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
15062 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
15063 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
15064 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
15065 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
15066 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
15067 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
15068 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
15069 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15070 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
15071 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15072 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15073 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
15074 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15075 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15076 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
15077 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15078 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
15079 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
15080 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
15081 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
15082 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
15083 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
15084 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
15085 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
15086 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
15087 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
15088 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
15089 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
15090 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
15091 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
15092 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
15093 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
15094 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
15095 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
15096 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
15097 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
15098 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
15099 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
15100 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
15101 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
15102 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
15103 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
15104 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
15105 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
15106 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
15107 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
15108 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
15109 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
15110 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
15111 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
15112 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
15113 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
15114 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
15115 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
15116 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
15117 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
15118 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
15119 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
15120 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
15121 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
15122 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
15123
15124
15125 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_OFFSET ( 0x00000084 )
15126
15127 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_OFFSET )
15128 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_ADDRESS ), (r) )
15129 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3_ADDRESS ), (v) )
15130
15131 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
15132 typedef struct
15133 {
15134         /* IH_CLASS_KEY_ERR */
15135         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15136
15137         /* IH_CLASS_KEY_SP */
15138         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15139
15140         /* IH_CLASS_KEY_5TPL_FLTR */
15141         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15142
15143         /* IH_CLASS_KEY_WAN_FLTR */
15144         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15145
15146         /* IH_CLASS_KEY_IP_ANYHIT */
15147         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15148
15149         /* IH_CLASS_KEY_IP_FLTR */
15150         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15151
15152         /* IH_CLASS_KEY_VID_ANYHIT */
15153         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15154
15155         /* IH_CLASS_KEY_VID_FLTR */
15156         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15157
15158         /* IH_CLASS_KEY_BC_FLTR */
15159         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15160
15161         /* IH_CLASS_KEY_MC_FLTR */
15162         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15163
15164         /* IH_CLASS_KEY_DA_ANYHIT */
15165         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15166
15167         /* IH_CLASS_KEY_DA_FLTR */
15168         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15169
15170         /* IH_CLASS_KEY_L4 */
15171         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15172
15173         /* IH_CLASS_KEY_L3 */
15174         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15175
15176         /* IH_CLASS_KEY_L2 */
15177         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15178 }
15179 __PACKING_ATTRIBUTE_STRUCT_END__
15180 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3 ;
15181 #else
15182 typedef struct
15183 {
15184         /* IH_CLASS_KEY_L2 */
15185         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15186
15187         /* IH_CLASS_KEY_L3 */
15188         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15189
15190         /* IH_CLASS_KEY_L4 */
15191         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15192
15193         /* IH_CLASS_KEY_DA_FLTR */
15194         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15195
15196         /* IH_CLASS_KEY_DA_ANYHIT */
15197         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15198
15199         /* IH_CLASS_KEY_MC_FLTR */
15200         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15201
15202         /* IH_CLASS_KEY_BC_FLTR */
15203         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15204
15205         /* IH_CLASS_KEY_VID_FLTR */
15206         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15207
15208         /* IH_CLASS_KEY_VID_ANYHIT */
15209         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15210
15211         /* IH_CLASS_KEY_IP_FLTR */
15212         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15213
15214         /* IH_CLASS_KEY_IP_ANYHIT */
15215         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15216
15217         /* IH_CLASS_KEY_WAN_FLTR */
15218         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15219
15220         /* IH_CLASS_KEY_5TPL_FLTR */
15221         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15222
15223         /* IH_CLASS_KEY_SP */
15224         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15225
15226         /* IH_CLASS_KEY_ERR */
15227         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15228 }
15229 __PACKING_ATTRIBUTE_STRUCT_END__
15230 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3 ;
15231 #endif
15232
15233 /*****************************************************************************************/
15234 /* IH_CLASS_KEY4                                                                         */
15235 /* IH Class - Key4 configuration    Note: used for IH class identification by Parser Cla */
15236 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
15237 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
15238 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
15239 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
15240 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
15241 /*****************************************************************************************/
15242
15243 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
15244 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
15245 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
15246 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
15247 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
15248 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
15249 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
15250 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
15251 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
15252 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
15253 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
15254 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
15255 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
15256 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
15257 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
15258 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
15259 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
15260 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
15261 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
15262 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
15263 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
15264 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15265 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
15266 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15267 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
15268 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
15269 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
15270 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
15271 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
15272 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
15273 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
15274 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
15275 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
15276 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
15277 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
15278 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
15279 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
15280 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
15281 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
15282 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
15283 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
15284 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
15285 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
15286 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
15287 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
15288 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
15289 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
15290 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
15291 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
15292 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15293 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
15294 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15295 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15296 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
15297 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15298 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15299 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
15300 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15301 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
15302 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
15303 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
15304 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
15305 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
15306 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
15307 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
15308 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
15309 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
15310 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
15311 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
15312 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
15313 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
15314 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
15315 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
15316 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
15317 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
15318 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
15319 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
15320 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
15321 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
15322 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
15323 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
15324 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
15325 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
15326 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
15327 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
15328 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
15329 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
15330 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
15331 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
15332 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
15333 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
15334 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
15335 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
15336 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
15337 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
15338 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
15339 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
15340 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
15341 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
15342 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
15343 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
15344 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
15345 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
15346
15347
15348 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_OFFSET ( 0x00000088 )
15349
15350 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_OFFSET )
15351 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_ADDRESS ), (r) )
15352 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4_ADDRESS ), (v) )
15353
15354 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
15355 typedef struct
15356 {
15357         /* IH_CLASS_KEY_ERR */
15358         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15359
15360         /* IH_CLASS_KEY_SP */
15361         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15362
15363         /* IH_CLASS_KEY_5TPL_FLTR */
15364         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15365
15366         /* IH_CLASS_KEY_WAN_FLTR */
15367         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15368
15369         /* IH_CLASS_KEY_IP_ANYHIT */
15370         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15371
15372         /* IH_CLASS_KEY_IP_FLTR */
15373         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15374
15375         /* IH_CLASS_KEY_VID_ANYHIT */
15376         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15377
15378         /* IH_CLASS_KEY_VID_FLTR */
15379         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15380
15381         /* IH_CLASS_KEY_BC_FLTR */
15382         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15383
15384         /* IH_CLASS_KEY_MC_FLTR */
15385         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15386
15387         /* IH_CLASS_KEY_DA_ANYHIT */
15388         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15389
15390         /* IH_CLASS_KEY_DA_FLTR */
15391         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15392
15393         /* IH_CLASS_KEY_L4 */
15394         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15395
15396         /* IH_CLASS_KEY_L3 */
15397         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15398
15399         /* IH_CLASS_KEY_L2 */
15400         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15401 }
15402 __PACKING_ATTRIBUTE_STRUCT_END__
15403 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4 ;
15404 #else
15405 typedef struct
15406 {
15407         /* IH_CLASS_KEY_L2 */
15408         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15409
15410         /* IH_CLASS_KEY_L3 */
15411         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15412
15413         /* IH_CLASS_KEY_L4 */
15414         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15415
15416         /* IH_CLASS_KEY_DA_FLTR */
15417         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15418
15419         /* IH_CLASS_KEY_DA_ANYHIT */
15420         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15421
15422         /* IH_CLASS_KEY_MC_FLTR */
15423         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15424
15425         /* IH_CLASS_KEY_BC_FLTR */
15426         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15427
15428         /* IH_CLASS_KEY_VID_FLTR */
15429         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15430
15431         /* IH_CLASS_KEY_VID_ANYHIT */
15432         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15433
15434         /* IH_CLASS_KEY_IP_FLTR */
15435         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15436
15437         /* IH_CLASS_KEY_IP_ANYHIT */
15438         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15439
15440         /* IH_CLASS_KEY_WAN_FLTR */
15441         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15442
15443         /* IH_CLASS_KEY_5TPL_FLTR */
15444         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15445
15446         /* IH_CLASS_KEY_SP */
15447         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15448
15449         /* IH_CLASS_KEY_ERR */
15450         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15451 }
15452 __PACKING_ATTRIBUTE_STRUCT_END__
15453 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4 ;
15454 #endif
15455
15456 /*****************************************************************************************/
15457 /* IH_CLASS_KEY5                                                                         */
15458 /* IH Class - Key5 configuration    Note: used for IH class identification by Parser Cla */
15459 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
15460 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
15461 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
15462 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
15463 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
15464 /*****************************************************************************************/
15465
15466 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
15467 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
15468 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
15469 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
15470 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
15471 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
15472 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
15473 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
15474 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
15475 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
15476 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
15477 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
15478 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
15479 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
15480 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
15481 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
15482 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
15483 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
15484 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
15485 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
15486 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
15487 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15488 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
15489 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15490 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
15491 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
15492 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
15493 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
15494 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
15495 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
15496 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
15497 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
15498 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
15499 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
15500 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
15501 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
15502 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
15503 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
15504 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
15505 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
15506 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
15507 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
15508 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
15509 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
15510 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
15511 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
15512 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
15513 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
15514 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
15515 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15516 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
15517 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15518 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15519 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
15520 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15521 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15522 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
15523 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15524 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
15525 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
15526 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
15527 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
15528 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
15529 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
15530 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
15531 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
15532 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
15533 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
15534 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
15535 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
15536 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
15537 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
15538 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
15539 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
15540 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
15541 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
15542 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
15543 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
15544 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
15545 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
15546 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
15547 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
15548 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
15549 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
15550 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
15551 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
15552 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
15553 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
15554 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
15555 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
15556 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
15557 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
15558 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
15559 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
15560 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
15561 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
15562 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
15563 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
15564 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
15565 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
15566 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
15567 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
15568 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
15569
15570
15571 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_OFFSET ( 0x0000008C )
15572
15573 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_OFFSET )
15574 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_ADDRESS ), (r) )
15575 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5_ADDRESS ), (v) )
15576
15577 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
15578 typedef struct
15579 {
15580         /* IH_CLASS_KEY_ERR */
15581         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15582
15583         /* IH_CLASS_KEY_SP */
15584         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15585
15586         /* IH_CLASS_KEY_5TPL_FLTR */
15587         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15588
15589         /* IH_CLASS_KEY_WAN_FLTR */
15590         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15591
15592         /* IH_CLASS_KEY_IP_ANYHIT */
15593         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15594
15595         /* IH_CLASS_KEY_IP_FLTR */
15596         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15597
15598         /* IH_CLASS_KEY_VID_ANYHIT */
15599         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15600
15601         /* IH_CLASS_KEY_VID_FLTR */
15602         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15603
15604         /* IH_CLASS_KEY_BC_FLTR */
15605         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15606
15607         /* IH_CLASS_KEY_MC_FLTR */
15608         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15609
15610         /* IH_CLASS_KEY_DA_ANYHIT */
15611         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15612
15613         /* IH_CLASS_KEY_DA_FLTR */
15614         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15615
15616         /* IH_CLASS_KEY_L4 */
15617         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15618
15619         /* IH_CLASS_KEY_L3 */
15620         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15621
15622         /* IH_CLASS_KEY_L2 */
15623         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15624 }
15625 __PACKING_ATTRIBUTE_STRUCT_END__
15626 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5 ;
15627 #else
15628 typedef struct
15629 {
15630         /* IH_CLASS_KEY_L2 */
15631         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15632
15633         /* IH_CLASS_KEY_L3 */
15634         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15635
15636         /* IH_CLASS_KEY_L4 */
15637         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15638
15639         /* IH_CLASS_KEY_DA_FLTR */
15640         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15641
15642         /* IH_CLASS_KEY_DA_ANYHIT */
15643         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15644
15645         /* IH_CLASS_KEY_MC_FLTR */
15646         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15647
15648         /* IH_CLASS_KEY_BC_FLTR */
15649         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15650
15651         /* IH_CLASS_KEY_VID_FLTR */
15652         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15653
15654         /* IH_CLASS_KEY_VID_ANYHIT */
15655         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15656
15657         /* IH_CLASS_KEY_IP_FLTR */
15658         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15659
15660         /* IH_CLASS_KEY_IP_ANYHIT */
15661         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15662
15663         /* IH_CLASS_KEY_WAN_FLTR */
15664         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15665
15666         /* IH_CLASS_KEY_5TPL_FLTR */
15667         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15668
15669         /* IH_CLASS_KEY_SP */
15670         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15671
15672         /* IH_CLASS_KEY_ERR */
15673         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15674 }
15675 __PACKING_ATTRIBUTE_STRUCT_END__
15676 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5 ;
15677 #endif
15678
15679 /*****************************************************************************************/
15680 /* IH_CLASS_KEY6                                                                         */
15681 /* IH Class - Key6 configuration    Note: used for IH class identification by Parser Cla */
15682 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
15683 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
15684 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
15685 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
15686 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
15687 /*****************************************************************************************/
15688
15689 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
15690 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
15691 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
15692 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
15693 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
15694 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
15695 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
15696 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
15697 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
15698 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
15699 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
15700 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
15701 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
15702 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
15703 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
15704 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
15705 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
15706 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
15707 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
15708 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
15709 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
15710 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15711 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
15712 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15713 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
15714 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
15715 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
15716 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
15717 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
15718 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
15719 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
15720 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
15721 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
15722 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
15723 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
15724 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
15725 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
15726 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
15727 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
15728 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
15729 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
15730 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
15731 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
15732 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
15733 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
15734 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
15735 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
15736 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
15737 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
15738 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15739 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
15740 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15741 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15742 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
15743 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15744 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15745 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
15746 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15747 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
15748 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
15749 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
15750 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
15751 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
15752 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
15753 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
15754 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
15755 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
15756 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
15757 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
15758 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
15759 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
15760 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
15761 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
15762 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
15763 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
15764 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
15765 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
15766 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
15767 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
15768 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
15769 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
15770 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
15771 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
15772 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
15773 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
15774 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
15775 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
15776 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
15777 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
15778 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
15779 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
15780 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
15781 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
15782 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
15783 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
15784 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
15785 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
15786 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
15787 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
15788 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
15789 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
15790 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
15791 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
15792
15793
15794 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_OFFSET ( 0x00000090 )
15795
15796 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_OFFSET )
15797 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_ADDRESS ), (r) )
15798 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6_ADDRESS ), (v) )
15799
15800 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
15801 typedef struct
15802 {
15803         /* IH_CLASS_KEY_ERR */
15804         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15805
15806         /* IH_CLASS_KEY_SP */
15807         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15808
15809         /* IH_CLASS_KEY_5TPL_FLTR */
15810         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15811
15812         /* IH_CLASS_KEY_WAN_FLTR */
15813         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15814
15815         /* IH_CLASS_KEY_IP_ANYHIT */
15816         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15817
15818         /* IH_CLASS_KEY_IP_FLTR */
15819         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15820
15821         /* IH_CLASS_KEY_VID_ANYHIT */
15822         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15823
15824         /* IH_CLASS_KEY_VID_FLTR */
15825         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15826
15827         /* IH_CLASS_KEY_BC_FLTR */
15828         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15829
15830         /* IH_CLASS_KEY_MC_FLTR */
15831         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15832
15833         /* IH_CLASS_KEY_DA_ANYHIT */
15834         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15835
15836         /* IH_CLASS_KEY_DA_FLTR */
15837         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15838
15839         /* IH_CLASS_KEY_L4 */
15840         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15841
15842         /* IH_CLASS_KEY_L3 */
15843         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15844
15845         /* IH_CLASS_KEY_L2 */
15846         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15847 }
15848 __PACKING_ATTRIBUTE_STRUCT_END__
15849 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6 ;
15850 #else
15851 typedef struct
15852 {
15853         /* IH_CLASS_KEY_L2 */
15854         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15855
15856         /* IH_CLASS_KEY_L3 */
15857         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15858
15859         /* IH_CLASS_KEY_L4 */
15860         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15861
15862         /* IH_CLASS_KEY_DA_FLTR */
15863         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15864
15865         /* IH_CLASS_KEY_DA_ANYHIT */
15866         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15867
15868         /* IH_CLASS_KEY_MC_FLTR */
15869         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15870
15871         /* IH_CLASS_KEY_BC_FLTR */
15872         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15873
15874         /* IH_CLASS_KEY_VID_FLTR */
15875         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15876
15877         /* IH_CLASS_KEY_VID_ANYHIT */
15878         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15879
15880         /* IH_CLASS_KEY_IP_FLTR */
15881         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15882
15883         /* IH_CLASS_KEY_IP_ANYHIT */
15884         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15885
15886         /* IH_CLASS_KEY_WAN_FLTR */
15887         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15888
15889         /* IH_CLASS_KEY_5TPL_FLTR */
15890         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15891
15892         /* IH_CLASS_KEY_SP */
15893         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15894
15895         /* IH_CLASS_KEY_ERR */
15896         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
15897 }
15898 __PACKING_ATTRIBUTE_STRUCT_END__
15899 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6 ;
15900 #endif
15901
15902 /*****************************************************************************************/
15903 /* IH_CLASS_KEY7                                                                         */
15904 /* IH Class - Key7 configuration    Note: used for IH class identification by Parser Cla */
15905 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
15906 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
15907 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
15908 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
15909 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
15910 /*****************************************************************************************/
15911
15912 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
15913 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
15914 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
15915 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
15916 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
15917 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
15918 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
15919 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
15920 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
15921 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
15922 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
15923 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
15924 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
15925 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
15926 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
15927 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
15928 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
15929 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
15930 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
15931 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
15932 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
15933 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15934 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
15935 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15936 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
15937 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
15938 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
15939 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
15940 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
15941 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
15942 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
15943 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
15944 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
15945 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
15946 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
15947 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
15948 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
15949 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
15950 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
15951 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
15952 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
15953 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
15954 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
15955 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
15956 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
15957 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
15958 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
15959 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
15960 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
15961 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15962 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
15963 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15964 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
15965 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
15966 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
15967 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
15968 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
15969 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
15970 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
15971 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
15972 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
15973 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
15974 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
15975 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
15976 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
15977 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
15978 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
15979 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
15980 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
15981 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
15982 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
15983 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
15984 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
15985 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
15986 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
15987 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
15988 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
15989 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
15990 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
15991 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
15992 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
15993 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
15994 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
15995 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
15996 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
15997 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
15998 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
15999 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
16000 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
16001 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
16002 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
16003 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
16004 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
16005 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
16006 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
16007 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
16008 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
16009 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
16010 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
16011 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
16012 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
16013 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
16014 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
16015
16016
16017 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_OFFSET ( 0x00000094 )
16018
16019 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_OFFSET )
16020 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_ADDRESS ), (r) )
16021 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7_ADDRESS ), (v) )
16022
16023 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
16024 typedef struct
16025 {
16026         /* IH_CLASS_KEY_ERR */
16027         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16028
16029         /* IH_CLASS_KEY_SP */
16030         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16031
16032         /* IH_CLASS_KEY_5TPL_FLTR */
16033         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16034
16035         /* IH_CLASS_KEY_WAN_FLTR */
16036         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16037
16038         /* IH_CLASS_KEY_IP_ANYHIT */
16039         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16040
16041         /* IH_CLASS_KEY_IP_FLTR */
16042         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16043
16044         /* IH_CLASS_KEY_VID_ANYHIT */
16045         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16046
16047         /* IH_CLASS_KEY_VID_FLTR */
16048         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16049
16050         /* IH_CLASS_KEY_BC_FLTR */
16051         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16052
16053         /* IH_CLASS_KEY_MC_FLTR */
16054         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16055
16056         /* IH_CLASS_KEY_DA_ANYHIT */
16057         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16058
16059         /* IH_CLASS_KEY_DA_FLTR */
16060         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16061
16062         /* IH_CLASS_KEY_L4 */
16063         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16064
16065         /* IH_CLASS_KEY_L3 */
16066         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16067
16068         /* IH_CLASS_KEY_L2 */
16069         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16070 }
16071 __PACKING_ATTRIBUTE_STRUCT_END__
16072 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7 ;
16073 #else
16074 typedef struct
16075 {
16076         /* IH_CLASS_KEY_L2 */
16077         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16078
16079         /* IH_CLASS_KEY_L3 */
16080         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16081
16082         /* IH_CLASS_KEY_L4 */
16083         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16084
16085         /* IH_CLASS_KEY_DA_FLTR */
16086         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16087
16088         /* IH_CLASS_KEY_DA_ANYHIT */
16089         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16090
16091         /* IH_CLASS_KEY_MC_FLTR */
16092         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16093
16094         /* IH_CLASS_KEY_BC_FLTR */
16095         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16096
16097         /* IH_CLASS_KEY_VID_FLTR */
16098         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16099
16100         /* IH_CLASS_KEY_VID_ANYHIT */
16101         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16102
16103         /* IH_CLASS_KEY_IP_FLTR */
16104         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16105
16106         /* IH_CLASS_KEY_IP_ANYHIT */
16107         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16108
16109         /* IH_CLASS_KEY_WAN_FLTR */
16110         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16111
16112         /* IH_CLASS_KEY_5TPL_FLTR */
16113         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16114
16115         /* IH_CLASS_KEY_SP */
16116         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16117
16118         /* IH_CLASS_KEY_ERR */
16119         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16120 }
16121 __PACKING_ATTRIBUTE_STRUCT_END__
16122 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7 ;
16123 #endif
16124
16125 /*****************************************************************************************/
16126 /* IH_CLASS_KEY8                                                                         */
16127 /* IH Class - Key8 configuration    Note: used for IH class identification by Parser Cla */
16128 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
16129 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
16130 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
16131 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
16132 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
16133 /*****************************************************************************************/
16134
16135 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
16136 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
16137 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
16138 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
16139 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
16140 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
16141 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
16142 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
16143 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
16144 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
16145 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
16146 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
16147 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
16148 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
16149 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
16150 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
16151 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
16152 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
16153 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
16154 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
16155 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
16156 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16157 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
16158 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16159 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
16160 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
16161 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
16162 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
16163 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
16164 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
16165 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
16166 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
16167 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
16168 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
16169 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
16170 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
16171 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
16172 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
16173 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
16174 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
16175 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
16176 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
16177 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
16178 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
16179 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
16180 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
16181 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
16182 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
16183 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
16184 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16185 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
16186 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16187 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16188 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
16189 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16190 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16191 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
16192 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16193 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
16194 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
16195 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
16196 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
16197 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
16198 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
16199 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
16200 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
16201 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
16202 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
16203 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
16204 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
16205 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
16206 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
16207 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
16208 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
16209 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
16210 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
16211 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
16212 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
16213 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
16214 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
16215 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
16216 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
16217 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
16218 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
16219 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
16220 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
16221 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
16222 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
16223 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
16224 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
16225 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
16226 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
16227 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
16228 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
16229 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
16230 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
16231 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
16232 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
16233 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
16234 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
16235 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
16236 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
16237 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
16238
16239
16240 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_OFFSET ( 0x00000098 )
16241
16242 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_OFFSET )
16243 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_ADDRESS ), (r) )
16244 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8_ADDRESS ), (v) )
16245
16246 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
16247 typedef struct
16248 {
16249         /* IH_CLASS_KEY_ERR */
16250         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16251
16252         /* IH_CLASS_KEY_SP */
16253         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16254
16255         /* IH_CLASS_KEY_5TPL_FLTR */
16256         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16257
16258         /* IH_CLASS_KEY_WAN_FLTR */
16259         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16260
16261         /* IH_CLASS_KEY_IP_ANYHIT */
16262         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16263
16264         /* IH_CLASS_KEY_IP_FLTR */
16265         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16266
16267         /* IH_CLASS_KEY_VID_ANYHIT */
16268         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16269
16270         /* IH_CLASS_KEY_VID_FLTR */
16271         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16272
16273         /* IH_CLASS_KEY_BC_FLTR */
16274         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16275
16276         /* IH_CLASS_KEY_MC_FLTR */
16277         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16278
16279         /* IH_CLASS_KEY_DA_ANYHIT */
16280         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16281
16282         /* IH_CLASS_KEY_DA_FLTR */
16283         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16284
16285         /* IH_CLASS_KEY_L4 */
16286         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16287
16288         /* IH_CLASS_KEY_L3 */
16289         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16290
16291         /* IH_CLASS_KEY_L2 */
16292         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16293 }
16294 __PACKING_ATTRIBUTE_STRUCT_END__
16295 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8 ;
16296 #else
16297 typedef struct
16298 {
16299         /* IH_CLASS_KEY_L2 */
16300         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16301
16302         /* IH_CLASS_KEY_L3 */
16303         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16304
16305         /* IH_CLASS_KEY_L4 */
16306         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16307
16308         /* IH_CLASS_KEY_DA_FLTR */
16309         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16310
16311         /* IH_CLASS_KEY_DA_ANYHIT */
16312         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16313
16314         /* IH_CLASS_KEY_MC_FLTR */
16315         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16316
16317         /* IH_CLASS_KEY_BC_FLTR */
16318         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16319
16320         /* IH_CLASS_KEY_VID_FLTR */
16321         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16322
16323         /* IH_CLASS_KEY_VID_ANYHIT */
16324         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16325
16326         /* IH_CLASS_KEY_IP_FLTR */
16327         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16328
16329         /* IH_CLASS_KEY_IP_ANYHIT */
16330         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16331
16332         /* IH_CLASS_KEY_WAN_FLTR */
16333         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16334
16335         /* IH_CLASS_KEY_5TPL_FLTR */
16336         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16337
16338         /* IH_CLASS_KEY_SP */
16339         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16340
16341         /* IH_CLASS_KEY_ERR */
16342         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16343 }
16344 __PACKING_ATTRIBUTE_STRUCT_END__
16345 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8 ;
16346 #endif
16347
16348 /*****************************************************************************************/
16349 /* IH_CLASS_KEY9                                                                         */
16350 /* IH Class - Key9 configuration    Note: used for IH class identification by Parser Cla */
16351 /* ssifier, based on the Parser Summary Word comparison. Per each class there is a KEY c */
16352 /* onfiguration and MASK that applied on the Parser Sumary word. If the match based on K */
16353 /* EY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header De */
16354 /* scriptor upon to override enable bit. The priority is always to lower Class ID (for e */
16355 /* xample: if Class 3, 4 and 15 has match - Class 3 is choosen.                          */
16356 /*****************************************************************************************/
16357
16358 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
16359 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
16360 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
16361 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
16362 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
16363 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
16364 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
16365 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
16366 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
16367 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
16368 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
16369 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
16370 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
16371 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
16372 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
16373 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
16374 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
16375 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
16376 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
16377 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
16378 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
16379 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16380 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
16381 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16382 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
16383 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
16384 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
16385 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
16386 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
16387 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
16388 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
16389 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
16390 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
16391 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
16392 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
16393 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
16394 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
16395 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
16396 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
16397 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
16398 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
16399 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
16400 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
16401 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
16402 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
16403 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
16404 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
16405 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
16406 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
16407 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16408 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
16409 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16410 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16411 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
16412 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16413 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16414 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
16415 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16416 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
16417 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
16418 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
16419 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
16420 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
16421 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
16422 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
16423 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
16424 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
16425 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
16426 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
16427 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
16428 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
16429 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
16430 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
16431 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
16432 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
16433 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
16434 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
16435 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
16436 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
16437 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
16438 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
16439 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
16440 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
16441 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
16442 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
16443 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
16444 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
16445 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
16446 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
16447 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
16448 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
16449 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
16450 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
16451 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
16452 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
16453 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
16454 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
16455 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
16456 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
16457 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
16458 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
16459 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
16460 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
16461
16462
16463 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_OFFSET ( 0x0000009C )
16464
16465 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_OFFSET )
16466 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_ADDRESS ), (r) )
16467 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9_ADDRESS ), (v) )
16468
16469 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
16470 typedef struct
16471 {
16472         /* IH_CLASS_KEY_ERR */
16473         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16474
16475         /* IH_CLASS_KEY_SP */
16476         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16477
16478         /* IH_CLASS_KEY_5TPL_FLTR */
16479         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16480
16481         /* IH_CLASS_KEY_WAN_FLTR */
16482         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16483
16484         /* IH_CLASS_KEY_IP_ANYHIT */
16485         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16486
16487         /* IH_CLASS_KEY_IP_FLTR */
16488         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16489
16490         /* IH_CLASS_KEY_VID_ANYHIT */
16491         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16492
16493         /* IH_CLASS_KEY_VID_FLTR */
16494         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16495
16496         /* IH_CLASS_KEY_BC_FLTR */
16497         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16498
16499         /* IH_CLASS_KEY_MC_FLTR */
16500         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16501
16502         /* IH_CLASS_KEY_DA_ANYHIT */
16503         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16504
16505         /* IH_CLASS_KEY_DA_FLTR */
16506         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16507
16508         /* IH_CLASS_KEY_L4 */
16509         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16510
16511         /* IH_CLASS_KEY_L3 */
16512         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16513
16514         /* IH_CLASS_KEY_L2 */
16515         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16516 }
16517 __PACKING_ATTRIBUTE_STRUCT_END__
16518 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9 ;
16519 #else
16520 typedef struct
16521 {
16522         /* IH_CLASS_KEY_L2 */
16523         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16524
16525         /* IH_CLASS_KEY_L3 */
16526         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16527
16528         /* IH_CLASS_KEY_L4 */
16529         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16530
16531         /* IH_CLASS_KEY_DA_FLTR */
16532         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16533
16534         /* IH_CLASS_KEY_DA_ANYHIT */
16535         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16536
16537         /* IH_CLASS_KEY_MC_FLTR */
16538         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16539
16540         /* IH_CLASS_KEY_BC_FLTR */
16541         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16542
16543         /* IH_CLASS_KEY_VID_FLTR */
16544         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16545
16546         /* IH_CLASS_KEY_VID_ANYHIT */
16547         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16548
16549         /* IH_CLASS_KEY_IP_FLTR */
16550         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16551
16552         /* IH_CLASS_KEY_IP_ANYHIT */
16553         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16554
16555         /* IH_CLASS_KEY_WAN_FLTR */
16556         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16557
16558         /* IH_CLASS_KEY_5TPL_FLTR */
16559         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16560
16561         /* IH_CLASS_KEY_SP */
16562         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16563
16564         /* IH_CLASS_KEY_ERR */
16565         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16566 }
16567 __PACKING_ATTRIBUTE_STRUCT_END__
16568 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9 ;
16569 #endif
16570
16571 /*****************************************************************************************/
16572 /* IH_CLASS_KEY10                                                                        */
16573 /* IH Class - Key10 configuration    Note: used for IH class identification by Parser Cl */
16574 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
16575 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
16576 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
16577 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
16578 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
16579 /*****************************************************************************************/
16580
16581 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
16582 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
16583 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
16584 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
16585 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
16586 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
16587 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
16588 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
16589 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
16590 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
16591 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
16592 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
16593 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
16594 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
16595 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
16596 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
16597 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
16598 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
16599 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
16600 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
16601 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
16602 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16603 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
16604 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16605 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
16606 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
16607 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
16608 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
16609 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
16610 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
16611 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
16612 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
16613 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
16614 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
16615 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
16616 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
16617 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
16618 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
16619 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
16620 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
16621 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
16622 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
16623 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
16624 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
16625 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
16626 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
16627 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
16628 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
16629 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
16630 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16631 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
16632 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16633 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16634 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
16635 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16636 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16637 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
16638 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16639 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
16640 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
16641 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
16642 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
16643 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
16644 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
16645 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
16646 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
16647 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
16648 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
16649 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
16650 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
16651 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
16652 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
16653 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
16654 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
16655 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
16656 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
16657 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
16658 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
16659 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
16660 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
16661 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
16662 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
16663 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
16664 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
16665 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
16666 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
16667 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
16668 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
16669 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
16670 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
16671 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
16672 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
16673 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
16674 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
16675 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
16676 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
16677 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
16678 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
16679 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
16680 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
16681 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
16682 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
16683 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
16684
16685
16686 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_OFFSET ( 0x00000100 )
16687
16688 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_OFFSET )
16689 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_ADDRESS ), (r) )
16690 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10_ADDRESS ), (v) )
16691
16692 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
16693 typedef struct
16694 {
16695         /* IH_CLASS_KEY_ERR */
16696         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16697
16698         /* IH_CLASS_KEY_SP */
16699         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16700
16701         /* IH_CLASS_KEY_5TPL_FLTR */
16702         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16703
16704         /* IH_CLASS_KEY_WAN_FLTR */
16705         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16706
16707         /* IH_CLASS_KEY_IP_ANYHIT */
16708         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16709
16710         /* IH_CLASS_KEY_IP_FLTR */
16711         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16712
16713         /* IH_CLASS_KEY_VID_ANYHIT */
16714         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16715
16716         /* IH_CLASS_KEY_VID_FLTR */
16717         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16718
16719         /* IH_CLASS_KEY_BC_FLTR */
16720         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16721
16722         /* IH_CLASS_KEY_MC_FLTR */
16723         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16724
16725         /* IH_CLASS_KEY_DA_ANYHIT */
16726         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16727
16728         /* IH_CLASS_KEY_DA_FLTR */
16729         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16730
16731         /* IH_CLASS_KEY_L4 */
16732         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16733
16734         /* IH_CLASS_KEY_L3 */
16735         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16736
16737         /* IH_CLASS_KEY_L2 */
16738         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16739 }
16740 __PACKING_ATTRIBUTE_STRUCT_END__
16741 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10 ;
16742 #else
16743 typedef struct
16744 {
16745         /* IH_CLASS_KEY_L2 */
16746         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16747
16748         /* IH_CLASS_KEY_L3 */
16749         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16750
16751         /* IH_CLASS_KEY_L4 */
16752         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16753
16754         /* IH_CLASS_KEY_DA_FLTR */
16755         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16756
16757         /* IH_CLASS_KEY_DA_ANYHIT */
16758         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16759
16760         /* IH_CLASS_KEY_MC_FLTR */
16761         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16762
16763         /* IH_CLASS_KEY_BC_FLTR */
16764         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16765
16766         /* IH_CLASS_KEY_VID_FLTR */
16767         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16768
16769         /* IH_CLASS_KEY_VID_ANYHIT */
16770         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16771
16772         /* IH_CLASS_KEY_IP_FLTR */
16773         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16774
16775         /* IH_CLASS_KEY_IP_ANYHIT */
16776         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16777
16778         /* IH_CLASS_KEY_WAN_FLTR */
16779         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16780
16781         /* IH_CLASS_KEY_5TPL_FLTR */
16782         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16783
16784         /* IH_CLASS_KEY_SP */
16785         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16786
16787         /* IH_CLASS_KEY_ERR */
16788         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16789 }
16790 __PACKING_ATTRIBUTE_STRUCT_END__
16791 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10 ;
16792 #endif
16793
16794 /*****************************************************************************************/
16795 /* IH_CLASS_KEY11                                                                        */
16796 /* IH Class - Key11 configuration    Note: used for IH class identification by Parser Cl */
16797 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
16798 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
16799 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
16800 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
16801 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
16802 /*****************************************************************************************/
16803
16804 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
16805 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
16806 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
16807 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
16808 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
16809 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
16810 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
16811 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
16812 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
16813 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
16814 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
16815 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
16816 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
16817 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
16818 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
16819 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
16820 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
16821 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
16822 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
16823 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
16824 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
16825 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16826 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
16827 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16828 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
16829 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
16830 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
16831 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
16832 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
16833 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
16834 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
16835 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
16836 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
16837 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
16838 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
16839 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
16840 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
16841 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
16842 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
16843 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
16844 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
16845 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
16846 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
16847 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
16848 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
16849 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
16850 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
16851 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
16852 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
16853 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16854 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
16855 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16856 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
16857 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
16858 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
16859 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
16860 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
16861 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
16862 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
16863 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
16864 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
16865 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
16866 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
16867 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
16868 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
16869 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
16870 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
16871 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
16872 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
16873 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
16874 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
16875 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
16876 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
16877 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
16878 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
16879 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
16880 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
16881 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
16882 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
16883 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
16884 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
16885 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
16886 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
16887 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
16888 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
16889 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
16890 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
16891 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
16892 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
16893 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
16894 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
16895 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
16896 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
16897 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
16898 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
16899 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
16900 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
16901 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
16902 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
16903 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
16904 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
16905 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
16906 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
16907
16908
16909 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_OFFSET ( 0x00000104 )
16910
16911 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_OFFSET )
16912 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_ADDRESS ), (r) )
16913 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11_ADDRESS ), (v) )
16914
16915 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
16916 typedef struct
16917 {
16918         /* IH_CLASS_KEY_ERR */
16919         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16920
16921         /* IH_CLASS_KEY_SP */
16922         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16923
16924         /* IH_CLASS_KEY_5TPL_FLTR */
16925         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16926
16927         /* IH_CLASS_KEY_WAN_FLTR */
16928         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16929
16930         /* IH_CLASS_KEY_IP_ANYHIT */
16931         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16932
16933         /* IH_CLASS_KEY_IP_FLTR */
16934         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16935
16936         /* IH_CLASS_KEY_VID_ANYHIT */
16937         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16938
16939         /* IH_CLASS_KEY_VID_FLTR */
16940         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16941
16942         /* IH_CLASS_KEY_BC_FLTR */
16943         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16944
16945         /* IH_CLASS_KEY_MC_FLTR */
16946         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16947
16948         /* IH_CLASS_KEY_DA_ANYHIT */
16949         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16950
16951         /* IH_CLASS_KEY_DA_FLTR */
16952         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16953
16954         /* IH_CLASS_KEY_L4 */
16955         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16956
16957         /* IH_CLASS_KEY_L3 */
16958         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16959
16960         /* IH_CLASS_KEY_L2 */
16961         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16962 }
16963 __PACKING_ATTRIBUTE_STRUCT_END__
16964 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11 ;
16965 #else
16966 typedef struct
16967 {
16968         /* IH_CLASS_KEY_L2 */
16969         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16970
16971         /* IH_CLASS_KEY_L3 */
16972         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16973
16974         /* IH_CLASS_KEY_L4 */
16975         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16976
16977         /* IH_CLASS_KEY_DA_FLTR */
16978         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16979
16980         /* IH_CLASS_KEY_DA_ANYHIT */
16981         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16982
16983         /* IH_CLASS_KEY_MC_FLTR */
16984         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16985
16986         /* IH_CLASS_KEY_BC_FLTR */
16987         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16988
16989         /* IH_CLASS_KEY_VID_FLTR */
16990         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16991
16992         /* IH_CLASS_KEY_VID_ANYHIT */
16993         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16994
16995         /* IH_CLASS_KEY_IP_FLTR */
16996         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
16997
16998         /* IH_CLASS_KEY_IP_ANYHIT */
16999         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17000
17001         /* IH_CLASS_KEY_WAN_FLTR */
17002         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17003
17004         /* IH_CLASS_KEY_5TPL_FLTR */
17005         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17006
17007         /* IH_CLASS_KEY_SP */
17008         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17009
17010         /* IH_CLASS_KEY_ERR */
17011         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17012 }
17013 __PACKING_ATTRIBUTE_STRUCT_END__
17014 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11 ;
17015 #endif
17016
17017 /*****************************************************************************************/
17018 /* IH_CLASS_KEY12                                                                        */
17019 /* IH Class - Key12 configuration    Note: used for IH class identification by Parser Cl */
17020 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
17021 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
17022 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
17023 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
17024 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
17025 /*****************************************************************************************/
17026
17027 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
17028 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
17029 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
17030 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
17031 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
17032 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
17033 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
17034 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
17035 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
17036 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
17037 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
17038 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
17039 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
17040 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
17041 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
17042 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
17043 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
17044 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
17045 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
17046 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
17047 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
17048 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17049 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
17050 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17051 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
17052 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
17053 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
17054 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
17055 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
17056 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
17057 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
17058 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
17059 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
17060 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
17061 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
17062 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
17063 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
17064 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
17065 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
17066 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
17067 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
17068 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
17069 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
17070 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
17071 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
17072 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
17073 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
17074 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
17075 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
17076 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17077 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
17078 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17079 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17080 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
17081 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17082 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17083 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
17084 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17085 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
17086 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
17087 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
17088 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
17089 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
17090 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
17091 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
17092 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
17093 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
17094 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
17095 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
17096 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
17097 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
17098 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
17099 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
17100 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
17101 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
17102 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
17103 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
17104 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
17105 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
17106 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
17107 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
17108 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
17109 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
17110 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
17111 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
17112 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
17113 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
17114 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
17115 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
17116 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
17117 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
17118 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
17119 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
17120 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
17121 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
17122 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
17123 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
17124 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
17125 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
17126 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
17127 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
17128 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
17129 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
17130
17131
17132 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_OFFSET ( 0x00000108 )
17133
17134 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_OFFSET )
17135 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_ADDRESS ), (r) )
17136 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12_ADDRESS ), (v) )
17137
17138 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
17139 typedef struct
17140 {
17141         /* IH_CLASS_KEY_ERR */
17142         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17143
17144         /* IH_CLASS_KEY_SP */
17145         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17146
17147         /* IH_CLASS_KEY_5TPL_FLTR */
17148         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17149
17150         /* IH_CLASS_KEY_WAN_FLTR */
17151         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17152
17153         /* IH_CLASS_KEY_IP_ANYHIT */
17154         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17155
17156         /* IH_CLASS_KEY_IP_FLTR */
17157         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17158
17159         /* IH_CLASS_KEY_VID_ANYHIT */
17160         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17161
17162         /* IH_CLASS_KEY_VID_FLTR */
17163         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17164
17165         /* IH_CLASS_KEY_BC_FLTR */
17166         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17167
17168         /* IH_CLASS_KEY_MC_FLTR */
17169         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17170
17171         /* IH_CLASS_KEY_DA_ANYHIT */
17172         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17173
17174         /* IH_CLASS_KEY_DA_FLTR */
17175         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17176
17177         /* IH_CLASS_KEY_L4 */
17178         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17179
17180         /* IH_CLASS_KEY_L3 */
17181         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17182
17183         /* IH_CLASS_KEY_L2 */
17184         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17185 }
17186 __PACKING_ATTRIBUTE_STRUCT_END__
17187 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12 ;
17188 #else
17189 typedef struct
17190 {
17191         /* IH_CLASS_KEY_L2 */
17192         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17193
17194         /* IH_CLASS_KEY_L3 */
17195         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17196
17197         /* IH_CLASS_KEY_L4 */
17198         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17199
17200         /* IH_CLASS_KEY_DA_FLTR */
17201         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17202
17203         /* IH_CLASS_KEY_DA_ANYHIT */
17204         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17205
17206         /* IH_CLASS_KEY_MC_FLTR */
17207         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17208
17209         /* IH_CLASS_KEY_BC_FLTR */
17210         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17211
17212         /* IH_CLASS_KEY_VID_FLTR */
17213         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17214
17215         /* IH_CLASS_KEY_VID_ANYHIT */
17216         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17217
17218         /* IH_CLASS_KEY_IP_FLTR */
17219         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17220
17221         /* IH_CLASS_KEY_IP_ANYHIT */
17222         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17223
17224         /* IH_CLASS_KEY_WAN_FLTR */
17225         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17226
17227         /* IH_CLASS_KEY_5TPL_FLTR */
17228         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17229
17230         /* IH_CLASS_KEY_SP */
17231         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17232
17233         /* IH_CLASS_KEY_ERR */
17234         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17235 }
17236 __PACKING_ATTRIBUTE_STRUCT_END__
17237 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12 ;
17238 #endif
17239
17240 /*****************************************************************************************/
17241 /* IH_CLASS_KEY13                                                                        */
17242 /* IH Class - Key13 configuration    Note: used for IH class identification by Parser Cl */
17243 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
17244 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
17245 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
17246 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
17247 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
17248 /*****************************************************************************************/
17249
17250 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
17251 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
17252 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
17253 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
17254 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
17255 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
17256 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
17257 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
17258 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
17259 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
17260 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
17261 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
17262 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
17263 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
17264 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
17265 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
17266 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
17267 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
17268 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
17269 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
17270 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
17271 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17272 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
17273 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17274 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
17275 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
17276 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
17277 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
17278 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
17279 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
17280 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
17281 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
17282 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
17283 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
17284 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
17285 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
17286 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
17287 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
17288 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
17289 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
17290 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
17291 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
17292 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
17293 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
17294 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
17295 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
17296 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
17297 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
17298 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
17299 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17300 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
17301 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17302 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17303 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
17304 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17305 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17306 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
17307 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17308 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
17309 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
17310 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
17311 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
17312 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
17313 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
17314 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
17315 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
17316 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
17317 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
17318 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
17319 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
17320 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
17321 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
17322 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
17323 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
17324 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
17325 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
17326 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
17327 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
17328 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
17329 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
17330 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
17331 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
17332 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
17333 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
17334 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
17335 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
17336 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
17337 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
17338 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
17339 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
17340 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
17341 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
17342 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
17343 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
17344 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
17345 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
17346 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
17347 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
17348 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
17349 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
17350 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
17351 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
17352 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
17353
17354
17355 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_OFFSET ( 0x0000010C )
17356
17357 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_OFFSET )
17358 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_ADDRESS ), (r) )
17359 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13_ADDRESS ), (v) )
17360
17361 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
17362 typedef struct
17363 {
17364         /* IH_CLASS_KEY_ERR */
17365         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17366
17367         /* IH_CLASS_KEY_SP */
17368         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17369
17370         /* IH_CLASS_KEY_5TPL_FLTR */
17371         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17372
17373         /* IH_CLASS_KEY_WAN_FLTR */
17374         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17375
17376         /* IH_CLASS_KEY_IP_ANYHIT */
17377         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17378
17379         /* IH_CLASS_KEY_IP_FLTR */
17380         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17381
17382         /* IH_CLASS_KEY_VID_ANYHIT */
17383         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17384
17385         /* IH_CLASS_KEY_VID_FLTR */
17386         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17387
17388         /* IH_CLASS_KEY_BC_FLTR */
17389         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17390
17391         /* IH_CLASS_KEY_MC_FLTR */
17392         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17393
17394         /* IH_CLASS_KEY_DA_ANYHIT */
17395         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17396
17397         /* IH_CLASS_KEY_DA_FLTR */
17398         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17399
17400         /* IH_CLASS_KEY_L4 */
17401         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17402
17403         /* IH_CLASS_KEY_L3 */
17404         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17405
17406         /* IH_CLASS_KEY_L2 */
17407         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17408 }
17409 __PACKING_ATTRIBUTE_STRUCT_END__
17410 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13 ;
17411 #else
17412 typedef struct
17413 {
17414         /* IH_CLASS_KEY_L2 */
17415         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17416
17417         /* IH_CLASS_KEY_L3 */
17418         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17419
17420         /* IH_CLASS_KEY_L4 */
17421         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17422
17423         /* IH_CLASS_KEY_DA_FLTR */
17424         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17425
17426         /* IH_CLASS_KEY_DA_ANYHIT */
17427         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17428
17429         /* IH_CLASS_KEY_MC_FLTR */
17430         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17431
17432         /* IH_CLASS_KEY_BC_FLTR */
17433         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17434
17435         /* IH_CLASS_KEY_VID_FLTR */
17436         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17437
17438         /* IH_CLASS_KEY_VID_ANYHIT */
17439         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17440
17441         /* IH_CLASS_KEY_IP_FLTR */
17442         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17443
17444         /* IH_CLASS_KEY_IP_ANYHIT */
17445         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17446
17447         /* IH_CLASS_KEY_WAN_FLTR */
17448         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17449
17450         /* IH_CLASS_KEY_5TPL_FLTR */
17451         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17452
17453         /* IH_CLASS_KEY_SP */
17454         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17455
17456         /* IH_CLASS_KEY_ERR */
17457         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17458 }
17459 __PACKING_ATTRIBUTE_STRUCT_END__
17460 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13 ;
17461 #endif
17462
17463 /*****************************************************************************************/
17464 /* IH_CLASS_KEY14                                                                        */
17465 /* IH Class - Key14 configuration    Note: used for IH class identification by Parser Cl */
17466 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
17467 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
17468 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
17469 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
17470 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
17471 /*****************************************************************************************/
17472
17473 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
17474 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
17475 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
17476 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
17477 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
17478 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
17479 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
17480 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
17481 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
17482 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
17483 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
17484 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
17485 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
17486 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
17487 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
17488 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
17489 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
17490 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
17491 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
17492 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
17493 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
17494 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17495 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
17496 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17497 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
17498 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
17499 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
17500 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
17501 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
17502 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
17503 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
17504 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
17505 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
17506 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
17507 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
17508 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
17509 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
17510 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
17511 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
17512 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
17513 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
17514 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
17515 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
17516 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
17517 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
17518 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
17519 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
17520 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
17521 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
17522 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17523 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
17524 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17525 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17526 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
17527 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17528 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17529 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
17530 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17531 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
17532 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
17533 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
17534 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
17535 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
17536 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
17537 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
17538 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
17539 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
17540 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
17541 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
17542 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
17543 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
17544 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
17545 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
17546 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
17547 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
17548 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
17549 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
17550 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
17551 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
17552 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
17553 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
17554 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
17555 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
17556 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
17557 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
17558 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
17559 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
17560 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
17561 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
17562 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
17563 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
17564 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
17565 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
17566 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
17567 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
17568 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
17569 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
17570 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
17571 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
17572 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
17573 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
17574 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
17575 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
17576
17577
17578 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_OFFSET ( 0x00000110 )
17579
17580 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_OFFSET )
17581 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_ADDRESS ), (r) )
17582 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14_ADDRESS ), (v) )
17583
17584 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
17585 typedef struct
17586 {
17587         /* IH_CLASS_KEY_ERR */
17588         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17589
17590         /* IH_CLASS_KEY_SP */
17591         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17592
17593         /* IH_CLASS_KEY_5TPL_FLTR */
17594         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17595
17596         /* IH_CLASS_KEY_WAN_FLTR */
17597         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17598
17599         /* IH_CLASS_KEY_IP_ANYHIT */
17600         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17601
17602         /* IH_CLASS_KEY_IP_FLTR */
17603         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17604
17605         /* IH_CLASS_KEY_VID_ANYHIT */
17606         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17607
17608         /* IH_CLASS_KEY_VID_FLTR */
17609         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17610
17611         /* IH_CLASS_KEY_BC_FLTR */
17612         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17613
17614         /* IH_CLASS_KEY_MC_FLTR */
17615         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17616
17617         /* IH_CLASS_KEY_DA_ANYHIT */
17618         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17619
17620         /* IH_CLASS_KEY_DA_FLTR */
17621         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17622
17623         /* IH_CLASS_KEY_L4 */
17624         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17625
17626         /* IH_CLASS_KEY_L3 */
17627         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17628
17629         /* IH_CLASS_KEY_L2 */
17630         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17631 }
17632 __PACKING_ATTRIBUTE_STRUCT_END__
17633 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14 ;
17634 #else
17635 typedef struct
17636 {
17637         /* IH_CLASS_KEY_L2 */
17638         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17639
17640         /* IH_CLASS_KEY_L3 */
17641         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17642
17643         /* IH_CLASS_KEY_L4 */
17644         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17645
17646         /* IH_CLASS_KEY_DA_FLTR */
17647         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17648
17649         /* IH_CLASS_KEY_DA_ANYHIT */
17650         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17651
17652         /* IH_CLASS_KEY_MC_FLTR */
17653         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17654
17655         /* IH_CLASS_KEY_BC_FLTR */
17656         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17657
17658         /* IH_CLASS_KEY_VID_FLTR */
17659         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17660
17661         /* IH_CLASS_KEY_VID_ANYHIT */
17662         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17663
17664         /* IH_CLASS_KEY_IP_FLTR */
17665         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17666
17667         /* IH_CLASS_KEY_IP_ANYHIT */
17668         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17669
17670         /* IH_CLASS_KEY_WAN_FLTR */
17671         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17672
17673         /* IH_CLASS_KEY_5TPL_FLTR */
17674         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17675
17676         /* IH_CLASS_KEY_SP */
17677         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17678
17679         /* IH_CLASS_KEY_ERR */
17680         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17681 }
17682 __PACKING_ATTRIBUTE_STRUCT_END__
17683 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14 ;
17684 #endif
17685
17686 /*****************************************************************************************/
17687 /* IH_CLASS_KEY15                                                                        */
17688 /* IH Class - Key15 configuration    Note: used for IH class identification by Parser Cl */
17689 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
17690 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
17691 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
17692 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
17693 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
17694 /*****************************************************************************************/
17695
17696 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_ERR_NO_ERROR_VALUE                         ( 0x0 )
17697 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_ERR_ERROR_VALUE                            ( 0x1 )
17698 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_ERR_ERROR_VALUE_RESET_VALUE                ( 0x1 )
17699 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH0_PORT_VALUE                         ( 0x0 )
17700 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH1_PORT_VALUE                         ( 0x1 )
17701 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH2_PORT_VALUE                         ( 0x2 )
17702 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH3_PORT_VALUE                         ( 0x3 )
17703 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_ETH4_PORT_VALUE                         ( 0x4 )
17704 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_GPON_PORT_VALUE                         ( 0x5 )
17705 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RNRA_PORT_VALUE                         ( 0x6 )
17706 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_PCIE0_PORT_VALUE                        ( 0x7 )
17707 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_PCIE1_PORT_VALUE                        ( 0x8 )
17708 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RNRB_PORT_VALUE                         ( 0xE )
17709 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE                       ( 0x1F )
17710 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_SP_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x1F )
17711 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_5TPL_FLTR_NO_HIT_VALUE                     ( 0x0 )
17712 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE                        ( 0x1 )
17713 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_5TPL_FLTR_HIT_VALUE_RESET_VALUE            ( 0x1 )
17714 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_WAN_FLTR_NO_HIT_VALUE                      ( 0x0 )
17715 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE                         ( 0x1 )
17716 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_WAN_FLTR_HIT_VALUE_RESET_VALUE             ( 0x1 )
17717 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17718 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE                        ( 0x1 )
17719 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17720 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER0_MATCH_VALUE             ( 0x0 )
17721 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER1_MATCH_VALUE             ( 0x1 )
17722 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER2_MATCH_VALUE             ( 0x2 )
17723 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE             ( 0x3 )
17724 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_IP_FLTR_IP_FILTER3_MATCH_VALUE_RESET_VALUE ( 0x3 )
17725 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_ANYHIT_NO_HIT_VALUE                    ( 0x0 )
17726 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE                       ( 0x1 )
17727 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_ANYHIT_HIT_VALUE_RESET_VALUE           ( 0x1 )
17728 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER0_MATCH_VALUE           ( 0x0 )
17729 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER1_MATCH_VALUE           ( 0x1 )
17730 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER2_MATCH_VALUE           ( 0x2 )
17731 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER3_MATCH_VALUE           ( 0x3 )
17732 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER4_MATCH_VALUE           ( 0x4 )
17733 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER5_MATCH_VALUE           ( 0x5 )
17734 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER6_MATCH_VALUE           ( 0x6 )
17735 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER7_MATCH_VALUE           ( 0x7 )
17736 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER8_MATCH_VALUE           ( 0x8 )
17737 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER9_MATCH_VALUE           ( 0x9 )
17738 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER10_MATCH_VALUE          ( 0xA )
17739 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_VID_FILTER11_MATCH_VALUE          ( 0xB )
17740 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV1_VALUE                        ( 0xC )
17741 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV2_VALUE                        ( 0xD )
17742 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV3_VALUE                        ( 0xE )
17743 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE                        ( 0xF )
17744 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_VID_FLTR_RSV4_VALUE_RESET_VALUE            ( 0xF )
17745 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_BC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17746 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_BC_FLTR_HIT_VALUE                          ( 0x1 )
17747 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_BC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17748 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_MC_FLTR_NO_HIT_VALUE                       ( 0x0 )
17749 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_MC_FLTR_HIT_VALUE                          ( 0x1 )
17750 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_MC_FLTR_HIT_VALUE_RESET_VALUE              ( 0x1 )
17751 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_ANYHIT_NO_HIT_VALUE                     ( 0x0 )
17752 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE                        ( 0x1 )
17753 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_ANYHIT_HIT_VALUE_RESET_VALUE            ( 0x1 )
17754 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER0_MATCH_VALUE             ( 0x0 )
17755 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER1_MATCH_VALUE             ( 0x1 )
17756 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER2_MATCH_VALUE             ( 0x2 )
17757 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER3_MATCH_VALUE             ( 0x3 )
17758 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER4_MATCH_VALUE             ( 0x4 )
17759 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_DA_FILTER5_MATCH_VALUE             ( 0x5 )
17760 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_RSV1_VALUE                         ( 0x6 )
17761 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE                         ( 0x7 )
17762 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_DA_FLTR_RSV2_VALUE_RESET_VALUE             ( 0x7 )
17763 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_NONE_VALUE                              ( 0x0 )
17764 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_TCP_VALUE                               ( 0x1 )
17765 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_UDP_VALUE                               ( 0x2 )
17766 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_IGMP_VALUE                              ( 0x3 )
17767 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_ICMP_VALUE                              ( 0x4 )
17768 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_ICMPV6_VALUE                            ( 0x5 )
17769 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_ESP_VALUE                               ( 0x6 )
17770 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_GRE_VALUE                               ( 0x7 )
17771 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER0_VALUE                             ( 0x8 )
17772 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER1_VALUE                             ( 0x9 )
17773 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER2_VALUE                             ( 0xA )
17774 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_USER3_VALUE                             ( 0xB )
17775 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_RSV1_VALUE                              ( 0xC )
17776 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_IPV6_VALUE                              ( 0xD )
17777 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_AH_VALUE                                ( 0xE )
17778 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_NOT_PARSED_VALUE                        ( 0xF )
17779 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L4_NOT_PARSED_VALUE_RESET_VALUE            ( 0xF )
17780 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_NONE_VALUE                              ( 0x0 )
17781 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_IPV4_VALUE                              ( 0x1 )
17782 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_IPV6_VALUE                              ( 0x2 )
17783 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE                       ( 0x3 )
17784 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L3_RSV_DEFAULT_VALUE_RESET_VALUE           ( 0x3 )
17785 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_UNKNOWN_VALUE                           ( 0x0 )
17786 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_PPPOE_DISCOVERY_VALUE                   ( 0x1 )
17787 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_PPPOE_SESSION_VALUE                     ( 0x2 )
17788 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_IPV4OE_VALUE                            ( 0x4 )
17789 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_IPV6OE_VALUE                            ( 0x5 )
17790 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER0_VALUE                             ( 0x8 )
17791 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER1_VALUE                             ( 0x9 )
17792 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER2_VALUE                             ( 0xA )
17793 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_USER3_VALUE                             ( 0xB )
17794 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_ARP_VALUE                               ( 0xC )
17795 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE1588_VALUE                          ( 0xD )
17796 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE8021X_VALUE                         ( 0xE )
17797 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE                     ( 0xF )
17798 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_IH_CLASS_KEY_L2_TYPE8011AGCFM_VALUE_RESET_VALUE         ( 0xF )
17799
17800
17801 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_OFFSET ( 0x00000114 )
17802
17803 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_OFFSET )
17804 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_ADDRESS ), (r) )
17805 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15_ADDRESS ), (v) )
17806
17807 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
17808 typedef struct
17809 {
17810         /* IH_CLASS_KEY_ERR */
17811         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17812
17813         /* IH_CLASS_KEY_SP */
17814         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17815
17816         /* IH_CLASS_KEY_5TPL_FLTR */
17817         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17818
17819         /* IH_CLASS_KEY_WAN_FLTR */
17820         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17821
17822         /* IH_CLASS_KEY_IP_ANYHIT */
17823         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17824
17825         /* IH_CLASS_KEY_IP_FLTR */
17826         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17827
17828         /* IH_CLASS_KEY_VID_ANYHIT */
17829         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17830
17831         /* IH_CLASS_KEY_VID_FLTR */
17832         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17833
17834         /* IH_CLASS_KEY_BC_FLTR */
17835         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17836
17837         /* IH_CLASS_KEY_MC_FLTR */
17838         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17839
17840         /* IH_CLASS_KEY_DA_ANYHIT */
17841         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17842
17843         /* IH_CLASS_KEY_DA_FLTR */
17844         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17845
17846         /* IH_CLASS_KEY_L4 */
17847         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17848
17849         /* IH_CLASS_KEY_L3 */
17850         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17851
17852         /* IH_CLASS_KEY_L2 */
17853         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17854 }
17855 __PACKING_ATTRIBUTE_STRUCT_END__
17856 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15 ;
17857 #else
17858 typedef struct
17859 {
17860         /* IH_CLASS_KEY_L2 */
17861         uint32_t ih_class_key_l2                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17862
17863         /* IH_CLASS_KEY_L3 */
17864         uint32_t ih_class_key_l3                : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17865
17866         /* IH_CLASS_KEY_L4 */
17867         uint32_t ih_class_key_l4                : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17868
17869         /* IH_CLASS_KEY_DA_FLTR */
17870         uint32_t ih_class_key_da_fltr           : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17871
17872         /* IH_CLASS_KEY_DA_ANYHIT */
17873         uint32_t ih_class_key_da_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17874
17875         /* IH_CLASS_KEY_MC_FLTR */
17876         uint32_t ih_class_key_mc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17877
17878         /* IH_CLASS_KEY_BC_FLTR */
17879         uint32_t ih_class_key_bc_fltr           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17880
17881         /* IH_CLASS_KEY_VID_FLTR */
17882         uint32_t ih_class_key_vid_fltr          : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17883
17884         /* IH_CLASS_KEY_VID_ANYHIT */
17885         uint32_t ih_class_key_vid_anyhit        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17886
17887         /* IH_CLASS_KEY_IP_FLTR */
17888         uint32_t ih_class_key_ip_fltr           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17889
17890         /* IH_CLASS_KEY_IP_ANYHIT */
17891         uint32_t ih_class_key_ip_anyhit         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17892
17893         /* IH_CLASS_KEY_WAN_FLTR */
17894         uint32_t ih_class_key_wan_fltr          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17895
17896         /* IH_CLASS_KEY_5TPL_FLTR */
17897         uint32_t ih_class_key_5tpl_fltr         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17898
17899         /* IH_CLASS_KEY_SP */
17900         uint32_t ih_class_key_sp                : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17901
17902         /* IH_CLASS_KEY_ERR */
17903         uint32_t ih_class_key_err               : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17904 }
17905 __PACKING_ATTRIBUTE_STRUCT_END__
17906 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15 ;
17907 #endif
17908
17909 /*****************************************************************************************/
17910 /* IH_CLASS_MASK0                                                                        */
17911 /* IH Class - Mask0 configuration    Note: used for IH class identification by Parser Cl */
17912 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
17913 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
17914 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
17915 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
17916 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
17917 /*****************************************************************************************/
17918
17919 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
17920 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
17921
17922
17923 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_OFFSET ( 0x00000118 )
17924
17925 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_OFFSET )
17926 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_ADDRESS ), (r) )
17927 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0_ADDRESS ), (v) )
17928
17929 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
17930 typedef struct
17931 {
17932         /* IH_CLASS_KEY_MASK */
17933         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17934 }
17935 __PACKING_ATTRIBUTE_STRUCT_END__
17936 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0 ;
17937 #else
17938 typedef struct
17939 {
17940         /* IH_CLASS_KEY_MASK */
17941         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17942 }
17943 __PACKING_ATTRIBUTE_STRUCT_END__
17944 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0 ;
17945 #endif
17946
17947 /*****************************************************************************************/
17948 /* IH_CLASS_MASK1                                                                        */
17949 /* IH Class - Mask1 configuration    Note: used for IH class identification by Parser Cl */
17950 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
17951 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
17952 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
17953 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
17954 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
17955 /*****************************************************************************************/
17956
17957 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
17958 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
17959
17960
17961 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_OFFSET ( 0x0000011C )
17962
17963 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_OFFSET )
17964 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_ADDRESS ), (r) )
17965 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1_ADDRESS ), (v) )
17966
17967 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
17968 typedef struct
17969 {
17970         /* IH_CLASS_KEY_MASK */
17971         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17972 }
17973 __PACKING_ATTRIBUTE_STRUCT_END__
17974 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1 ;
17975 #else
17976 typedef struct
17977 {
17978         /* IH_CLASS_KEY_MASK */
17979         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
17980 }
17981 __PACKING_ATTRIBUTE_STRUCT_END__
17982 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1 ;
17983 #endif
17984
17985 /*****************************************************************************************/
17986 /* IH_CLASS_MASK2                                                                        */
17987 /* IH Class - Mask2 configuration    Note: used for IH class identification by Parser Cl */
17988 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
17989 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
17990 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
17991 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
17992 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
17993 /*****************************************************************************************/
17994
17995 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
17996 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
17997
17998
17999 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_OFFSET ( 0x00000120 )
18000
18001 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_OFFSET )
18002 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_ADDRESS ), (r) )
18003 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2_ADDRESS ), (v) )
18004
18005 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18006 typedef struct
18007 {
18008         /* IH_CLASS_KEY_MASK */
18009         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18010 }
18011 __PACKING_ATTRIBUTE_STRUCT_END__
18012 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2 ;
18013 #else
18014 typedef struct
18015 {
18016         /* IH_CLASS_KEY_MASK */
18017         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18018 }
18019 __PACKING_ATTRIBUTE_STRUCT_END__
18020 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2 ;
18021 #endif
18022
18023 /*****************************************************************************************/
18024 /* IH_CLASS_MASK3                                                                        */
18025 /* IH Class - Mask3 configuration    Note: used for IH class identification by Parser Cl */
18026 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
18027 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
18028 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
18029 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
18030 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
18031 /*****************************************************************************************/
18032
18033 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18034 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18035
18036
18037 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_OFFSET ( 0x00000124 )
18038
18039 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_OFFSET )
18040 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_ADDRESS ), (r) )
18041 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3_ADDRESS ), (v) )
18042
18043 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18044 typedef struct
18045 {
18046         /* IH_CLASS_KEY_MASK */
18047         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18048 }
18049 __PACKING_ATTRIBUTE_STRUCT_END__
18050 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3 ;
18051 #else
18052 typedef struct
18053 {
18054         /* IH_CLASS_KEY_MASK */
18055         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18056 }
18057 __PACKING_ATTRIBUTE_STRUCT_END__
18058 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3 ;
18059 #endif
18060
18061 /*****************************************************************************************/
18062 /* IH_CLASS_MASK4                                                                        */
18063 /* IH Class - Mask4 configuration    Note: used for IH class identification by Parser Cl */
18064 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
18065 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
18066 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
18067 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
18068 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
18069 /*****************************************************************************************/
18070
18071 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18072 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18073
18074
18075 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_OFFSET ( 0x00000128 )
18076
18077 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_OFFSET )
18078 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_ADDRESS ), (r) )
18079 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4_ADDRESS ), (v) )
18080
18081 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18082 typedef struct
18083 {
18084         /* IH_CLASS_KEY_MASK */
18085         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18086 }
18087 __PACKING_ATTRIBUTE_STRUCT_END__
18088 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4 ;
18089 #else
18090 typedef struct
18091 {
18092         /* IH_CLASS_KEY_MASK */
18093         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18094 }
18095 __PACKING_ATTRIBUTE_STRUCT_END__
18096 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4 ;
18097 #endif
18098
18099 /*****************************************************************************************/
18100 /* IH_CLASS_MASK5                                                                        */
18101 /* IH Class - Mask5 configuration    Note: used for IH class identification by Parser Cl */
18102 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
18103 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
18104 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
18105 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
18106 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
18107 /*****************************************************************************************/
18108
18109 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18110 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18111
18112
18113 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_OFFSET ( 0x0000012C )
18114
18115 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_OFFSET )
18116 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_ADDRESS ), (r) )
18117 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5_ADDRESS ), (v) )
18118
18119 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18120 typedef struct
18121 {
18122         /* IH_CLASS_KEY_MASK */
18123         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18124 }
18125 __PACKING_ATTRIBUTE_STRUCT_END__
18126 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5 ;
18127 #else
18128 typedef struct
18129 {
18130         /* IH_CLASS_KEY_MASK */
18131         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18132 }
18133 __PACKING_ATTRIBUTE_STRUCT_END__
18134 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5 ;
18135 #endif
18136
18137 /*****************************************************************************************/
18138 /* IH_CLASS_MASK6                                                                        */
18139 /* IH Class - Mask6 configuration    Note: used for IH class identification by Parser Cl */
18140 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
18141 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
18142 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
18143 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
18144 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
18145 /*****************************************************************************************/
18146
18147 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18148 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18149
18150
18151 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_OFFSET ( 0x00000130 )
18152
18153 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_OFFSET )
18154 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_ADDRESS ), (r) )
18155 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6_ADDRESS ), (v) )
18156
18157 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18158 typedef struct
18159 {
18160         /* IH_CLASS_KEY_MASK */
18161         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18162 }
18163 __PACKING_ATTRIBUTE_STRUCT_END__
18164 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6 ;
18165 #else
18166 typedef struct
18167 {
18168         /* IH_CLASS_KEY_MASK */
18169         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18170 }
18171 __PACKING_ATTRIBUTE_STRUCT_END__
18172 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6 ;
18173 #endif
18174
18175 /*****************************************************************************************/
18176 /* IH_CLASS_MASK7                                                                        */
18177 /* IH Class - Mask7 configuration    Note: used for IH class identification by Parser Cl */
18178 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
18179 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
18180 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
18181 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
18182 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
18183 /*****************************************************************************************/
18184
18185 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18186 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18187
18188
18189 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_OFFSET ( 0x00000134 )
18190
18191 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_OFFSET )
18192 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_ADDRESS ), (r) )
18193 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7_ADDRESS ), (v) )
18194
18195 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18196 typedef struct
18197 {
18198         /* IH_CLASS_KEY_MASK */
18199         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18200 }
18201 __PACKING_ATTRIBUTE_STRUCT_END__
18202 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7 ;
18203 #else
18204 typedef struct
18205 {
18206         /* IH_CLASS_KEY_MASK */
18207         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18208 }
18209 __PACKING_ATTRIBUTE_STRUCT_END__
18210 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7 ;
18211 #endif
18212
18213 /*****************************************************************************************/
18214 /* IH_CLASS_MASK8                                                                        */
18215 /* IH Class - Mask8 configuration    Note: used for IH class identification by Parser Cl */
18216 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
18217 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
18218 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
18219 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
18220 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
18221 /*****************************************************************************************/
18222
18223 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18224 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18225
18226
18227 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_OFFSET ( 0x00000138 )
18228
18229 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_OFFSET )
18230 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_ADDRESS ), (r) )
18231 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8_ADDRESS ), (v) )
18232
18233 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18234 typedef struct
18235 {
18236         /* IH_CLASS_KEY_MASK */
18237         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18238 }
18239 __PACKING_ATTRIBUTE_STRUCT_END__
18240 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8 ;
18241 #else
18242 typedef struct
18243 {
18244         /* IH_CLASS_KEY_MASK */
18245         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18246 }
18247 __PACKING_ATTRIBUTE_STRUCT_END__
18248 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8 ;
18249 #endif
18250
18251 /*****************************************************************************************/
18252 /* IH_CLASS_MASK9                                                                        */
18253 /* IH Class - Mask9 configuration    Note: used for IH class identification by Parser Cl */
18254 /* assifier, based on the Parser Summary Word comparison. Per each class there is a KEY  */
18255 /* configuration and MASK that applied on the Parser Sumary word. If the match based on  */
18256 /* KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header D */
18257 /* escriptor upon to override enable bit. The priority is always to lower Class ID (for  */
18258 /* example: if Class 3, 4 and 15 has match - Class 3 is choosen.                         */
18259 /*****************************************************************************************/
18260
18261 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18262 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18263
18264
18265 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_OFFSET ( 0x0000013C )
18266
18267 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_OFFSET )
18268 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_ADDRESS ), (r) )
18269 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9_ADDRESS ), (v) )
18270
18271 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18272 typedef struct
18273 {
18274         /* IH_CLASS_KEY_MASK */
18275         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18276 }
18277 __PACKING_ATTRIBUTE_STRUCT_END__
18278 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9 ;
18279 #else
18280 typedef struct
18281 {
18282         /* IH_CLASS_KEY_MASK */
18283         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18284 }
18285 __PACKING_ATTRIBUTE_STRUCT_END__
18286 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9 ;
18287 #endif
18288
18289 /*****************************************************************************************/
18290 /* IH_CLASS_MASK10                                                                       */
18291 /* IH Class - Mask10 configuration    Note: used for IH class identification by Parser C */
18292 /* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
18293 /*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
18294 /*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
18295 /* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
18296 /*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
18297 /*****************************************************************************************/
18298
18299 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18300 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18301
18302
18303 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_OFFSET ( 0x00000140 )
18304
18305 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_OFFSET )
18306 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_ADDRESS ), (r) )
18307 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10_ADDRESS ), (v) )
18308
18309 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18310 typedef struct
18311 {
18312         /* IH_CLASS_KEY_MASK */
18313         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18314 }
18315 __PACKING_ATTRIBUTE_STRUCT_END__
18316 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10 ;
18317 #else
18318 typedef struct
18319 {
18320         /* IH_CLASS_KEY_MASK */
18321         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18322 }
18323 __PACKING_ATTRIBUTE_STRUCT_END__
18324 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10 ;
18325 #endif
18326
18327 /*****************************************************************************************/
18328 /* IH_CLASS_MASK11                                                                       */
18329 /* IH Class - Mask11 configuration    Note: used for IH class identification by Parser C */
18330 /* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
18331 /*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
18332 /*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
18333 /* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
18334 /*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
18335 /*****************************************************************************************/
18336
18337 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18338 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18339
18340
18341 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_OFFSET ( 0x00000144 )
18342
18343 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_OFFSET )
18344 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_ADDRESS ), (r) )
18345 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11_ADDRESS ), (v) )
18346
18347 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18348 typedef struct
18349 {
18350         /* IH_CLASS_KEY_MASK */
18351         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18352 }
18353 __PACKING_ATTRIBUTE_STRUCT_END__
18354 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11 ;
18355 #else
18356 typedef struct
18357 {
18358         /* IH_CLASS_KEY_MASK */
18359         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18360 }
18361 __PACKING_ATTRIBUTE_STRUCT_END__
18362 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11 ;
18363 #endif
18364
18365 /*****************************************************************************************/
18366 /* IH_CLASS_MASK12                                                                       */
18367 /* IH Class - Mask12 configuration    Note: used for IH class identification by Parser C */
18368 /* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
18369 /*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
18370 /*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
18371 /* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
18372 /*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
18373 /*****************************************************************************************/
18374
18375 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18376 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18377
18378
18379 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_OFFSET ( 0x00000148 )
18380
18381 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_OFFSET )
18382 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_ADDRESS ), (r) )
18383 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12_ADDRESS ), (v) )
18384
18385 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18386 typedef struct
18387 {
18388         /* IH_CLASS_KEY_MASK */
18389         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18390 }
18391 __PACKING_ATTRIBUTE_STRUCT_END__
18392 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12 ;
18393 #else
18394 typedef struct
18395 {
18396         /* IH_CLASS_KEY_MASK */
18397         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18398 }
18399 __PACKING_ATTRIBUTE_STRUCT_END__
18400 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12 ;
18401 #endif
18402
18403 /*****************************************************************************************/
18404 /* IH_CLASS_MASK13                                                                       */
18405 /* IH Class - Mask13 configuration    Note: used for IH class identification by Parser C */
18406 /* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
18407 /*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
18408 /*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
18409 /* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
18410 /*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
18411 /*****************************************************************************************/
18412
18413 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18414 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18415
18416
18417 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_OFFSET ( 0x0000014C )
18418
18419 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_OFFSET )
18420 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_ADDRESS ), (r) )
18421 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13_ADDRESS ), (v) )
18422
18423 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18424 typedef struct
18425 {
18426         /* IH_CLASS_KEY_MASK */
18427         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18428 }
18429 __PACKING_ATTRIBUTE_STRUCT_END__
18430 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13 ;
18431 #else
18432 typedef struct
18433 {
18434         /* IH_CLASS_KEY_MASK */
18435         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18436 }
18437 __PACKING_ATTRIBUTE_STRUCT_END__
18438 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13 ;
18439 #endif
18440
18441 /*****************************************************************************************/
18442 /* IH_CLASS_MASK14                                                                       */
18443 /* IH Class - Mask13 configuration    Note: used for IH class identification by Parser C */
18444 /* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
18445 /*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
18446 /*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
18447 /* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
18448 /*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
18449 /*****************************************************************************************/
18450
18451 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18452 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18453
18454
18455 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_OFFSET ( 0x00000150 )
18456
18457 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_OFFSET )
18458 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_ADDRESS ), (r) )
18459 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14_ADDRESS ), (v) )
18460
18461 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18462 typedef struct
18463 {
18464         /* IH_CLASS_KEY_MASK */
18465         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18466 }
18467 __PACKING_ATTRIBUTE_STRUCT_END__
18468 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14 ;
18469 #else
18470 typedef struct
18471 {
18472         /* IH_CLASS_KEY_MASK */
18473         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18474 }
18475 __PACKING_ATTRIBUTE_STRUCT_END__
18476 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14 ;
18477 #endif
18478
18479 /*****************************************************************************************/
18480 /* IH_CLASS_MASK15                                                                       */
18481 /* IH Class - Mask15 configuration    Note: used for IH class identification by Parser C */
18482 /* lassifier, based on the Parser Summary Word comparison. Per each class there is a KEY */
18483 /*  configuration and MASK that applied on the Parser Sumary word. If the match based on */
18484 /*  KEY & MASK is OK, Classifier may override IH class provided by BBH/Runner in Header  */
18485 /* Descriptor upon to override enable bit. The priority is always to lower Class ID (for */
18486 /*  example: if Class 3, 4 and 15 has match - Class 3 is choosen.                        */
18487 /*****************************************************************************************/
18488
18489 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_IH_CLASS_MASK_MASK_VALUE_VALUE             ( 0x0 )
18490 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_IH_CLASS_MASK_MASK_VALUE_VALUE_RESET_VALUE ( 0x0 )
18491
18492
18493 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_OFFSET ( 0x00000154 )
18494
18495 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_OFFSET )
18496 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_ADDRESS ), (r) )
18497 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15_ADDRESS ), (v) )
18498
18499 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18500 typedef struct
18501 {
18502         /* IH_CLASS_KEY_MASK */
18503         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18504 }
18505 __PACKING_ATTRIBUTE_STRUCT_END__
18506 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15 ;
18507 #else
18508 typedef struct
18509 {
18510         /* IH_CLASS_KEY_MASK */
18511         uint32_t ih_class_mask  : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18512 }
18513 __PACKING_ATTRIBUTE_STRUCT_END__
18514 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15 ;
18515 #endif
18516
18517 /*****************************************************************************************/
18518 /* IH_CLASS0_GENERAL_CFG                                                                 */
18519 /* Set of defaults (general parameters) for IH class0    These parameters used for defau */
18520 /* lt setting per current IH class, used also as characterization of this ingres traffic */
18521 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
18522 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
18523 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
18524 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
18525 /* translation: reference to translation table  o                                              */
18526 /*****************************************************************************************/
18527
18528 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
18529 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
18530 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
18531 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
18532 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
18533 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
18534 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
18535 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
18536 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
18537 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
18538 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
18539 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
18540 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
18541 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
18542 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
18543 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
18544 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
18545 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
18546 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
18547 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
18548 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
18549 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
18550 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
18551 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
18552 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
18553 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
18554 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
18555 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
18556 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
18557 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
18558 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
18559 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
18560 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
18561 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
18562 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
18563 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
18564 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
18565 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
18566 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
18567 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
18568 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
18569 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
18570 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
18571
18572
18573 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_OFFSET ( 0x00000158 )
18574
18575 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_OFFSET )
18576 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_ADDRESS ), (r) )
18577 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG_ADDRESS ), (v) )
18578
18579 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18580 typedef struct
18581 {
18582         /* rsv */
18583         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18584
18585         /* SPARE */
18586         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18587
18588         /* RNR_DEFAULT_DM */
18589         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18590
18591         /* RNR_OVR_DM */
18592         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18593
18594         /* DSCP2TCI_TRANS_TBL */
18595         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18596
18597         /* PREF_LB_EN */
18598         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18599
18600         /* LB_EN */
18601         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18602
18603         /* TR_DEFAULT */
18604         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18605
18606         /* DM_OVERRIDE */
18607         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18608
18609         /* DM_DEFAULT */
18610         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18611
18612         /* TM_OVERRIDE */
18613         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18614
18615         /* TM_DEFAULT */
18616         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18617
18618         /* QOS_OVERRIDE */
18619         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18620
18621         /* QOS_DEFAULT */
18622         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18623 }
18624 __PACKING_ATTRIBUTE_STRUCT_END__
18625 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG ;
18626 #else
18627 typedef struct
18628 {
18629         /* QOS_DEFAULT */
18630         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18631
18632         /* QOS_OVERRIDE */
18633         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18634
18635         /* TM_DEFAULT */
18636         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18637
18638         /* TM_OVERRIDE */
18639         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18640
18641         /* DM_DEFAULT */
18642         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18643
18644         /* DM_OVERRIDE */
18645         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18646
18647         /* TR_DEFAULT */
18648         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18649
18650         /* LB_EN */
18651         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18652
18653         /* PREF_LB_EN */
18654         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18655
18656         /* DSCP2TCI_TRANS_TBL */
18657         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18658
18659         /* RNR_OVR_DM */
18660         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18661
18662         /* RNR_DEFAULT_DM */
18663         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18664
18665         /* SPARE */
18666         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18667
18668         /* rsv */
18669         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18670 }
18671 __PACKING_ATTRIBUTE_STRUCT_END__
18672 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG ;
18673 #endif
18674
18675 /*****************************************************************************************/
18676 /* IH_CLASS1_GENERAL_CFG                                                                 */
18677 /* Set of defaults (general parameters) for IH class1    These parameters used for defau */
18678 /* lt setting per current IH class, used also as characterization of this ingres traffic */
18679 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
18680 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
18681 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
18682 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
18683 /* translation: reference to translation table  o                                              */
18684 /*****************************************************************************************/
18685
18686 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
18687 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
18688 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
18689 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
18690 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
18691 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
18692 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
18693 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
18694 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
18695 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
18696 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
18697 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
18698 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
18699 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
18700 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
18701 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
18702 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
18703 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
18704 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
18705 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
18706 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
18707 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
18708 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
18709 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
18710 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
18711 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
18712 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
18713 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
18714 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
18715 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
18716 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
18717 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
18718 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
18719 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
18720 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
18721 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
18722 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
18723 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
18724 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
18725 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
18726 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
18727 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
18728 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
18729
18730
18731 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_OFFSET ( 0x0000015C )
18732
18733 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_OFFSET )
18734 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_ADDRESS ), (r) )
18735 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG_ADDRESS ), (v) )
18736
18737 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18738 typedef struct
18739 {
18740         /* rsv */
18741         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18742
18743         /* SPARE */
18744         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18745
18746         /* RNR_DEFAULT_DM */
18747         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18748
18749         /* RNR_OVR_DM */
18750         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18751
18752         /* DSCP2TCI_TRANS_TBL */
18753         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18754
18755         /* PREF_LB_EN */
18756         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18757
18758         /* LB_EN */
18759         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18760
18761         /* TR_DEFAULT */
18762         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18763
18764         /* DM_OVERRIDE */
18765         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18766
18767         /* DM_DEFAULT */
18768         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18769
18770         /* TM_OVERRIDE */
18771         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18772
18773         /* TM_DEFAULT */
18774         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18775
18776         /* QOS_OVERRIDE */
18777         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18778
18779         /* QOS_DEFAULT */
18780         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18781 }
18782 __PACKING_ATTRIBUTE_STRUCT_END__
18783 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG ;
18784 #else
18785 typedef struct
18786 {
18787         /* QOS_DEFAULT */
18788         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18789
18790         /* QOS_OVERRIDE */
18791         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18792
18793         /* TM_DEFAULT */
18794         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18795
18796         /* TM_OVERRIDE */
18797         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18798
18799         /* DM_DEFAULT */
18800         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18801
18802         /* DM_OVERRIDE */
18803         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18804
18805         /* TR_DEFAULT */
18806         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18807
18808         /* LB_EN */
18809         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18810
18811         /* PREF_LB_EN */
18812         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18813
18814         /* DSCP2TCI_TRANS_TBL */
18815         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18816
18817         /* RNR_OVR_DM */
18818         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18819
18820         /* RNR_DEFAULT_DM */
18821         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18822
18823         /* SPARE */
18824         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18825
18826         /* rsv */
18827         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18828 }
18829 __PACKING_ATTRIBUTE_STRUCT_END__
18830 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG ;
18831 #endif
18832
18833 /*****************************************************************************************/
18834 /* IH_CLASS2_GENERAL_CFG                                                                 */
18835 /* Set of defaults (general parameters) for IH class2    These parameters used for defau */
18836 /* lt setting per current IH class, used also as characterization of this ingres traffic */
18837 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
18838 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
18839 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
18840 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
18841 /* translation: reference to translation table  o                                              */
18842 /*****************************************************************************************/
18843
18844 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
18845 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
18846 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
18847 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
18848 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
18849 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
18850 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
18851 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
18852 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
18853 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
18854 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
18855 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
18856 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
18857 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
18858 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
18859 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
18860 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
18861 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
18862 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
18863 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
18864 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
18865 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
18866 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
18867 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
18868 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
18869 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
18870 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
18871 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
18872 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
18873 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
18874 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
18875 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
18876 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
18877 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
18878 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
18879 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
18880 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
18881 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
18882 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
18883 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
18884 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
18885 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
18886 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
18887
18888
18889 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_OFFSET ( 0x00000160 )
18890
18891 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_OFFSET )
18892 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_ADDRESS ), (r) )
18893 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG_ADDRESS ), (v) )
18894
18895 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
18896 typedef struct
18897 {
18898         /* rsv */
18899         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18900
18901         /* SPARE */
18902         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18903
18904         /* RNR_DEFAULT_DM */
18905         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18906
18907         /* RNR_OVR_DM */
18908         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18909
18910         /* DSCP2TCI_TRANS_TBL */
18911         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18912
18913         /* PREF_LB_EN */
18914         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18915
18916         /* LB_EN */
18917         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18918
18919         /* TR_DEFAULT */
18920         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18921
18922         /* DM_OVERRIDE */
18923         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18924
18925         /* DM_DEFAULT */
18926         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18927
18928         /* TM_OVERRIDE */
18929         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18930
18931         /* TM_DEFAULT */
18932         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18933
18934         /* QOS_OVERRIDE */
18935         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18936
18937         /* QOS_DEFAULT */
18938         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18939 }
18940 __PACKING_ATTRIBUTE_STRUCT_END__
18941 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG ;
18942 #else
18943 typedef struct
18944 {
18945         /* QOS_DEFAULT */
18946         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18947
18948         /* QOS_OVERRIDE */
18949         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18950
18951         /* TM_DEFAULT */
18952         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18953
18954         /* TM_OVERRIDE */
18955         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18956
18957         /* DM_DEFAULT */
18958         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18959
18960         /* DM_OVERRIDE */
18961         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18962
18963         /* TR_DEFAULT */
18964         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18965
18966         /* LB_EN */
18967         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18968
18969         /* PREF_LB_EN */
18970         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18971
18972         /* DSCP2TCI_TRANS_TBL */
18973         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18974
18975         /* RNR_OVR_DM */
18976         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18977
18978         /* RNR_DEFAULT_DM */
18979         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18980
18981         /* SPARE */
18982         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18983
18984         /* rsv */
18985         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
18986 }
18987 __PACKING_ATTRIBUTE_STRUCT_END__
18988 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG ;
18989 #endif
18990
18991 /*****************************************************************************************/
18992 /* IH_CLASS3_GENERAL_CFG                                                                 */
18993 /* Set of defaults (general parameters) for IH class3    These parameters used for defau */
18994 /* lt setting per current IH class, used also as characterization of this ingres traffic */
18995 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
18996 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
18997 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
18998 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
18999 /* translation: reference to translation table  o                                              */
19000 /*****************************************************************************************/
19001
19002 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
19003 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
19004 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
19005 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
19006 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
19007 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
19008 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
19009 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
19010 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
19011 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
19012 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
19013 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
19014 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
19015 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
19016 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
19017 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
19018 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
19019 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
19020 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
19021 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
19022 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
19023 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
19024 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
19025 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19026 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19027 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19028 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
19029 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
19030 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
19031 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19032 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19033 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19034 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
19035 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
19036 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
19037 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
19038 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
19039 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
19040 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
19041 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
19042 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
19043 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
19044 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
19045
19046
19047 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_OFFSET ( 0x00000164 )
19048
19049 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_OFFSET )
19050 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_ADDRESS ), (r) )
19051 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG_ADDRESS ), (v) )
19052
19053 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
19054 typedef struct
19055 {
19056         /* rsv */
19057         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19058
19059         /* SPARE */
19060         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19061
19062         /* RNR_DEFAULT_DM */
19063         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19064
19065         /* RNR_OVR_DM */
19066         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19067
19068         /* DSCP2TCI_TRANS_TBL */
19069         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19070
19071         /* PREF_LB_EN */
19072         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19073
19074         /* LB_EN */
19075         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19076
19077         /* TR_DEFAULT */
19078         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19079
19080         /* DM_OVERRIDE */
19081         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19082
19083         /* DM_DEFAULT */
19084         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19085
19086         /* TM_OVERRIDE */
19087         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19088
19089         /* TM_DEFAULT */
19090         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19091
19092         /* QOS_OVERRIDE */
19093         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19094
19095         /* QOS_DEFAULT */
19096         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19097 }
19098 __PACKING_ATTRIBUTE_STRUCT_END__
19099 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG ;
19100 #else
19101 typedef struct
19102 {
19103         /* QOS_DEFAULT */
19104         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19105
19106         /* QOS_OVERRIDE */
19107         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19108
19109         /* TM_DEFAULT */
19110         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19111
19112         /* TM_OVERRIDE */
19113         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19114
19115         /* DM_DEFAULT */
19116         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19117
19118         /* DM_OVERRIDE */
19119         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19120
19121         /* TR_DEFAULT */
19122         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19123
19124         /* LB_EN */
19125         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19126
19127         /* PREF_LB_EN */
19128         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19129
19130         /* DSCP2TCI_TRANS_TBL */
19131         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19132
19133         /* RNR_OVR_DM */
19134         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19135
19136         /* RNR_DEFAULT_DM */
19137         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19138
19139         /* SPARE */
19140         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19141
19142         /* rsv */
19143         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19144 }
19145 __PACKING_ATTRIBUTE_STRUCT_END__
19146 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG ;
19147 #endif
19148
19149 /*****************************************************************************************/
19150 /* IH_CLASS4_GENERAL_CFG                                                                 */
19151 /* Set of defaults (general parameters) for IH class4    These parameters used for defau */
19152 /* lt setting per current IH class, used also as characterization of this ingres traffic */
19153 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
19154 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
19155 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
19156 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
19157 /* translation: reference to translation table  o                                              */
19158 /*****************************************************************************************/
19159
19160 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
19161 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
19162 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
19163 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
19164 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
19165 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
19166 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
19167 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
19168 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
19169 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
19170 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
19171 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
19172 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
19173 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
19174 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
19175 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
19176 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
19177 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
19178 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
19179 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
19180 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
19181 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
19182 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
19183 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19184 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19185 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19186 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
19187 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
19188 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
19189 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19190 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19191 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19192 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
19193 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
19194 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
19195 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
19196 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
19197 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
19198 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
19199 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
19200 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
19201 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
19202 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
19203
19204
19205 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_OFFSET ( 0x00000168 )
19206
19207 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_OFFSET )
19208 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_ADDRESS ), (r) )
19209 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG_ADDRESS ), (v) )
19210
19211 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
19212 typedef struct
19213 {
19214         /* rsv */
19215         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19216
19217         /* SPARE */
19218         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19219
19220         /* RNR_DEFAULT_DM */
19221         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19222
19223         /* RNR_OVR_DM */
19224         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19225
19226         /* DSCP2TCI_TRANS_TBL */
19227         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19228
19229         /* PREF_LB_EN */
19230         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19231
19232         /* LB_EN */
19233         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19234
19235         /* TR_DEFAULT */
19236         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19237
19238         /* DM_OVERRIDE */
19239         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19240
19241         /* DM_DEFAULT */
19242         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19243
19244         /* TM_OVERRIDE */
19245         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19246
19247         /* TM_DEFAULT */
19248         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19249
19250         /* QOS_OVERRIDE */
19251         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19252
19253         /* QOS_DEFAULT */
19254         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19255 }
19256 __PACKING_ATTRIBUTE_STRUCT_END__
19257 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG ;
19258 #else
19259 typedef struct
19260 {
19261         /* QOS_DEFAULT */
19262         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19263
19264         /* QOS_OVERRIDE */
19265         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19266
19267         /* TM_DEFAULT */
19268         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19269
19270         /* TM_OVERRIDE */
19271         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19272
19273         /* DM_DEFAULT */
19274         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19275
19276         /* DM_OVERRIDE */
19277         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19278
19279         /* TR_DEFAULT */
19280         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19281
19282         /* LB_EN */
19283         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19284
19285         /* PREF_LB_EN */
19286         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19287
19288         /* DSCP2TCI_TRANS_TBL */
19289         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19290
19291         /* RNR_OVR_DM */
19292         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19293
19294         /* RNR_DEFAULT_DM */
19295         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19296
19297         /* SPARE */
19298         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19299
19300         /* rsv */
19301         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19302 }
19303 __PACKING_ATTRIBUTE_STRUCT_END__
19304 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG ;
19305 #endif
19306
19307 /*****************************************************************************************/
19308 /* IH_CLASS5_GENERAL_CFG                                                                 */
19309 /* Set of defaults (general parameters) for IH class5    These parameters used for defau */
19310 /* lt setting per current IH class, used also as characterization of this ingres traffic */
19311 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
19312 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
19313 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
19314 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
19315 /* translation: reference to translation table  o                                              */
19316 /*****************************************************************************************/
19317
19318 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
19319 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
19320 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
19321 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
19322 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
19323 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
19324 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
19325 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
19326 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
19327 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
19328 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
19329 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
19330 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
19331 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
19332 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
19333 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
19334 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
19335 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
19336 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
19337 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
19338 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
19339 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
19340 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
19341 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19342 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19343 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19344 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
19345 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
19346 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
19347 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19348 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19349 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19350 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
19351 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
19352 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
19353 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
19354 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
19355 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
19356 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
19357 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
19358 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
19359 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
19360 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
19361
19362
19363 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_OFFSET ( 0x0000016C )
19364
19365 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_OFFSET )
19366 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_ADDRESS ), (r) )
19367 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG_ADDRESS ), (v) )
19368
19369 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
19370 typedef struct
19371 {
19372         /* rsv */
19373         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19374
19375         /* SPARE */
19376         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19377
19378         /* RNR_DEFAULT_DM */
19379         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19380
19381         /* RNR_OVR_DM */
19382         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19383
19384         /* DSCP2TCI_TRANS_TBL */
19385         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19386
19387         /* PREF_LB_EN */
19388         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19389
19390         /* LB_EN */
19391         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19392
19393         /* TR_DEFAULT */
19394         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19395
19396         /* DM_OVERRIDE */
19397         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19398
19399         /* DM_DEFAULT */
19400         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19401
19402         /* TM_OVERRIDE */
19403         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19404
19405         /* TM_DEFAULT */
19406         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19407
19408         /* QOS_OVERRIDE */
19409         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19410
19411         /* QOS_DEFAULT */
19412         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19413 }
19414 __PACKING_ATTRIBUTE_STRUCT_END__
19415 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG ;
19416 #else
19417 typedef struct
19418 {
19419         /* QOS_DEFAULT */
19420         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19421
19422         /* QOS_OVERRIDE */
19423         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19424
19425         /* TM_DEFAULT */
19426         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19427
19428         /* TM_OVERRIDE */
19429         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19430
19431         /* DM_DEFAULT */
19432         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19433
19434         /* DM_OVERRIDE */
19435         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19436
19437         /* TR_DEFAULT */
19438         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19439
19440         /* LB_EN */
19441         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19442
19443         /* PREF_LB_EN */
19444         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19445
19446         /* DSCP2TCI_TRANS_TBL */
19447         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19448
19449         /* RNR_OVR_DM */
19450         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19451
19452         /* RNR_DEFAULT_DM */
19453         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19454
19455         /* SPARE */
19456         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19457
19458         /* rsv */
19459         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19460 }
19461 __PACKING_ATTRIBUTE_STRUCT_END__
19462 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG ;
19463 #endif
19464
19465 /*****************************************************************************************/
19466 /* IH_CLASS6_GENERAL_CFG                                                                 */
19467 /* Set of defaults (general parameters) for IH class6    These parameters used for defau */
19468 /* lt setting per current IH class, used also as characterization of this ingres traffic */
19469 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
19470 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
19471 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
19472 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
19473 /* translation: reference to translation table  o                                              */
19474 /*****************************************************************************************/
19475
19476 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
19477 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
19478 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
19479 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
19480 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
19481 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
19482 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
19483 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
19484 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
19485 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
19486 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
19487 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
19488 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
19489 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
19490 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
19491 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
19492 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
19493 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
19494 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
19495 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
19496 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
19497 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
19498 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
19499 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19500 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19501 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19502 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
19503 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
19504 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
19505 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19506 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19507 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19508 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
19509 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
19510 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
19511 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
19512 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
19513 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
19514 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
19515 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
19516 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
19517 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
19518 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
19519
19520
19521 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_OFFSET ( 0x00000170 )
19522
19523 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_OFFSET )
19524 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_ADDRESS ), (r) )
19525 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG_ADDRESS ), (v) )
19526
19527 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
19528 typedef struct
19529 {
19530         /* rsv */
19531         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19532
19533         /* SPARE */
19534         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19535
19536         /* RNR_DEFAULT_DM */
19537         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19538
19539         /* RNR_OVR_DM */
19540         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19541
19542         /* DSCP2TCI_TRANS_TBL */
19543         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19544
19545         /* PREF_LB_EN */
19546         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19547
19548         /* LB_EN */
19549         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19550
19551         /* TR_DEFAULT */
19552         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19553
19554         /* DM_OVERRIDE */
19555         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19556
19557         /* DM_DEFAULT */
19558         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19559
19560         /* TM_OVERRIDE */
19561         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19562
19563         /* TM_DEFAULT */
19564         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19565
19566         /* QOS_OVERRIDE */
19567         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19568
19569         /* QOS_DEFAULT */
19570         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19571 }
19572 __PACKING_ATTRIBUTE_STRUCT_END__
19573 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG ;
19574 #else
19575 typedef struct
19576 {
19577         /* QOS_DEFAULT */
19578         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19579
19580         /* QOS_OVERRIDE */
19581         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19582
19583         /* TM_DEFAULT */
19584         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19585
19586         /* TM_OVERRIDE */
19587         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19588
19589         /* DM_DEFAULT */
19590         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19591
19592         /* DM_OVERRIDE */
19593         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19594
19595         /* TR_DEFAULT */
19596         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19597
19598         /* LB_EN */
19599         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19600
19601         /* PREF_LB_EN */
19602         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19603
19604         /* DSCP2TCI_TRANS_TBL */
19605         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19606
19607         /* RNR_OVR_DM */
19608         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19609
19610         /* RNR_DEFAULT_DM */
19611         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19612
19613         /* SPARE */
19614         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19615
19616         /* rsv */
19617         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19618 }
19619 __PACKING_ATTRIBUTE_STRUCT_END__
19620 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG ;
19621 #endif
19622
19623 /*****************************************************************************************/
19624 /* IH_CLASS7_GENERAL_CFG                                                                 */
19625 /* Set of defaults (general parameters) for IH class7    These parameters used for defau */
19626 /* lt setting per current IH class, used also as characterization of this ingres traffic */
19627 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
19628 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
19629 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
19630 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
19631 /* translation: reference to translation table  o                                              */
19632 /*****************************************************************************************/
19633
19634 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
19635 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
19636 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
19637 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
19638 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
19639 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
19640 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
19641 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
19642 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
19643 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
19644 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
19645 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
19646 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
19647 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
19648 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
19649 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
19650 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
19651 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
19652 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
19653 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
19654 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
19655 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
19656 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
19657 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19658 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19659 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19660 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
19661 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
19662 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
19663 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19664 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19665 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19666 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
19667 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
19668 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
19669 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
19670 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
19671 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
19672 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
19673 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
19674 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
19675 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
19676 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
19677
19678
19679 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_OFFSET ( 0x00000174 )
19680
19681 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_OFFSET )
19682 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_ADDRESS ), (r) )
19683 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG_ADDRESS ), (v) )
19684
19685 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
19686 typedef struct
19687 {
19688         /* rsv */
19689         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19690
19691         /* SPARE */
19692         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19693
19694         /* RNR_DEFAULT_DM */
19695         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19696
19697         /* RNR_OVR_DM */
19698         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19699
19700         /* DSCP2TCI_TRANS_TBL */
19701         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19702
19703         /* PREF_LB_EN */
19704         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19705
19706         /* LB_EN */
19707         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19708
19709         /* TR_DEFAULT */
19710         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19711
19712         /* DM_OVERRIDE */
19713         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19714
19715         /* DM_DEFAULT */
19716         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19717
19718         /* TM_OVERRIDE */
19719         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19720
19721         /* TM_DEFAULT */
19722         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19723
19724         /* QOS_OVERRIDE */
19725         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19726
19727         /* QOS_DEFAULT */
19728         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19729 }
19730 __PACKING_ATTRIBUTE_STRUCT_END__
19731 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG ;
19732 #else
19733 typedef struct
19734 {
19735         /* QOS_DEFAULT */
19736         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19737
19738         /* QOS_OVERRIDE */
19739         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19740
19741         /* TM_DEFAULT */
19742         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19743
19744         /* TM_OVERRIDE */
19745         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19746
19747         /* DM_DEFAULT */
19748         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19749
19750         /* DM_OVERRIDE */
19751         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19752
19753         /* TR_DEFAULT */
19754         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19755
19756         /* LB_EN */
19757         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19758
19759         /* PREF_LB_EN */
19760         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19761
19762         /* DSCP2TCI_TRANS_TBL */
19763         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19764
19765         /* RNR_OVR_DM */
19766         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19767
19768         /* RNR_DEFAULT_DM */
19769         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19770
19771         /* SPARE */
19772         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19773
19774         /* rsv */
19775         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19776 }
19777 __PACKING_ATTRIBUTE_STRUCT_END__
19778 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG ;
19779 #endif
19780
19781 /*****************************************************************************************/
19782 /* IH_CLASS8_GENERAL_CFG                                                                 */
19783 /* Set of defaults (general parameters) for IH class8    These parameters used for defau */
19784 /* lt setting per current IH class, used also as characterization of this ingres traffic */
19785 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
19786 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
19787 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
19788 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
19789 /* translation: reference to translation table  o                                              */
19790 /*****************************************************************************************/
19791
19792 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
19793 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
19794 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
19795 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
19796 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
19797 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
19798 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
19799 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
19800 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
19801 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
19802 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
19803 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
19804 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
19805 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
19806 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
19807 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
19808 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
19809 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
19810 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
19811 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
19812 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
19813 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
19814 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
19815 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19816 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19817 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19818 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
19819 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
19820 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
19821 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19822 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19823 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19824 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
19825 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
19826 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
19827 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
19828 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
19829 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
19830 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
19831 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
19832 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
19833 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
19834 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
19835
19836
19837 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_OFFSET ( 0x00000178 )
19838
19839 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_OFFSET )
19840 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_ADDRESS ), (r) )
19841 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG_ADDRESS ), (v) )
19842
19843 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
19844 typedef struct
19845 {
19846         /* rsv */
19847         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19848
19849         /* SPARE */
19850         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19851
19852         /* RNR_DEFAULT_DM */
19853         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19854
19855         /* RNR_OVR_DM */
19856         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19857
19858         /* DSCP2TCI_TRANS_TBL */
19859         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19860
19861         /* PREF_LB_EN */
19862         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19863
19864         /* LB_EN */
19865         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19866
19867         /* TR_DEFAULT */
19868         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19869
19870         /* DM_OVERRIDE */
19871         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19872
19873         /* DM_DEFAULT */
19874         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19875
19876         /* TM_OVERRIDE */
19877         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19878
19879         /* TM_DEFAULT */
19880         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19881
19882         /* QOS_OVERRIDE */
19883         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19884
19885         /* QOS_DEFAULT */
19886         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19887 }
19888 __PACKING_ATTRIBUTE_STRUCT_END__
19889 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG ;
19890 #else
19891 typedef struct
19892 {
19893         /* QOS_DEFAULT */
19894         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19895
19896         /* QOS_OVERRIDE */
19897         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19898
19899         /* TM_DEFAULT */
19900         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19901
19902         /* TM_OVERRIDE */
19903         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19904
19905         /* DM_DEFAULT */
19906         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19907
19908         /* DM_OVERRIDE */
19909         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19910
19911         /* TR_DEFAULT */
19912         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19913
19914         /* LB_EN */
19915         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19916
19917         /* PREF_LB_EN */
19918         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19919
19920         /* DSCP2TCI_TRANS_TBL */
19921         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19922
19923         /* RNR_OVR_DM */
19924         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19925
19926         /* RNR_DEFAULT_DM */
19927         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19928
19929         /* SPARE */
19930         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19931
19932         /* rsv */
19933         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
19934 }
19935 __PACKING_ATTRIBUTE_STRUCT_END__
19936 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG ;
19937 #endif
19938
19939 /*****************************************************************************************/
19940 /* IH_CLASS9_GENERAL_CFG                                                                 */
19941 /* Set of defaults (general parameters) for IH class9    These parameters used for defau */
19942 /* lt setting per current IH class, used also as characterization of this ingres traffic */
19943 /* .    The set of aparametrs include:    o     Ingres QoS setting for class & override enab */
19944 /* le by LUT  o Destination memory setting per class & override enable by LUT  o        Direct  */
19945 /* mode setting per class & override enable by LUT   o  Default target Runner setting per */
19946 /*  class & load balancing enable + preference enable for load balancing  o     DSCP to TCI  */
19947 /* translation: reference to translation table  o                                              */
19948 /*****************************************************************************************/
19949
19950 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
19951 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
19952 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
19953 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
19954 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
19955 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
19956 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
19957 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
19958 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
19959 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
19960 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
19961 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
19962 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
19963 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
19964 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
19965 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
19966 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
19967 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
19968 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
19969 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
19970 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
19971 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
19972 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
19973 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19974 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19975 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19976 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
19977 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
19978 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
19979 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
19980 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
19981 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
19982 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
19983 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
19984 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
19985 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
19986 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
19987 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
19988 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
19989 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
19990 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
19991 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
19992 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
19993
19994
19995 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_OFFSET ( 0x0000017C )
19996
19997 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_OFFSET )
19998 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_ADDRESS ), (r) )
19999 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG_ADDRESS ), (v) )
20000
20001 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
20002 typedef struct
20003 {
20004         /* rsv */
20005         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20006
20007         /* SPARE */
20008         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20009
20010         /* RNR_DEFAULT_DM */
20011         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20012
20013         /* RNR_OVR_DM */
20014         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20015
20016         /* DSCP2TCI_TRANS_TBL */
20017         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20018
20019         /* PREF_LB_EN */
20020         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20021
20022         /* LB_EN */
20023         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20024
20025         /* TR_DEFAULT */
20026         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20027
20028         /* DM_OVERRIDE */
20029         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20030
20031         /* DM_DEFAULT */
20032         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20033
20034         /* TM_OVERRIDE */
20035         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20036
20037         /* TM_DEFAULT */
20038         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20039
20040         /* QOS_OVERRIDE */
20041         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20042
20043         /* QOS_DEFAULT */
20044         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20045 }
20046 __PACKING_ATTRIBUTE_STRUCT_END__
20047 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG ;
20048 #else
20049 typedef struct
20050 {
20051         /* QOS_DEFAULT */
20052         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20053
20054         /* QOS_OVERRIDE */
20055         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20056
20057         /* TM_DEFAULT */
20058         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20059
20060         /* TM_OVERRIDE */
20061         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20062
20063         /* DM_DEFAULT */
20064         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20065
20066         /* DM_OVERRIDE */
20067         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20068
20069         /* TR_DEFAULT */
20070         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20071
20072         /* LB_EN */
20073         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20074
20075         /* PREF_LB_EN */
20076         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20077
20078         /* DSCP2TCI_TRANS_TBL */
20079         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20080
20081         /* RNR_OVR_DM */
20082         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20083
20084         /* RNR_DEFAULT_DM */
20085         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20086
20087         /* SPARE */
20088         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20089
20090         /* rsv */
20091         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20092 }
20093 __PACKING_ATTRIBUTE_STRUCT_END__
20094 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG ;
20095 #endif
20096
20097 /*****************************************************************************************/
20098 /* IH_CLASS10_GENERAL_CFG                                                                */
20099 /* Set of defaults (general parameters) for IH class10    These parameters used for defa */
20100 /* ult setting per current IH class, used also as characterization of this ingres traffi */
20101 /* c.    The set of aparametrs include:    o    Ingres QoS setting for class & override ena */
20102 /* ble by LUT  o        Destination memory setting per class & override enable by LUT  o        Direct */
20103 /*  mode setting per class & override enable by LUT   o Default target Runner setting pe */
20104 /* r class & load balancing enable + preference enable for load balancing  o    DSCP to TCI */
20105 /*  translation: reference to translation table  o                                            */
20106 /*****************************************************************************************/
20107
20108 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
20109 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
20110 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
20111 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
20112 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
20113 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
20114 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
20115 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
20116 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
20117 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
20118 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
20119 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
20120 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
20121 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
20122 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
20123 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
20124 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
20125 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
20126 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
20127 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
20128 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
20129 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
20130 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
20131 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20132 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20133 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20134 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
20135 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
20136 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
20137 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20138 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20139 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20140 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
20141 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
20142 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
20143 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
20144 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
20145 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
20146 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
20147 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
20148 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
20149 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
20150 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
20151
20152
20153 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_OFFSET ( 0x00000180 )
20154
20155 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_OFFSET )
20156 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_ADDRESS ), (r) )
20157 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG_ADDRESS ), (v) )
20158
20159 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
20160 typedef struct
20161 {
20162         /* rsv */
20163         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20164
20165         /* SPARE */
20166         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20167
20168         /* RNR_DEFAULT_DM */
20169         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20170
20171         /* RNR_OVR_DM */
20172         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20173
20174         /* DSCP2TCI_TRANS_TBL */
20175         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20176
20177         /* PREF_LB_EN */
20178         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20179
20180         /* LB_EN */
20181         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20182
20183         /* TR_DEFAULT */
20184         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20185
20186         /* DM_OVERRIDE */
20187         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20188
20189         /* DM_DEFAULT */
20190         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20191
20192         /* TM_OVERRIDE */
20193         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20194
20195         /* TM_DEFAULT */
20196         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20197
20198         /* QOS_OVERRIDE */
20199         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20200
20201         /* QOS_DEFAULT */
20202         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20203 }
20204 __PACKING_ATTRIBUTE_STRUCT_END__
20205 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG ;
20206 #else
20207 typedef struct
20208 {
20209         /* QOS_DEFAULT */
20210         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20211
20212         /* QOS_OVERRIDE */
20213         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20214
20215         /* TM_DEFAULT */
20216         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20217
20218         /* TM_OVERRIDE */
20219         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20220
20221         /* DM_DEFAULT */
20222         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20223
20224         /* DM_OVERRIDE */
20225         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20226
20227         /* TR_DEFAULT */
20228         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20229
20230         /* LB_EN */
20231         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20232
20233         /* PREF_LB_EN */
20234         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20235
20236         /* DSCP2TCI_TRANS_TBL */
20237         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20238
20239         /* RNR_OVR_DM */
20240         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20241
20242         /* RNR_DEFAULT_DM */
20243         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20244
20245         /* SPARE */
20246         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20247
20248         /* rsv */
20249         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20250 }
20251 __PACKING_ATTRIBUTE_STRUCT_END__
20252 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG ;
20253 #endif
20254
20255 /*****************************************************************************************/
20256 /* IH_CLASS11_GENERAL_CFG                                                                */
20257 /* Set of defaults (general parameters) for IH class11    These parameters used for defa */
20258 /* ult setting per current IH class, used also as characterization of this ingres traffi */
20259 /* c.    The set of aparametrs include:    o    Ingres QoS setting for class & override ena */
20260 /* ble by LUT  o        Destination memory setting per class & override enable by LUT  o        Direct */
20261 /*  mode setting per class & override enable by LUT   o Default target Runner setting pe */
20262 /* r class & load balancing enable + preference enable for load balancing  o    DSCP to TCI */
20263 /*  translation: reference to translation table  o                                            */
20264 /*****************************************************************************************/
20265
20266 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
20267 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
20268 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
20269 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
20270 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
20271 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
20272 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
20273 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
20274 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
20275 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
20276 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
20277 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
20278 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
20279 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
20280 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
20281 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
20282 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
20283 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
20284 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
20285 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
20286 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
20287 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
20288 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
20289 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20290 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20291 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20292 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
20293 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
20294 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
20295 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20296 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20297 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20298 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
20299 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
20300 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
20301 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
20302 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
20303 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
20304 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
20305 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
20306 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
20307 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
20308 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
20309
20310
20311 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_OFFSET ( 0x00000184 )
20312
20313 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_OFFSET )
20314 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_ADDRESS ), (r) )
20315 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG_ADDRESS ), (v) )
20316
20317 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
20318 typedef struct
20319 {
20320         /* rsv */
20321         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20322
20323         /* SPARE */
20324         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20325
20326         /* RNR_DEFAULT_DM */
20327         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20328
20329         /* RNR_OVR_DM */
20330         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20331
20332         /* DSCP2TCI_TRANS_TBL */
20333         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20334
20335         /* PREF_LB_EN */
20336         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20337
20338         /* LB_EN */
20339         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20340
20341         /* TR_DEFAULT */
20342         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20343
20344         /* DM_OVERRIDE */
20345         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20346
20347         /* DM_DEFAULT */
20348         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20349
20350         /* TM_OVERRIDE */
20351         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20352
20353         /* TM_DEFAULT */
20354         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20355
20356         /* QOS_OVERRIDE */
20357         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20358
20359         /* QOS_DEFAULT */
20360         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20361 }
20362 __PACKING_ATTRIBUTE_STRUCT_END__
20363 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG ;
20364 #else
20365 typedef struct
20366 {
20367         /* QOS_DEFAULT */
20368         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20369
20370         /* QOS_OVERRIDE */
20371         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20372
20373         /* TM_DEFAULT */
20374         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20375
20376         /* TM_OVERRIDE */
20377         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20378
20379         /* DM_DEFAULT */
20380         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20381
20382         /* DM_OVERRIDE */
20383         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20384
20385         /* TR_DEFAULT */
20386         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20387
20388         /* LB_EN */
20389         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20390
20391         /* PREF_LB_EN */
20392         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20393
20394         /* DSCP2TCI_TRANS_TBL */
20395         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20396
20397         /* RNR_OVR_DM */
20398         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20399
20400         /* RNR_DEFAULT_DM */
20401         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20402
20403         /* SPARE */
20404         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20405
20406         /* rsv */
20407         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20408 }
20409 __PACKING_ATTRIBUTE_STRUCT_END__
20410 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG ;
20411 #endif
20412
20413 /*****************************************************************************************/
20414 /* IH_CLASS12_GENERAL_CFG                                                                */
20415 /* Set of defaults (general parameters) for IH class12    These parameters used for defa */
20416 /* ult setting per current IH class, used also as characterization of this ingres traffi */
20417 /* c.    The set of aparametrs include:    o    Ingres QoS setting for class & override ena */
20418 /* ble by LUT  o        Destination memory setting per class & override enable by LUT  o        Direct */
20419 /*  mode setting per class & override enable by LUT   o Default target Runner setting pe */
20420 /* r class & load balancing enable + preference enable for load balancing  o    DSCP to TCI */
20421 /*  translation: reference to translation table  o                                            */
20422 /*****************************************************************************************/
20423
20424 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
20425 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
20426 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
20427 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
20428 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
20429 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
20430 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
20431 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
20432 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
20433 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
20434 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
20435 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
20436 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
20437 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
20438 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
20439 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
20440 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
20441 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
20442 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
20443 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
20444 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
20445 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
20446 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
20447 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20448 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20449 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20450 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
20451 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
20452 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
20453 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20454 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20455 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20456 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
20457 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
20458 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
20459 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
20460 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
20461 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
20462 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
20463 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
20464 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
20465 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
20466 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
20467
20468
20469 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_OFFSET ( 0x00000188 )
20470
20471 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_OFFSET )
20472 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_ADDRESS ), (r) )
20473 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG_ADDRESS ), (v) )
20474
20475 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
20476 typedef struct
20477 {
20478         /* rsv */
20479         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20480
20481         /* SPARE */
20482         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20483
20484         /* RNR_DEFAULT_DM */
20485         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20486
20487         /* RNR_OVR_DM */
20488         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20489
20490         /* DSCP2TCI_TRANS_TBL */
20491         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20492
20493         /* PREF_LB_EN */
20494         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20495
20496         /* LB_EN */
20497         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20498
20499         /* TR_DEFAULT */
20500         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20501
20502         /* DM_OVERRIDE */
20503         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20504
20505         /* DM_DEFAULT */
20506         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20507
20508         /* TM_OVERRIDE */
20509         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20510
20511         /* TM_DEFAULT */
20512         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20513
20514         /* QOS_OVERRIDE */
20515         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20516
20517         /* QOS_DEFAULT */
20518         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20519 }
20520 __PACKING_ATTRIBUTE_STRUCT_END__
20521 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG ;
20522 #else
20523 typedef struct
20524 {
20525         /* QOS_DEFAULT */
20526         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20527
20528         /* QOS_OVERRIDE */
20529         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20530
20531         /* TM_DEFAULT */
20532         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20533
20534         /* TM_OVERRIDE */
20535         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20536
20537         /* DM_DEFAULT */
20538         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20539
20540         /* DM_OVERRIDE */
20541         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20542
20543         /* TR_DEFAULT */
20544         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20545
20546         /* LB_EN */
20547         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20548
20549         /* PREF_LB_EN */
20550         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20551
20552         /* DSCP2TCI_TRANS_TBL */
20553         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20554
20555         /* RNR_OVR_DM */
20556         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20557
20558         /* RNR_DEFAULT_DM */
20559         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20560
20561         /* SPARE */
20562         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20563
20564         /* rsv */
20565         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20566 }
20567 __PACKING_ATTRIBUTE_STRUCT_END__
20568 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG ;
20569 #endif
20570
20571 /*****************************************************************************************/
20572 /* IH_CLASS13_GENERAL_CFG                                                                */
20573 /* Set of defaults (general parameters) for IH class13    These parameters used for defa */
20574 /* ult setting per current IH class, used also as characterization of this ingres traffi */
20575 /* c.    The set of aparametrs include:    o    Ingres QoS setting for class & override ena */
20576 /* ble by LUT  o        Destination memory setting per class & override enable by LUT  o        Direct */
20577 /*  mode setting per class & override enable by LUT   o Default target Runner setting pe */
20578 /* r class & load balancing enable + preference enable for load balancing  o    DSCP to TCI */
20579 /*  translation: reference to translation table  o                                            */
20580 /*****************************************************************************************/
20581
20582 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
20583 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
20584 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
20585 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
20586 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
20587 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
20588 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
20589 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
20590 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
20591 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
20592 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
20593 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
20594 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
20595 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
20596 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
20597 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
20598 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
20599 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
20600 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
20601 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
20602 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
20603 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
20604 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
20605 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20606 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20607 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20608 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
20609 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
20610 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
20611 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20612 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20613 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20614 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
20615 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
20616 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
20617 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
20618 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
20619 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
20620 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
20621 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
20622 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
20623 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
20624 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
20625
20626
20627 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_OFFSET ( 0x0000018C )
20628
20629 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_OFFSET )
20630 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_ADDRESS ), (r) )
20631 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG_ADDRESS ), (v) )
20632
20633 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
20634 typedef struct
20635 {
20636         /* rsv */
20637         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20638
20639         /* SPARE */
20640         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20641
20642         /* RNR_DEFAULT_DM */
20643         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20644
20645         /* RNR_OVR_DM */
20646         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20647
20648         /* DSCP2TCI_TRANS_TBL */
20649         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20650
20651         /* PREF_LB_EN */
20652         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20653
20654         /* LB_EN */
20655         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20656
20657         /* TR_DEFAULT */
20658         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20659
20660         /* DM_OVERRIDE */
20661         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20662
20663         /* DM_DEFAULT */
20664         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20665
20666         /* TM_OVERRIDE */
20667         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20668
20669         /* TM_DEFAULT */
20670         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20671
20672         /* QOS_OVERRIDE */
20673         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20674
20675         /* QOS_DEFAULT */
20676         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20677 }
20678 __PACKING_ATTRIBUTE_STRUCT_END__
20679 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG ;
20680 #else
20681 typedef struct
20682 {
20683         /* QOS_DEFAULT */
20684         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20685
20686         /* QOS_OVERRIDE */
20687         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20688
20689         /* TM_DEFAULT */
20690         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20691
20692         /* TM_OVERRIDE */
20693         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20694
20695         /* DM_DEFAULT */
20696         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20697
20698         /* DM_OVERRIDE */
20699         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20700
20701         /* TR_DEFAULT */
20702         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20703
20704         /* LB_EN */
20705         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20706
20707         /* PREF_LB_EN */
20708         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20709
20710         /* DSCP2TCI_TRANS_TBL */
20711         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20712
20713         /* RNR_OVR_DM */
20714         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20715
20716         /* RNR_DEFAULT_DM */
20717         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20718
20719         /* SPARE */
20720         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20721
20722         /* rsv */
20723         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20724 }
20725 __PACKING_ATTRIBUTE_STRUCT_END__
20726 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG ;
20727 #endif
20728
20729 /*****************************************************************************************/
20730 /* IH_CLASS14_GENERAL_CFG                                                                */
20731 /* Set of defaults (general parameters) for IH class14    These parameters used for defa */
20732 /* ult setting per current IH class, used also as characterization of this ingres traffi */
20733 /* c.    The set of aparametrs include:    o    Ingres QoS setting for class & override ena */
20734 /* ble by LUT  o        Destination memory setting per class & override enable by LUT  o        Direct */
20735 /*  mode setting per class & override enable by LUT   o Default target Runner setting pe */
20736 /* r class & load balancing enable + preference enable for load balancing  o    DSCP to TCI */
20737 /*  translation: reference to translation table  o                                            */
20738 /*****************************************************************************************/
20739
20740 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
20741 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
20742 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
20743 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
20744 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
20745 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
20746 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
20747 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
20748 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
20749 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
20750 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
20751 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
20752 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
20753 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
20754 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
20755 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
20756 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
20757 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
20758 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
20759 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
20760 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
20761 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
20762 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
20763 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20764 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20765 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20766 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
20767 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
20768 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
20769 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20770 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20771 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20772 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
20773 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
20774 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
20775 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
20776 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
20777 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
20778 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
20779 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
20780 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
20781 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
20782 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
20783
20784
20785 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_OFFSET ( 0x00000190 )
20786
20787 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_OFFSET )
20788 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_ADDRESS ), (r) )
20789 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG_ADDRESS ), (v) )
20790
20791 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
20792 typedef struct
20793 {
20794         /* rsv */
20795         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20796
20797         /* SPARE */
20798         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20799
20800         /* RNR_DEFAULT_DM */
20801         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20802
20803         /* RNR_OVR_DM */
20804         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20805
20806         /* DSCP2TCI_TRANS_TBL */
20807         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20808
20809         /* PREF_LB_EN */
20810         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20811
20812         /* LB_EN */
20813         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20814
20815         /* TR_DEFAULT */
20816         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20817
20818         /* DM_OVERRIDE */
20819         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20820
20821         /* DM_DEFAULT */
20822         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20823
20824         /* TM_OVERRIDE */
20825         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20826
20827         /* TM_DEFAULT */
20828         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20829
20830         /* QOS_OVERRIDE */
20831         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20832
20833         /* QOS_DEFAULT */
20834         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20835 }
20836 __PACKING_ATTRIBUTE_STRUCT_END__
20837 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG ;
20838 #else
20839 typedef struct
20840 {
20841         /* QOS_DEFAULT */
20842         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20843
20844         /* QOS_OVERRIDE */
20845         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20846
20847         /* TM_DEFAULT */
20848         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20849
20850         /* TM_OVERRIDE */
20851         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20852
20853         /* DM_DEFAULT */
20854         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20855
20856         /* DM_OVERRIDE */
20857         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20858
20859         /* TR_DEFAULT */
20860         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20861
20862         /* LB_EN */
20863         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20864
20865         /* PREF_LB_EN */
20866         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20867
20868         /* DSCP2TCI_TRANS_TBL */
20869         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20870
20871         /* RNR_OVR_DM */
20872         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20873
20874         /* RNR_DEFAULT_DM */
20875         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20876
20877         /* SPARE */
20878         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20879
20880         /* rsv */
20881         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20882 }
20883 __PACKING_ATTRIBUTE_STRUCT_END__
20884 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG ;
20885 #endif
20886
20887 /*****************************************************************************************/
20888 /* IH_CLASS15_GENERAL_CFG                                                                */
20889 /* Set of defaults (general parameters) for IH class15    These parameters used for defa */
20890 /* ult setting per current IH class, used also as characterization of this ingres traffi */
20891 /* c.    The set of aparametrs include:    o    Ingres QoS setting for class & override ena */
20892 /* ble by LUT  o        Destination memory setting per class & override enable by LUT  o        Direct */
20893 /*  mode setting per class & override enable by LUT   o Default target Runner setting pe */
20894 /* r class & load balancing enable + preference enable for load balancing  o    DSCP to TCI */
20895 /*  translation: reference to translation table  o                                            */
20896 /*****************************************************************************************/
20897
20898 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RSV_RSV_VALUE                               ( 0x0 )
20899 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RSV_RSV_VALUE_RESET_VALUE                   ( 0x0 )
20900 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_SPARE_RNRA_VALUE                            ( 0x0 )
20901 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_SPARE_RNRA_VALUE_RESET_VALUE                ( 0x0 )
20902 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_SPARE_RNRB_VALUE                            ( 0x1 )
20903 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE                   ( 0x0 )
20904 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_DEFAULT_DM_RNRA_VALUE_RESET_VALUE       ( 0x0 )
20905 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_DEFAULT_DM_RNRB_VALUE                   ( 0x1 )
20906 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE               ( 0x0 )
20907 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_OVR_DM_NON_OVERIIDE_VALUE_RESET_VALUE   ( 0x0 )
20908 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_RNR_OVR_DM_OVERIIDE_VALUE                   ( 0x1 )
20909 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE             ( 0x0 )
20910 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE0_VALUE_RESET_VALUE ( 0x0 )
20911 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DSCP2TCI_TRANS_TBL_TABLE1_VALUE             ( 0x1 )
20912 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE                   ( 0x0 )
20913 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_PREF_LB_EN_DISABLED_VALUE_RESET_VALUE       ( 0x0 )
20914 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_PREF_LB_EN_ENABLED_VALUE                    ( 0x1 )
20915 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_LB_EN_DISABLED_VALUE                        ( 0x0 )
20916 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_LB_EN_DISABLED_VALUE_RESET_VALUE            ( 0x0 )
20917 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_LB_EN_ENABLED_VALUE                         ( 0x1 )
20918 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE                       ( 0x0 )
20919 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TR_DEFAULT_RNRA_VALUE_RESET_VALUE           ( 0x0 )
20920 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TR_DEFAULT_RNRB_VALUE                       ( 0x1 )
20921 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20922 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20923 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20924 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE                 ( 0x0 )
20925 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_DEFAULT_NON_DIRECT_VALUE_RESET_VALUE     ( 0x0 )
20926 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_DM_DEFAULT_DIRECT_VALUE                     ( 0x1 )
20927 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE                  ( 0x0 )
20928 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_OVERRIDE_DISABLED_VALUE_RESET_VALUE      ( 0x0 )
20929 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_OVERRIDE_ENABLED_VALUE                   ( 0x1 )
20930 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_DEFAULT_DDR_VALUE                        ( 0x0 )
20931 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_DEFAULT_DDR_VALUE_RESET_VALUE            ( 0x0 )
20932 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_TM_DEFAULT_SRAM_VALUE                       ( 0x1 )
20933 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE                 ( 0x0 )
20934 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_OVERRIDE_DISABLED_VALUE_RESET_VALUE     ( 0x0 )
20935 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_OVERRIDE_ENABLED_VALUE                  ( 0x1 )
20936 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE                       ( 0x0 )
20937 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_LOW_VALUE_RESET_VALUE           ( 0x0 )
20938 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_HIGH_VALUE                      ( 0x1 )
20939 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_RESERVED_EXCL_PLOAM_VALUE       ( 0x2 )
20940 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_QOS_DEFAULT_EXCL_VALUE                      ( 0x3 )
20941
20942
20943 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_OFFSET ( 0x00000194 )
20944
20945 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_OFFSET )
20946 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_ADDRESS ), (r) )
20947 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG_ADDRESS ), (v) )
20948
20949 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
20950 typedef struct
20951 {
20952         /* rsv */
20953         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20954
20955         /* SPARE */
20956         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20957
20958         /* RNR_DEFAULT_DM */
20959         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20960
20961         /* RNR_OVR_DM */
20962         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20963
20964         /* DSCP2TCI_TRANS_TBL */
20965         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20966
20967         /* PREF_LB_EN */
20968         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20969
20970         /* LB_EN */
20971         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20972
20973         /* TR_DEFAULT */
20974         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20975
20976         /* DM_OVERRIDE */
20977         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20978
20979         /* DM_DEFAULT */
20980         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20981
20982         /* TM_OVERRIDE */
20983         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20984
20985         /* TM_DEFAULT */
20986         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20987
20988         /* QOS_OVERRIDE */
20989         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20990
20991         /* QOS_DEFAULT */
20992         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
20993 }
20994 __PACKING_ATTRIBUTE_STRUCT_END__
20995 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG ;
20996 #else
20997 typedef struct
20998 {
20999         /* QOS_DEFAULT */
21000         uint32_t qos_default            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21001
21002         /* QOS_OVERRIDE */
21003         uint32_t qos_override           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21004
21005         /* TM_DEFAULT */
21006         uint32_t tm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21007
21008         /* TM_OVERRIDE */
21009         uint32_t tm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21010
21011         /* DM_DEFAULT */
21012         uint32_t dm_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21013
21014         /* DM_OVERRIDE */
21015         uint32_t dm_override            : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21016
21017         /* TR_DEFAULT */
21018         uint32_t tr_default             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21019
21020         /* LB_EN */
21021         uint32_t lb_en                  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21022
21023         /* PREF_LB_EN */
21024         uint32_t pref_lb_en             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21025
21026         /* DSCP2TCI_TRANS_TBL */
21027         uint32_t dscp2tci_trans_tbl     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21028
21029         /* RNR_OVR_DM */
21030         uint32_t rnr_ovr_dm             : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21031
21032         /* RNR_DEFAULT_DM */
21033         uint32_t rnr_default_dm         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21034
21035         /* SPARE */
21036         uint32_t spare                  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21037
21038         /* rsv */
21039         uint32_t rsv                    : 17 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21040 }
21041 __PACKING_ATTRIBUTE_STRUCT_END__
21042 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG ;
21043 #endif
21044
21045 /*****************************************************************************************/
21046 /* IH_CLASS0_SEARCH_CFG                                                                  */
21047 /* Set of search parametrs for IH class0    These parameters used for search setting per */
21048 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
21049 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
21050 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
21051 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
21052 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
21053 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
21054 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
21055 /* n of them)                                                                            */
21056 /*****************************************************************************************/
21057
21058 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
21059 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
21060 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
21061 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
21062 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
21063 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
21064 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
21065 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
21066 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
21067 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
21068 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
21069 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
21070 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
21071 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
21072 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
21073 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
21074 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
21075 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21076 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21077 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21078 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21079 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21080 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21081 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21082 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21083 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21084 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21085 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21086 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21087 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21088 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21089 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21090 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21091 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21092 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21093 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21094 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21095 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21096 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21097 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21098 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21099 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21100 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21101 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21102 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21103 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21104 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21105 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21106 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21107 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21108 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21109 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21110 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21111 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21112 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21113 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21114 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21115 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21116 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21117 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21118 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21119 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21120 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21121 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21122 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21123 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21124 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21125 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21126 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21127 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21128 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21129 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21130 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21131 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21132 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21133 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21134 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21135 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21136 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21137 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21138 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21139 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21140 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21141 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21142 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21143
21144
21145 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_OFFSET ( 0x00000198 )
21146
21147 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_OFFSET )
21148 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_ADDRESS ), (r) )
21149 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG_ADDRESS ), (v) )
21150
21151 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
21152 typedef struct
21153 {
21154         /* rsv */
21155         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21156
21157         /* DROP_ON_MISS_EXTR_CFG */
21158         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21159
21160         /* DP_EXTR_CFG */
21161         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21162
21163         /* QOS_EXTR_CFG */
21164         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21165
21166         /* SEARCH4_LKUP_TBL_REF */
21167         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21168
21169         /* SEARCH3_LKUP_TBL_REF */
21170         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21171
21172         /* SEARCH2_LKUP_TBL_REF */
21173         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21174
21175         /* SEARCH1_LKUP_TBL_REF */
21176         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21177 }
21178 __PACKING_ATTRIBUTE_STRUCT_END__
21179 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG ;
21180 #else
21181 typedef struct
21182 {
21183         /* SEARCH1_LKUP_TBL_REF */
21184         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21185
21186         /* SEARCH2_LKUP_TBL_REF */
21187         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21188
21189         /* SEARCH3_LKUP_TBL_REF */
21190         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21191
21192         /* SEARCH4_LKUP_TBL_REF */
21193         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21194
21195         /* QOS_EXTR_CFG */
21196         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21197
21198         /* DP_EXTR_CFG */
21199         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21200
21201         /* DROP_ON_MISS_EXTR_CFG */
21202         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21203
21204         /* rsv */
21205         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21206 }
21207 __PACKING_ATTRIBUTE_STRUCT_END__
21208 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG ;
21209 #endif
21210
21211 /*****************************************************************************************/
21212 /* IH_CLASS1_SEARCH_CFG                                                                  */
21213 /* Set of search parametrs for IH class1    These parameters used for search setting per */
21214 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
21215 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
21216 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
21217 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
21218 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
21219 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
21220 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
21221 /* n of them)                                                                            */
21222 /*****************************************************************************************/
21223
21224 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
21225 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
21226 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
21227 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
21228 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
21229 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
21230 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
21231 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
21232 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
21233 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
21234 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
21235 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
21236 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
21237 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
21238 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
21239 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
21240 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
21241 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21242 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21243 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21244 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21245 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21246 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21247 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21248 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21249 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21250 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21251 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21252 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21253 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21254 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21255 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21256 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21257 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21258 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21259 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21260 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21261 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21262 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21263 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21264 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21265 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21266 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21267 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21268 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21269 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21270 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21271 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21272 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21273 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21274 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21275 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21276 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21277 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21278 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21279 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21280 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21281 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21282 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21283 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21284 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21285 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21286 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21287 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21288 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21289 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21290 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21291 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21292 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21293 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21294 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21295 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21296 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21297 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21298 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21299 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21300 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21301 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21302 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21303 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21304 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21305 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21306 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21307 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21308 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21309
21310
21311 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_OFFSET ( 0x0000019C )
21312
21313 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_OFFSET )
21314 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_ADDRESS ), (r) )
21315 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG_ADDRESS ), (v) )
21316
21317 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
21318 typedef struct
21319 {
21320         /* rsv */
21321         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21322
21323         /* DROP_ON_MISS_EXTR_CFG */
21324         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21325
21326         /* DP_EXTR_CFG */
21327         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21328
21329         /* QOS_EXTR_CFG */
21330         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21331
21332         /* SEARCH4_LKUP_TBL_REF */
21333         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21334
21335         /* SEARCH3_LKUP_TBL_REF */
21336         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21337
21338         /* SEARCH2_LKUP_TBL_REF */
21339         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21340
21341         /* SEARCH1_LKUP_TBL_REF */
21342         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21343 }
21344 __PACKING_ATTRIBUTE_STRUCT_END__
21345 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG ;
21346 #else
21347 typedef struct
21348 {
21349         /* SEARCH1_LKUP_TBL_REF */
21350         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21351
21352         /* SEARCH2_LKUP_TBL_REF */
21353         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21354
21355         /* SEARCH3_LKUP_TBL_REF */
21356         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21357
21358         /* SEARCH4_LKUP_TBL_REF */
21359         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21360
21361         /* QOS_EXTR_CFG */
21362         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21363
21364         /* DP_EXTR_CFG */
21365         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21366
21367         /* DROP_ON_MISS_EXTR_CFG */
21368         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21369
21370         /* rsv */
21371         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21372 }
21373 __PACKING_ATTRIBUTE_STRUCT_END__
21374 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG ;
21375 #endif
21376
21377 /*****************************************************************************************/
21378 /* IH_CLASS2_SEARCH_CFG                                                                  */
21379 /* Set of search parametrs for IH class2    These parameters used for search setting per */
21380 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
21381 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
21382 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
21383 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
21384 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
21385 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
21386 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
21387 /* n of them)                                                                            */
21388 /*****************************************************************************************/
21389
21390 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
21391 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
21392 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
21393 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
21394 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
21395 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
21396 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
21397 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
21398 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
21399 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
21400 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
21401 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
21402 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
21403 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
21404 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
21405 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
21406 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
21407 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21408 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21409 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21410 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21411 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21412 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21413 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21414 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21415 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21416 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21417 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21418 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21419 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21420 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21421 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21422 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21423 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21424 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21425 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21426 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21427 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21428 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21429 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21430 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21431 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21432 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21433 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21434 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21435 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21436 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21437 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21438 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21439 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21440 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21441 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21442 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21443 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21444 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21445 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21446 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21447 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21448 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21449 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21450 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21451 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21452 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21453 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21454 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21455 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21456 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21457 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21458 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21459 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21460 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21461 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21462 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21463 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21464 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21465 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21466 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21467 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21468 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21469 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21470 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21471 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21472 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21473 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21474 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21475
21476
21477 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_OFFSET ( 0x00000200 )
21478
21479 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_OFFSET )
21480 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_ADDRESS ), (r) )
21481 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG_ADDRESS ), (v) )
21482
21483 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
21484 typedef struct
21485 {
21486         /* rsv */
21487         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21488
21489         /* DROP_ON_MISS_EXTR_CFG */
21490         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21491
21492         /* DP_EXTR_CFG */
21493         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21494
21495         /* QOS_EXTR_CFG */
21496         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21497
21498         /* SEARCH4_LKUP_TBL_REF */
21499         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21500
21501         /* SEARCH3_LKUP_TBL_REF */
21502         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21503
21504         /* SEARCH2_LKUP_TBL_REF */
21505         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21506
21507         /* SEARCH1_LKUP_TBL_REF */
21508         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21509 }
21510 __PACKING_ATTRIBUTE_STRUCT_END__
21511 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG ;
21512 #else
21513 typedef struct
21514 {
21515         /* SEARCH1_LKUP_TBL_REF */
21516         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21517
21518         /* SEARCH2_LKUP_TBL_REF */
21519         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21520
21521         /* SEARCH3_LKUP_TBL_REF */
21522         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21523
21524         /* SEARCH4_LKUP_TBL_REF */
21525         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21526
21527         /* QOS_EXTR_CFG */
21528         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21529
21530         /* DP_EXTR_CFG */
21531         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21532
21533         /* DROP_ON_MISS_EXTR_CFG */
21534         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21535
21536         /* rsv */
21537         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21538 }
21539 __PACKING_ATTRIBUTE_STRUCT_END__
21540 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG ;
21541 #endif
21542
21543 /*****************************************************************************************/
21544 /* IH_CLASS3_SEARCH_CFG                                                                  */
21545 /* Set of search parametrs for IH class3    These parameters used for search setting per */
21546 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
21547 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
21548 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
21549 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
21550 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
21551 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
21552 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
21553 /* n of them)                                                                            */
21554 /*****************************************************************************************/
21555
21556 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
21557 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
21558 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
21559 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
21560 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
21561 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
21562 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
21563 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
21564 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
21565 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
21566 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
21567 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
21568 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
21569 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
21570 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
21571 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
21572 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
21573 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21574 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21575 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21576 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21577 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21578 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21579 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21580 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21581 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21582 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21583 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21584 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21585 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21586 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21587 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21588 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21589 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21590 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21591 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21592 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21593 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21594 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21595 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21596 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21597 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21598 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21599 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21600 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21601 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21602 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21603 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21604 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21605 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21606 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21607 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21608 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21609 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21610 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21611 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21612 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21613 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21614 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21615 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21616 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21617 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21618 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21619 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21620 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21621 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21622 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21623 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21624 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21625 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21626 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21627 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21628 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21629 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21630 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21631 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21632 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21633 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21634 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21635 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21636 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21637 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21638 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21639 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21640 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21641
21642
21643 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_OFFSET ( 0x00000204 )
21644
21645 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_OFFSET )
21646 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_ADDRESS ), (r) )
21647 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG_ADDRESS ), (v) )
21648
21649 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
21650 typedef struct
21651 {
21652         /* rsv */
21653         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21654
21655         /* DROP_ON_MISS_EXTR_CFG */
21656         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21657
21658         /* DP_EXTR_CFG */
21659         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21660
21661         /* QOS_EXTR_CFG */
21662         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21663
21664         /* SEARCH4_LKUP_TBL_REF */
21665         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21666
21667         /* SEARCH3_LKUP_TBL_REF */
21668         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21669
21670         /* SEARCH2_LKUP_TBL_REF */
21671         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21672
21673         /* SEARCH1_LKUP_TBL_REF */
21674         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21675 }
21676 __PACKING_ATTRIBUTE_STRUCT_END__
21677 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG ;
21678 #else
21679 typedef struct
21680 {
21681         /* SEARCH1_LKUP_TBL_REF */
21682         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21683
21684         /* SEARCH2_LKUP_TBL_REF */
21685         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21686
21687         /* SEARCH3_LKUP_TBL_REF */
21688         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21689
21690         /* SEARCH4_LKUP_TBL_REF */
21691         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21692
21693         /* QOS_EXTR_CFG */
21694         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21695
21696         /* DP_EXTR_CFG */
21697         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21698
21699         /* DROP_ON_MISS_EXTR_CFG */
21700         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21701
21702         /* rsv */
21703         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21704 }
21705 __PACKING_ATTRIBUTE_STRUCT_END__
21706 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG ;
21707 #endif
21708
21709 /*****************************************************************************************/
21710 /* IH_CLASS4_SEARCH_CFG                                                                  */
21711 /* Set of search parametrs for IH class1    These parameters used for search setting per */
21712 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
21713 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
21714 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
21715 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
21716 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
21717 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
21718 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
21719 /* n of them)                                                                            */
21720 /*****************************************************************************************/
21721
21722 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
21723 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
21724 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
21725 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
21726 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
21727 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
21728 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
21729 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
21730 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
21731 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
21732 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
21733 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
21734 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
21735 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
21736 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
21737 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
21738 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
21739 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21740 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21741 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21742 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21743 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21744 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21745 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21746 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21747 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21748 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21749 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21750 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21751 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21752 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21753 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21754 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21755 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21756 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21757 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21758 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21759 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21760 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21761 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21762 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21763 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21764 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21765 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21766 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21767 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21768 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21769 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21770 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21771 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21772 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21773 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21774 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21775 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21776 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21777 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21778 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21779 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21780 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21781 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21782 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21783 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21784 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21785 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21786 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21787 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21788 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21789 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21790 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21791 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21792 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21793 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21794 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21795 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21796 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21797 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21798 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21799 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21800 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21801 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21802 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21803 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21804 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21805 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21806 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21807
21808
21809 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_OFFSET ( 0x00000208 )
21810
21811 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_OFFSET )
21812 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_ADDRESS ), (r) )
21813 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG_ADDRESS ), (v) )
21814
21815 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
21816 typedef struct
21817 {
21818         /* rsv */
21819         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21820
21821         /* DROP_ON_MISS_EXTR_CFG */
21822         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21823
21824         /* DP_EXTR_CFG */
21825         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21826
21827         /* QOS_EXTR_CFG */
21828         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21829
21830         /* SEARCH4_LKUP_TBL_REF */
21831         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21832
21833         /* SEARCH3_LKUP_TBL_REF */
21834         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21835
21836         /* SEARCH2_LKUP_TBL_REF */
21837         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21838
21839         /* SEARCH1_LKUP_TBL_REF */
21840         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21841 }
21842 __PACKING_ATTRIBUTE_STRUCT_END__
21843 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG ;
21844 #else
21845 typedef struct
21846 {
21847         /* SEARCH1_LKUP_TBL_REF */
21848         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21849
21850         /* SEARCH2_LKUP_TBL_REF */
21851         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21852
21853         /* SEARCH3_LKUP_TBL_REF */
21854         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21855
21856         /* SEARCH4_LKUP_TBL_REF */
21857         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21858
21859         /* QOS_EXTR_CFG */
21860         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21861
21862         /* DP_EXTR_CFG */
21863         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21864
21865         /* DROP_ON_MISS_EXTR_CFG */
21866         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21867
21868         /* rsv */
21869         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21870 }
21871 __PACKING_ATTRIBUTE_STRUCT_END__
21872 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG ;
21873 #endif
21874
21875 /*****************************************************************************************/
21876 /* IH_CLASS5_SEARCH_CFG                                                                  */
21877 /* Set of search parametrs for IH class5    These parameters used for search setting per */
21878 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
21879 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
21880 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
21881 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
21882 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
21883 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
21884 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
21885 /* n of them)                                                                            */
21886 /*****************************************************************************************/
21887
21888 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
21889 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
21890 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
21891 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
21892 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
21893 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
21894 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
21895 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
21896 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
21897 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
21898 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
21899 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
21900 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
21901 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
21902 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
21903 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
21904 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
21905 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21906 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21907 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21908 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21909 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21910 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21911 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21912 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21913 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21914 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21915 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21916 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21917 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21918 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21919 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21920 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21921 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21922 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21923 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21924 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21925 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21926 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21927 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21928 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21929 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21930 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21931 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21932 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21933 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21934 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21935 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21936 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21937 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21938 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21939 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21940 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21941 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21942 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21943 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21944 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21945 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21946 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21947 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21948 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21949 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21950 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21951 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21952 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21953 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21954 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21955 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21956 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
21957 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
21958 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
21959 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
21960 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
21961 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
21962 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
21963 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
21964 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
21965 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
21966 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
21967 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
21968 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
21969 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
21970 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
21971 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
21972 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
21973
21974
21975 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_OFFSET ( 0x0000020C )
21976
21977 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_OFFSET )
21978 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_ADDRESS ), (r) )
21979 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG_ADDRESS ), (v) )
21980
21981 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
21982 typedef struct
21983 {
21984         /* rsv */
21985         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21986
21987         /* DROP_ON_MISS_EXTR_CFG */
21988         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21989
21990         /* DP_EXTR_CFG */
21991         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21992
21993         /* QOS_EXTR_CFG */
21994         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21995
21996         /* SEARCH4_LKUP_TBL_REF */
21997         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
21998
21999         /* SEARCH3_LKUP_TBL_REF */
22000         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22001
22002         /* SEARCH2_LKUP_TBL_REF */
22003         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22004
22005         /* SEARCH1_LKUP_TBL_REF */
22006         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22007 }
22008 __PACKING_ATTRIBUTE_STRUCT_END__
22009 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG ;
22010 #else
22011 typedef struct
22012 {
22013         /* SEARCH1_LKUP_TBL_REF */
22014         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22015
22016         /* SEARCH2_LKUP_TBL_REF */
22017         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22018
22019         /* SEARCH3_LKUP_TBL_REF */
22020         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22021
22022         /* SEARCH4_LKUP_TBL_REF */
22023         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22024
22025         /* QOS_EXTR_CFG */
22026         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22027
22028         /* DP_EXTR_CFG */
22029         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22030
22031         /* DROP_ON_MISS_EXTR_CFG */
22032         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22033
22034         /* rsv */
22035         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22036 }
22037 __PACKING_ATTRIBUTE_STRUCT_END__
22038 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG ;
22039 #endif
22040
22041 /*****************************************************************************************/
22042 /* IH_CLASS6_SEARCH_CFG                                                                  */
22043 /* Set of search parametrs for IH class6    These parameters used for search setting per */
22044 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
22045 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
22046 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
22047 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
22048 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
22049 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
22050 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
22051 /* n of them)                                                                            */
22052 /*****************************************************************************************/
22053
22054 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
22055 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
22056 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
22057 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
22058 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
22059 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
22060 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
22061 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
22062 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
22063 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
22064 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
22065 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
22066 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
22067 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
22068 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
22069 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
22070 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
22071 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22072 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22073 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22074 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22075 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22076 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22077 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22078 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22079 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22080 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22081 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22082 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22083 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22084 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22085 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22086 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22087 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22088 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22089 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22090 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22091 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22092 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22093 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22094 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22095 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22096 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22097 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22098 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22099 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22100 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22101 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22102 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22103 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22104 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22105 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22106 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22107 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22108 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22109 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22110 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22111 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22112 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22113 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22114 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22115 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22116 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22117 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22118 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22119 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22120 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22121 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22122 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22123 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22124 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22125 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22126 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22127 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22128 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22129 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22130 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22131 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22132 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22133 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22134 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22135 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22136 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22137 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22138 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22139
22140
22141 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_OFFSET ( 0x00000210 )
22142
22143 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_OFFSET )
22144 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_ADDRESS ), (r) )
22145 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG_ADDRESS ), (v) )
22146
22147 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
22148 typedef struct
22149 {
22150         /* rsv */
22151         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22152
22153         /* DROP_ON_MISS_EXTR_CFG */
22154         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22155
22156         /* DP_EXTR_CFG */
22157         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22158
22159         /* QOS_EXTR_CFG */
22160         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22161
22162         /* SEARCH4_LKUP_TBL_REF */
22163         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22164
22165         /* SEARCH3_LKUP_TBL_REF */
22166         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22167
22168         /* SEARCH2_LKUP_TBL_REF */
22169         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22170
22171         /* SEARCH1_LKUP_TBL_REF */
22172         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22173 }
22174 __PACKING_ATTRIBUTE_STRUCT_END__
22175 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG ;
22176 #else
22177 typedef struct
22178 {
22179         /* SEARCH1_LKUP_TBL_REF */
22180         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22181
22182         /* SEARCH2_LKUP_TBL_REF */
22183         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22184
22185         /* SEARCH3_LKUP_TBL_REF */
22186         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22187
22188         /* SEARCH4_LKUP_TBL_REF */
22189         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22190
22191         /* QOS_EXTR_CFG */
22192         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22193
22194         /* DP_EXTR_CFG */
22195         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22196
22197         /* DROP_ON_MISS_EXTR_CFG */
22198         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22199
22200         /* rsv */
22201         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22202 }
22203 __PACKING_ATTRIBUTE_STRUCT_END__
22204 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG ;
22205 #endif
22206
22207 /*****************************************************************************************/
22208 /* IH_CLASS7_SEARCH_CFG                                                                  */
22209 /* Set of search parametrs for IH class7    These parameters used for search setting per */
22210 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
22211 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
22212 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
22213 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
22214 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
22215 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
22216 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
22217 /* n of them)                                                                            */
22218 /*****************************************************************************************/
22219
22220 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
22221 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
22222 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
22223 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
22224 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
22225 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
22226 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
22227 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
22228 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
22229 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
22230 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
22231 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
22232 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
22233 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
22234 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
22235 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
22236 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
22237 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22238 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22239 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22240 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22241 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22242 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22243 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22244 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22245 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22246 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22247 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22248 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22249 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22250 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22251 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22252 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22253 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22254 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22255 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22256 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22257 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22258 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22259 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22260 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22261 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22262 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22263 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22264 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22265 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22266 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22267 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22268 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22269 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22270 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22271 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22272 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22273 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22274 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22275 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22276 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22277 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22278 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22279 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22280 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22281 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22282 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22283 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22284 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22285 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22286 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22287 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22288 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22289 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22290 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22291 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22292 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22293 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22294 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22295 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22296 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22297 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22298 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22299 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22300 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22301 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22302 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22303 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22304 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22305
22306
22307 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_OFFSET ( 0x00000214 )
22308
22309 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_OFFSET )
22310 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_ADDRESS ), (r) )
22311 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG_ADDRESS ), (v) )
22312
22313 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
22314 typedef struct
22315 {
22316         /* rsv */
22317         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22318
22319         /* DROP_ON_MISS_EXTR_CFG */
22320         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22321
22322         /* DP_EXTR_CFG */
22323         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22324
22325         /* QOS_EXTR_CFG */
22326         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22327
22328         /* SEARCH4_LKUP_TBL_REF */
22329         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22330
22331         /* SEARCH3_LKUP_TBL_REF */
22332         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22333
22334         /* SEARCH2_LKUP_TBL_REF */
22335         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22336
22337         /* SEARCH1_LKUP_TBL_REF */
22338         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22339 }
22340 __PACKING_ATTRIBUTE_STRUCT_END__
22341 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG ;
22342 #else
22343 typedef struct
22344 {
22345         /* SEARCH1_LKUP_TBL_REF */
22346         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22347
22348         /* SEARCH2_LKUP_TBL_REF */
22349         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22350
22351         /* SEARCH3_LKUP_TBL_REF */
22352         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22353
22354         /* SEARCH4_LKUP_TBL_REF */
22355         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22356
22357         /* QOS_EXTR_CFG */
22358         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22359
22360         /* DP_EXTR_CFG */
22361         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22362
22363         /* DROP_ON_MISS_EXTR_CFG */
22364         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22365
22366         /* rsv */
22367         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22368 }
22369 __PACKING_ATTRIBUTE_STRUCT_END__
22370 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG ;
22371 #endif
22372
22373 /*****************************************************************************************/
22374 /* IH_CLASS8_SEARCH_CFG                                                                  */
22375 /* Set of search parametrs for IH class8    These parameters used for search setting per */
22376 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
22377 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
22378 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
22379 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
22380 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
22381 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
22382 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
22383 /* n of them)                                                                            */
22384 /*****************************************************************************************/
22385
22386 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
22387 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
22388 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
22389 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
22390 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
22391 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
22392 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
22393 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
22394 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
22395 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
22396 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
22397 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
22398 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
22399 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
22400 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
22401 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
22402 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
22403 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22404 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22405 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22406 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22407 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22408 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22409 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22410 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22411 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22412 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22413 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22414 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22415 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22416 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22417 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22418 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22419 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22420 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22421 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22422 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22423 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22424 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22425 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22426 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22427 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22428 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22429 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22430 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22431 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22432 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22433 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22434 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22435 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22436 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22437 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22438 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22439 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22440 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22441 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22442 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22443 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22444 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22445 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22446 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22447 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22448 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22449 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22450 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22451 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22452 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22453 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22454 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22455 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22456 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22457 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22458 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22459 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22460 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22461 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22462 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22463 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22464 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22465 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22466 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22467 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22468 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22469 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22470 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22471
22472
22473 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_OFFSET ( 0x00000218 )
22474
22475 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_OFFSET )
22476 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_ADDRESS ), (r) )
22477 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG_ADDRESS ), (v) )
22478
22479 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
22480 typedef struct
22481 {
22482         /* rsv */
22483         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22484
22485         /* DROP_ON_MISS_EXTR_CFG */
22486         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22487
22488         /* DP_EXTR_CFG */
22489         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22490
22491         /* QOS_EXTR_CFG */
22492         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22493
22494         /* SEARCH4_LKUP_TBL_REF */
22495         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22496
22497         /* SEARCH3_LKUP_TBL_REF */
22498         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22499
22500         /* SEARCH2_LKUP_TBL_REF */
22501         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22502
22503         /* SEARCH1_LKUP_TBL_REF */
22504         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22505 }
22506 __PACKING_ATTRIBUTE_STRUCT_END__
22507 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG ;
22508 #else
22509 typedef struct
22510 {
22511         /* SEARCH1_LKUP_TBL_REF */
22512         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22513
22514         /* SEARCH2_LKUP_TBL_REF */
22515         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22516
22517         /* SEARCH3_LKUP_TBL_REF */
22518         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22519
22520         /* SEARCH4_LKUP_TBL_REF */
22521         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22522
22523         /* QOS_EXTR_CFG */
22524         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22525
22526         /* DP_EXTR_CFG */
22527         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22528
22529         /* DROP_ON_MISS_EXTR_CFG */
22530         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22531
22532         /* rsv */
22533         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22534 }
22535 __PACKING_ATTRIBUTE_STRUCT_END__
22536 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG ;
22537 #endif
22538
22539 /*****************************************************************************************/
22540 /* IH_CLASS9_SEARCH_CFG                                                                  */
22541 /* Set of search parametrs for IH class9    These parameters used for search setting per */
22542 /*  current IH class, used also as characterization of this ingres traffic.    The set o */
22543 /* f search parametrs include:    o     Detailed assignment of 4 LUT tables for up to 4 sear */
22544 /* ches (for SA search we can define dummy table that corresponds to same MAC table as f */
22545 /* or DA search, but with different key settings)    QoS extraction info:   - extract fr */
22546 /* om search 1 or from search 3 (one hot or none of them)    Destination port extraction */
22547 /*  info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop on */
22548 /*  miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or no */
22549 /* n of them)                                                                            */
22550 /*****************************************************************************************/
22551
22552 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
22553 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
22554 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
22555 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
22556 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
22557 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
22558 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
22559 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
22560 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
22561 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
22562 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
22563 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
22564 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
22565 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
22566 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
22567 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
22568 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
22569 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22570 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22571 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22572 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22573 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22574 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22575 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22576 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22577 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22578 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22579 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22580 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22581 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22582 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22583 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22584 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22585 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22586 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22587 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22588 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22589 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22590 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22591 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22592 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22593 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22594 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22595 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22596 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22597 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22598 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22599 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22600 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22601 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22602 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22603 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22604 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22605 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22606 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22607 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22608 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22609 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22610 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22611 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22612 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22613 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22614 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22615 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22616 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22617 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22618 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22619 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22620 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22621 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22622 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22623 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22624 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22625 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22626 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22627 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22628 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22629 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22630 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22631 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22632 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22633 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22634 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22635 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22636 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22637
22638
22639 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_OFFSET ( 0x0000021C )
22640
22641 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_OFFSET )
22642 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_ADDRESS ), (r) )
22643 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG_ADDRESS ), (v) )
22644
22645 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
22646 typedef struct
22647 {
22648         /* rsv */
22649         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22650
22651         /* DROP_ON_MISS_EXTR_CFG */
22652         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22653
22654         /* DP_EXTR_CFG */
22655         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22656
22657         /* QOS_EXTR_CFG */
22658         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22659
22660         /* SEARCH4_LKUP_TBL_REF */
22661         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22662
22663         /* SEARCH3_LKUP_TBL_REF */
22664         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22665
22666         /* SEARCH2_LKUP_TBL_REF */
22667         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22668
22669         /* SEARCH1_LKUP_TBL_REF */
22670         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22671 }
22672 __PACKING_ATTRIBUTE_STRUCT_END__
22673 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG ;
22674 #else
22675 typedef struct
22676 {
22677         /* SEARCH1_LKUP_TBL_REF */
22678         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22679
22680         /* SEARCH2_LKUP_TBL_REF */
22681         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22682
22683         /* SEARCH3_LKUP_TBL_REF */
22684         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22685
22686         /* SEARCH4_LKUP_TBL_REF */
22687         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22688
22689         /* QOS_EXTR_CFG */
22690         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22691
22692         /* DP_EXTR_CFG */
22693         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22694
22695         /* DROP_ON_MISS_EXTR_CFG */
22696         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22697
22698         /* rsv */
22699         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22700 }
22701 __PACKING_ATTRIBUTE_STRUCT_END__
22702 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG ;
22703 #endif
22704
22705 /*****************************************************************************************/
22706 /* IH_CLASS10_SEARCH_CFG                                                                 */
22707 /* Set of search parametrs for IH class10    These parameters used for search setting pe */
22708 /* r current IH class, used also as characterization of this ingres traffic.    The set  */
22709 /* of search parametrs include:    o    Detailed assignment of 4 LUT tables for up to 4 sea */
22710 /* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
22711 /* for DA search, but with different key settings)    QoS extraction info:   - extract f */
22712 /* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
22713 /* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
22714 /* n miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or n */
22715 /* on of them)                                                                           */
22716 /*****************************************************************************************/
22717
22718 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
22719 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
22720 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
22721 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
22722 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
22723 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
22724 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
22725 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
22726 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
22727 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
22728 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
22729 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
22730 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
22731 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
22732 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
22733 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
22734 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
22735 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22736 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22737 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22738 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22739 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22740 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22741 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22742 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22743 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22744 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22745 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22746 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22747 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22748 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22749 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22750 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22751 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22752 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22753 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22754 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22755 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22756 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22757 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22758 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22759 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22760 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22761 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22762 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22763 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22764 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22765 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22766 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22767 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22768 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22769 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22770 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22771 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22772 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22773 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22774 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22775 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22776 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22777 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22778 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22779 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22780 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22781 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22782 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22783 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22784 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22785 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22786 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22787 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22788 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22789 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22790 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22791 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22792 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22793 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22794 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22795 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22796 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22797 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22798 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22799 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22800 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22801 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22802 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22803
22804
22805 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_OFFSET ( 0x00000220 )
22806
22807 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_OFFSET )
22808 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_ADDRESS ), (r) )
22809 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG_ADDRESS ), (v) )
22810
22811 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
22812 typedef struct
22813 {
22814         /* rsv */
22815         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22816
22817         /* DROP_ON_MISS_EXTR_CFG */
22818         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22819
22820         /* DP_EXTR_CFG */
22821         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22822
22823         /* QOS_EXTR_CFG */
22824         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22825
22826         /* SEARCH4_LKUP_TBL_REF */
22827         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22828
22829         /* SEARCH3_LKUP_TBL_REF */
22830         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22831
22832         /* SEARCH2_LKUP_TBL_REF */
22833         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22834
22835         /* SEARCH1_LKUP_TBL_REF */
22836         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22837 }
22838 __PACKING_ATTRIBUTE_STRUCT_END__
22839 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG ;
22840 #else
22841 typedef struct
22842 {
22843         /* SEARCH1_LKUP_TBL_REF */
22844         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22845
22846         /* SEARCH2_LKUP_TBL_REF */
22847         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22848
22849         /* SEARCH3_LKUP_TBL_REF */
22850         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22851
22852         /* SEARCH4_LKUP_TBL_REF */
22853         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22854
22855         /* QOS_EXTR_CFG */
22856         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22857
22858         /* DP_EXTR_CFG */
22859         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22860
22861         /* DROP_ON_MISS_EXTR_CFG */
22862         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22863
22864         /* rsv */
22865         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22866 }
22867 __PACKING_ATTRIBUTE_STRUCT_END__
22868 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG ;
22869 #endif
22870
22871 /*****************************************************************************************/
22872 /* IH_CLASS11_SEARCH_CFG                                                                 */
22873 /* Set of search parametrs for IH class11    These parameters used for search setting pe */
22874 /* r current IH class, used also as characterization of this ingres traffic.    The set  */
22875 /* of search parametrs include:    o    Detailed assignment of 4 LUT tables for up to 4 sea */
22876 /* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
22877 /* for DA search, but with different key settings)    QoS extraction info:   - extract f */
22878 /* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
22879 /* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
22880 /* n miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or n */
22881 /* on of them)                                                                           */
22882 /*****************************************************************************************/
22883
22884 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
22885 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
22886 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
22887 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
22888 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
22889 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
22890 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
22891 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
22892 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
22893 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
22894 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
22895 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
22896 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
22897 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
22898 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
22899 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
22900 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
22901 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22902 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22903 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22904 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22905 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22906 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22907 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22908 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22909 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22910 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22911 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22912 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22913 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22914 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22915 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22916 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22917 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22918 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22919 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22920 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22921 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22922 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22923 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22924 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22925 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22926 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22927 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22928 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22929 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22930 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22931 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22932 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22933 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22934 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22935 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22936 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22937 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22938 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22939 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22940 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22941 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22942 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22943 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22944 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22945 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22946 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22947 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22948 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22949 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22950 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22951 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22952 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
22953 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
22954 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
22955 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
22956 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
22957 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
22958 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
22959 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
22960 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
22961 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
22962 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
22963 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
22964 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
22965 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
22966 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
22967 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
22968 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
22969
22970
22971 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_OFFSET ( 0x00000224 )
22972
22973 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_OFFSET )
22974 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_ADDRESS ), (r) )
22975 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG_ADDRESS ), (v) )
22976
22977 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
22978 typedef struct
22979 {
22980         /* rsv */
22981         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22982
22983         /* DROP_ON_MISS_EXTR_CFG */
22984         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22985
22986         /* DP_EXTR_CFG */
22987         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22988
22989         /* QOS_EXTR_CFG */
22990         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22991
22992         /* SEARCH4_LKUP_TBL_REF */
22993         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22994
22995         /* SEARCH3_LKUP_TBL_REF */
22996         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
22997
22998         /* SEARCH2_LKUP_TBL_REF */
22999         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23000
23001         /* SEARCH1_LKUP_TBL_REF */
23002         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23003 }
23004 __PACKING_ATTRIBUTE_STRUCT_END__
23005 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG ;
23006 #else
23007 typedef struct
23008 {
23009         /* SEARCH1_LKUP_TBL_REF */
23010         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23011
23012         /* SEARCH2_LKUP_TBL_REF */
23013         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23014
23015         /* SEARCH3_LKUP_TBL_REF */
23016         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23017
23018         /* SEARCH4_LKUP_TBL_REF */
23019         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23020
23021         /* QOS_EXTR_CFG */
23022         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23023
23024         /* DP_EXTR_CFG */
23025         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23026
23027         /* DROP_ON_MISS_EXTR_CFG */
23028         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23029
23030         /* rsv */
23031         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23032 }
23033 __PACKING_ATTRIBUTE_STRUCT_END__
23034 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG ;
23035 #endif
23036
23037 /*****************************************************************************************/
23038 /* IH_CLASS12_SEARCH_CFG                                                                 */
23039 /* Set of search parametrs for IH class12    These parameters used for search setting pe */
23040 /* r current IH class, used also as characterization of this ingres traffic.    The set  */
23041 /* of search parametrs include:    o    Detailed assignment of 4 LUT tables for up to 4 sea */
23042 /* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
23043 /* for DA search, but with different key settings)    QoS extraction info:   - extract f */
23044 /* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
23045 /* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
23046 /* n miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or n */
23047 /* on of them)                                                                           */
23048 /*****************************************************************************************/
23049
23050 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
23051 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
23052 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
23053 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
23054 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
23055 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
23056 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
23057 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
23058 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
23059 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
23060 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
23061 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
23062 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
23063 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
23064 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
23065 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
23066 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
23067 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23068 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23069 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23070 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23071 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23072 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23073 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23074 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23075 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23076 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23077 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23078 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23079 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23080 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23081 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23082 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23083 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23084 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23085 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23086 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23087 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23088 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23089 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23090 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23091 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23092 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23093 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23094 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23095 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23096 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23097 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23098 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23099 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23100 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23101 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23102 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23103 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23104 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23105 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23106 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23107 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23108 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23109 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23110 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23111 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23112 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23113 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23114 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23115 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23116 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23117 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23118 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23119 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23120 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23121 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23122 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23123 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23124 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23125 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23126 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23127 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23128 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23129 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23130 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23131 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23132 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23133 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23134 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23135
23136
23137 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_OFFSET ( 0x00000228 )
23138
23139 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_OFFSET )
23140 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_ADDRESS ), (r) )
23141 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG_ADDRESS ), (v) )
23142
23143 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
23144 typedef struct
23145 {
23146         /* rsv */
23147         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23148
23149         /* DROP_ON_MISS_EXTR_CFG */
23150         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23151
23152         /* DP_EXTR_CFG */
23153         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23154
23155         /* QOS_EXTR_CFG */
23156         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23157
23158         /* SEARCH4_LKUP_TBL_REF */
23159         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23160
23161         /* SEARCH3_LKUP_TBL_REF */
23162         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23163
23164         /* SEARCH2_LKUP_TBL_REF */
23165         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23166
23167         /* SEARCH1_LKUP_TBL_REF */
23168         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23169 }
23170 __PACKING_ATTRIBUTE_STRUCT_END__
23171 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG ;
23172 #else
23173 typedef struct
23174 {
23175         /* SEARCH1_LKUP_TBL_REF */
23176         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23177
23178         /* SEARCH2_LKUP_TBL_REF */
23179         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23180
23181         /* SEARCH3_LKUP_TBL_REF */
23182         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23183
23184         /* SEARCH4_LKUP_TBL_REF */
23185         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23186
23187         /* QOS_EXTR_CFG */
23188         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23189
23190         /* DP_EXTR_CFG */
23191         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23192
23193         /* DROP_ON_MISS_EXTR_CFG */
23194         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23195
23196         /* rsv */
23197         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23198 }
23199 __PACKING_ATTRIBUTE_STRUCT_END__
23200 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG ;
23201 #endif
23202
23203 /*****************************************************************************************/
23204 /* IH_CLASS13_SEARCH_CFG                                                                 */
23205 /* Set of search parametrs for IH class13    These parameters used for search setting pe */
23206 /* r current IH class, used also as characterization of this ingres traffic.    The set  */
23207 /* of search parametrs include:    o    Detailed assignment of 4 LUT tables for up to 4 sea */
23208 /* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
23209 /* for DA search, but with different key settings)    QoS extraction info:   - extract f */
23210 /* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
23211 /* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
23212 /* n miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or n */
23213 /* on of them)                                                                           */
23214 /*****************************************************************************************/
23215
23216 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
23217 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
23218 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
23219 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
23220 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
23221 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
23222 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
23223 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
23224 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
23225 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
23226 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
23227 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
23228 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
23229 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
23230 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
23231 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
23232 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
23233 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23234 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23235 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23236 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23237 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23238 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23239 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23240 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23241 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23242 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23243 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23244 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23245 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23246 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23247 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23248 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23249 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23250 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23251 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23252 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23253 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23254 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23255 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23256 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23257 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23258 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23259 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23260 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23261 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23262 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23263 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23264 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23265 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23266 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23267 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23268 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23269 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23270 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23271 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23272 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23273 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23274 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23275 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23276 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23277 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23278 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23279 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23280 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23281 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23282 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23283 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23284 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23285 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23286 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23287 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23288 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23289 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23290 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23291 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23292 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23293 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23294 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23295 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23296 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23297 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23298 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23299 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23300 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23301
23302
23303 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_OFFSET ( 0x0000022C )
23304
23305 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_OFFSET )
23306 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_ADDRESS ), (r) )
23307 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG_ADDRESS ), (v) )
23308
23309 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
23310 typedef struct
23311 {
23312         /* rsv */
23313         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23314
23315         /* DROP_ON_MISS_EXTR_CFG */
23316         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23317
23318         /* DP_EXTR_CFG */
23319         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23320
23321         /* QOS_EXTR_CFG */
23322         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23323
23324         /* SEARCH4_LKUP_TBL_REF */
23325         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23326
23327         /* SEARCH3_LKUP_TBL_REF */
23328         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23329
23330         /* SEARCH2_LKUP_TBL_REF */
23331         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23332
23333         /* SEARCH1_LKUP_TBL_REF */
23334         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23335 }
23336 __PACKING_ATTRIBUTE_STRUCT_END__
23337 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG ;
23338 #else
23339 typedef struct
23340 {
23341         /* SEARCH1_LKUP_TBL_REF */
23342         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23343
23344         /* SEARCH2_LKUP_TBL_REF */
23345         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23346
23347         /* SEARCH3_LKUP_TBL_REF */
23348         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23349
23350         /* SEARCH4_LKUP_TBL_REF */
23351         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23352
23353         /* QOS_EXTR_CFG */
23354         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23355
23356         /* DP_EXTR_CFG */
23357         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23358
23359         /* DROP_ON_MISS_EXTR_CFG */
23360         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23361
23362         /* rsv */
23363         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23364 }
23365 __PACKING_ATTRIBUTE_STRUCT_END__
23366 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG ;
23367 #endif
23368
23369 /*****************************************************************************************/
23370 /* IH_CLASS14_SEARCH_CFG                                                                 */
23371 /* Set of search parametrs for IH class14    These parameters used for search setting pe */
23372 /* r current IH class, used also as characterization of this ingres traffic.    The set  */
23373 /* of search parametrs include:    o    Detailed assignment of 4 LUT tables for up to 4 sea */
23374 /* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
23375 /* for DA search, but with different key settings)    QoS extraction info:   - extract f */
23376 /* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
23377 /* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
23378 /* n miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or n */
23379 /* on of them)                                                                           */
23380 /*****************************************************************************************/
23381
23382 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
23383 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
23384 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
23385 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
23386 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
23387 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
23388 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
23389 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
23390 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
23391 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
23392 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
23393 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
23394 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
23395 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
23396 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
23397 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
23398 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
23399 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23400 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23401 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23402 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23403 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23404 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23405 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23406 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23407 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23408 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23409 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23410 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23411 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23412 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23413 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23414 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23415 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23416 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23417 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23418 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23419 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23420 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23421 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23422 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23423 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23424 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23425 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23426 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23427 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23428 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23429 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23430 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23431 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23432 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23433 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23434 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23435 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23436 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23437 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23438 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23439 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23440 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23441 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23442 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23443 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23444 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23445 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23446 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23447 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23448 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23449 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23450 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23451 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23452 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23453 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23454 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23455 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23456 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23457 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23458 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23459 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23460 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23461 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23462 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23463 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23464 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23465 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23466 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23467
23468
23469 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_OFFSET ( 0x00000230 )
23470
23471 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_OFFSET )
23472 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_ADDRESS ), (r) )
23473 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG_ADDRESS ), (v) )
23474
23475 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
23476 typedef struct
23477 {
23478         /* rsv */
23479         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23480
23481         /* DROP_ON_MISS_EXTR_CFG */
23482         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23483
23484         /* DP_EXTR_CFG */
23485         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23486
23487         /* QOS_EXTR_CFG */
23488         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23489
23490         /* SEARCH4_LKUP_TBL_REF */
23491         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23492
23493         /* SEARCH3_LKUP_TBL_REF */
23494         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23495
23496         /* SEARCH2_LKUP_TBL_REF */
23497         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23498
23499         /* SEARCH1_LKUP_TBL_REF */
23500         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23501 }
23502 __PACKING_ATTRIBUTE_STRUCT_END__
23503 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG ;
23504 #else
23505 typedef struct
23506 {
23507         /* SEARCH1_LKUP_TBL_REF */
23508         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23509
23510         /* SEARCH2_LKUP_TBL_REF */
23511         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23512
23513         /* SEARCH3_LKUP_TBL_REF */
23514         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23515
23516         /* SEARCH4_LKUP_TBL_REF */
23517         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23518
23519         /* QOS_EXTR_CFG */
23520         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23521
23522         /* DP_EXTR_CFG */
23523         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23524
23525         /* DROP_ON_MISS_EXTR_CFG */
23526         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23527
23528         /* rsv */
23529         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23530 }
23531 __PACKING_ATTRIBUTE_STRUCT_END__
23532 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG ;
23533 #endif
23534
23535 /*****************************************************************************************/
23536 /* IH_CLASS15_SEARCH_CFG                                                                 */
23537 /* Set of search parametrs for IH class15    These parameters used for search setting pe */
23538 /* r current IH class, used also as characterization of this ingres traffic.    The set  */
23539 /* of search parametrs include:    o    Detailed assignment of 4 LUT tables for up to 4 sea */
23540 /* rches (for SA search we can define dummy table that corresponds to same MAC table as  */
23541 /* for DA search, but with different key settings)    QoS extraction info:   - extract f */
23542 /* rom search 1 or from search 3 (one hot or none of them)    Destination port extractio */
23543 /* n info:   - extract from search 1 or from search 3 (one hot or non of them)    Drop o */
23544 /* n miss info:   - consider \93drop on miss\94 from search 1 or from search 3 (one hot or n */
23545 /* on of them)                                                                           */
23546 /*****************************************************************************************/
23547
23548 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_RSV_RSV_VALUE                                                    ( 0x0 )
23549 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_RSV_RSV_VALUE_RESET_VALUE                                        ( 0x0 )
23550 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE             ( 0x0 )
23551 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_NONE_DROP_ON_SEARCH_MISS_VALUE_RESET_VALUE ( 0x0 )
23552 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH1_MISS_VALUE                 ( 0x1 )
23553 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_DROP_ON_SEARCH3_MISS_VALUE                 ( 0x2 )
23554 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DROP_ON_MISS_EXTR_CFG_RESERVED_VALUE                             ( 0x3 )
23555 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE                                    ( 0x0 )
23556 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                        ( 0x0 )
23557 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH1_VALUE                                   ( 0x1 )
23558 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_FROM_SEARCH3_VALUE                                   ( 0x2 )
23559 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_DP_EXTR_CFG_RESERVED_VALUE                                       ( 0x3 )
23560 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE                                   ( 0x0 )
23561 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_NONE_SEARCH_VALUE_RESET_VALUE                       ( 0x0 )
23562 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH1_VALUE                                  ( 0x1 )
23563 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_FROM_SEARCH3_VALUE                                  ( 0x2 )
23564 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_QOS_EXTR_CFG_RESERVED_VALUE                                      ( 0x3 )
23565 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23566 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23567 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23568 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23569 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23570 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23571 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23572 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23573 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23574 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23575 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23576 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23577 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23578 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23579 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23580 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23581 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH4_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23582 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23583 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23584 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23585 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23586 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23587 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23588 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23589 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23590 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23591 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23592 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23593 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23594 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23595 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23596 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23597 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23598 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH3_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23599 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23600 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23601 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23602 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23603 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23604 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23605 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23606 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23607 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23608 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23609 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23610 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23611 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23612 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23613 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23614 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23615 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH2_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23616 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL0_VALUE                             ( 0x0 )
23617 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL1_VALUE                             ( 0x1 )
23618 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL2_VALUE                             ( 0x2 )
23619 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL3_VALUE                             ( 0x3 )
23620 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL4_VALUE                             ( 0x4 )
23621 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL5_VALUE                             ( 0x5 )
23622 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL6_VALUE                             ( 0x6 )
23623 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL7_VALUE                             ( 0x7 )
23624 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL8_VALUE                             ( 0x8 )
23625 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_LKUP_TBL9_VALUE                             ( 0x9 )
23626 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV1_VALUE                                  ( 0xA )
23627 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV2_VALUE                                  ( 0xB )
23628 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV3_VALUE                                  ( 0xC )
23629 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV4_VALUE                                  ( 0xD )
23630 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_RSV5_VALUE                                  ( 0xE )
23631 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE                       ( 0xF )
23632 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_SEARCH1_LKUP_TBL_REF_SEARCH_DISABLED_VALUE_RESET_VALUE           ( 0xF )
23633
23634
23635 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_OFFSET ( 0x00000234 )
23636
23637 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_OFFSET )
23638 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_ADDRESS ), (r) )
23639 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG_ADDRESS ), (v) )
23640
23641 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
23642 typedef struct
23643 {
23644         /* rsv */
23645         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23646
23647         /* DROP_ON_MISS_EXTR_CFG */
23648         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23649
23650         /* DP_EXTR_CFG */
23651         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23652
23653         /* QOS_EXTR_CFG */
23654         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23655
23656         /* SEARCH4_LKUP_TBL_REF */
23657         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23658
23659         /* SEARCH3_LKUP_TBL_REF */
23660         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23661
23662         /* SEARCH2_LKUP_TBL_REF */
23663         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23664
23665         /* SEARCH1_LKUP_TBL_REF */
23666         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23667 }
23668 __PACKING_ATTRIBUTE_STRUCT_END__
23669 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG ;
23670 #else
23671 typedef struct
23672 {
23673         /* SEARCH1_LKUP_TBL_REF */
23674         uint32_t search1_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23675
23676         /* SEARCH2_LKUP_TBL_REF */
23677         uint32_t search2_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23678
23679         /* SEARCH3_LKUP_TBL_REF */
23680         uint32_t search3_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23681
23682         /* SEARCH4_LKUP_TBL_REF */
23683         uint32_t search4_lkup_tbl_ref   : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23684
23685         /* QOS_EXTR_CFG */
23686         uint32_t qos_extr_cfg           : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23687
23688         /* DP_EXTR_CFG */
23689         uint32_t dp_extr_cfg            : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23690
23691         /* DROP_ON_MISS_EXTR_CFG */
23692         uint32_t drop_on_miss_extr_cfg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23693
23694         /* rsv */
23695         uint32_t rsv                    : 10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23696 }
23697 __PACKING_ATTRIBUTE_STRUCT_END__
23698 IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG ;
23699 #endif
23700
23701 /*****************************************************************************************/
23702 /* RNRA_CNGS_TRSH_CFG                                                                    */
23703 /* Congestion thresholds of Runner A    Includes:  - Load balaning congestion threshold  */
23704 /* (start load balanicng upon to enable bit)  - Load balancing hysteresis  - High priori */
23705 /* ty congestion threshold (drop low priority packets)  - Exclusive priority congestion  */
23706 /* threshold (drop low/high priority packets)    Note: should be according to max number */
23707 /*  of RBs                                                                               */
23708 /*****************************************************************************************/
23709
23710 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV4_RSV_VALUE                             ( 0x0 )
23711 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23712 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE             ( 0x1C )
23713 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x1C )
23714 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV3_RSV_VALUE                             ( 0x0 )
23715 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23716 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE             ( 0x16 )
23717 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x16 )
23718 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV2_RSV_VALUE                             ( 0x0 )
23719 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23720 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE                    ( 0x0 )
23721 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE_RESET_VALUE        ( 0x0 )
23722 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV1_RSV_VALUE                             ( 0x0 )
23723 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23724 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE                    ( 0x8 )
23725 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE_RESET_VALUE        ( 0x8 )
23726
23727
23728 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_OFFSET ( 0x00000238 )
23729
23730 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_OFFSET )
23731 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_ADDRESS ), (r) )
23732 #define IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG_ADDRESS ), (v) )
23733
23734 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
23735 typedef struct
23736 {
23737         /* RSV4 */
23738         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23739
23740         /* EXCL_CNGS_TRSH */
23741         uint32_t excl_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23742
23743         /* rsv3 */
23744         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23745
23746         /* HIGH_CNGS_TRSH */
23747         uint32_t high_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23748
23749         /* rsv2 */
23750         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23751
23752         /* LB_HYST */
23753         uint32_t lb_hyst        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23754
23755         /* rsv1 */
23756         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23757
23758         /* LB_THSH */
23759         uint32_t lb_thsh        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23760 }
23761 __PACKING_ATTRIBUTE_STRUCT_END__
23762 IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG ;
23763 #else
23764 typedef struct
23765 {
23766         /* LB_THSH */
23767         uint32_t lb_thsh        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23768
23769         /* rsv1 */
23770         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23771
23772         /* LB_HYST */
23773         uint32_t lb_hyst        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23774
23775         /* rsv2 */
23776         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23777
23778         /* HIGH_CNGS_TRSH */
23779         uint32_t high_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23780
23781         /* rsv3 */
23782         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23783
23784         /* EXCL_CNGS_TRSH */
23785         uint32_t excl_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23786
23787         /* RSV4 */
23788         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23789 }
23790 __PACKING_ATTRIBUTE_STRUCT_END__
23791 IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG ;
23792 #endif
23793
23794 /*****************************************************************************************/
23795 /* RNRB_CNGS_TRSH_CFG                                                                    */
23796 /* Congestion thresholds of Runner B    Includes:  - Load balaning congestion threshold  */
23797 /* (start load balanicng upon to enable bit)  - Load balancing hysteresis  - High priori */
23798 /* ty congestion threshold (drop low priority packets)  - Exclusive priority congestion  */
23799 /* threshold (drop low/high priority packets)    Note: should be according to max number */
23800 /*  of RBs                                                                               */
23801 /*****************************************************************************************/
23802
23803 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV4_RSV_VALUE                             ( 0x0 )
23804 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV4_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23805 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE             ( 0x1C )
23806 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_EXCL_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x1C )
23807 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV3_RSV_VALUE                             ( 0x0 )
23808 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV3_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23809 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE             ( 0x16 )
23810 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_HIGH_CNGS_TRSH_THRESHOLD_VALUE_RESET_VALUE ( 0x16 )
23811 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV2_RSV_VALUE                             ( 0x0 )
23812 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23813 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE                    ( 0x0 )
23814 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_HYST_THRESHOLD_VALUE_RESET_VALUE        ( 0x0 )
23815 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV1_RSV_VALUE                             ( 0x0 )
23816 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_RSV1_RSV_VALUE_RESET_VALUE                 ( 0x0 )
23817 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE                    ( 0x8 )
23818 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_LB_THSH_THRESHOLD_VALUE_RESET_VALUE        ( 0x8 )
23819
23820
23821 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_OFFSET ( 0x0000023C )
23822
23823 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_OFFSET )
23824 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_ADDRESS ), (r) )
23825 #define IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG_ADDRESS ), (v) )
23826
23827 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
23828 typedef struct
23829 {
23830         /* RSV4 */
23831         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23832
23833         /* EXCL_CNGS_TRSH */
23834         uint32_t excl_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23835
23836         /* rsv3 */
23837         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23838
23839         /* HIGH_CNGS_TRSH */
23840         uint32_t high_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23841
23842         /* rsv2 */
23843         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23844
23845         /* LB_HYST */
23846         uint32_t lb_hyst        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23847
23848         /* rsv1 */
23849         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23850
23851         /* LB_THSH */
23852         uint32_t lb_thsh        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23853 }
23854 __PACKING_ATTRIBUTE_STRUCT_END__
23855 IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG ;
23856 #else
23857 typedef struct
23858 {
23859         /* LB_THSH */
23860         uint32_t lb_thsh        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23861
23862         /* rsv1 */
23863         uint32_t rsv1           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23864
23865         /* LB_HYST */
23866         uint32_t lb_hyst        : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23867
23868         /* rsv2 */
23869         uint32_t rsv2           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23870
23871         /* HIGH_CNGS_TRSH */
23872         uint32_t high_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23873
23874         /* rsv3 */
23875         uint32_t rsv3           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23876
23877         /* EXCL_CNGS_TRSH */
23878         uint32_t excl_cngs_trsh : 7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23879
23880         /* RSV4 */
23881         uint32_t rsv4           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23882 }
23883 __PACKING_ATTRIBUTE_STRUCT_END__
23884 IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG ;
23885 #endif
23886
23887 /*****************************************************************************************/
23888 /* WAN_PER_PORT_CFG                                                                      */
23889 /* Each phyisical ingres port has its own configuration if it belongs to WAN or non-WAN  */
23890 /* traffic                                                                               */
23891 /*****************************************************************************************/
23892
23893 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RSV_RSV_VALUE                           ( 0x0 )
23894 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RSV_RSV_VALUE_RESET_VALUE               ( 0x0 )
23895 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE1_TRF_MAP_NON_WAN_VALUE             ( 0x0 )
23896 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE1_TRF_MAP_NON_WAN_VALUE_RESET_VALUE ( 0x0 )
23897 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE1_TRF_MAP_WAN_VALUE                 ( 0x1 )
23898 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE0_TRF_MAP_NON_WAN_VALUE             ( 0x0 )
23899 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE0_TRF_MAP_NON_WAN_VALUE_RESET_VALUE ( 0x0 )
23900 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_PCIE0_TRF_MAP_WAN_VALUE                 ( 0x1 )
23901 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRB_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23902 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRB_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
23903 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRB_TRF_MAP_WAN_VALUE                  ( 0x1 )
23904 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRA_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23905 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRA_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
23906 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_RNRA_TRF_MAP_WAN_VALUE                  ( 0x1 )
23907 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_GPON_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23908 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_GPON_TRF_MAP_WAN_VALUE                  ( 0x1 )
23909 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_GPON_TRF_MAP_WAN_VALUE_RESET_VALUE      ( 0x1 )
23910 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH4_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23911 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH4_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
23912 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH4_TRF_MAP_WAN_VALUE                  ( 0x1 )
23913 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH3_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23914 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH3_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
23915 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH3_TRF_MAP_WAN_VALUE                  ( 0x1 )
23916 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH2_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23917 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH2_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
23918 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH2_TRF_MAP_WAN_VALUE                  ( 0x1 )
23919 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH1_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23920 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH1_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
23921 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH1_TRF_MAP_WAN_VALUE                  ( 0x1 )
23922 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH0_TRF_MAP_NON_WAN_VALUE              ( 0x0 )
23923 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH0_TRF_MAP_NON_WAN_VALUE_RESET_VALUE  ( 0x0 )
23924 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ETH0_TRF_MAP_WAN_VALUE                  ( 0x1 )
23925
23926
23927 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_OFFSET ( 0x00000240 )
23928
23929 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_OFFSET )
23930 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ADDRESS ), (r) )
23931 #define IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG_ADDRESS ), (v) )
23932
23933 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
23934 typedef struct
23935 {
23936         /* RSV */
23937         uint32_t rsv            : 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23938
23939         /* PCIE1_TRF_MAP */
23940         uint32_t pcie1_trf_map  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23941
23942         /* PCIE0_TRF_MAP */
23943         uint32_t pcie0_trf_map  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23944
23945         /* RNRB_TRF_MAP */
23946         uint32_t rnrb_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23947
23948         /* RNRA_TRF_MAP */
23949         uint32_t rnra_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23950
23951         /* GPON_TRF_MAP */
23952         uint32_t gpon_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23953
23954         /* ETH4_TRF_MAP */
23955         uint32_t eth4_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23956
23957         /* ETH3_TRF_MAP */
23958         uint32_t eth3_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23959
23960         /* ETH2_TRF_MAP */
23961         uint32_t eth2_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23962
23963         /* ETH1_TRF_MAP */
23964         uint32_t eth1_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23965
23966         /* ETH0_TRF_MAP */
23967         uint32_t eth0_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23968 }
23969 __PACKING_ATTRIBUTE_STRUCT_END__
23970 IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG ;
23971 #else
23972 typedef struct
23973 {
23974         /* ETH0_TRF_MAP */
23975         uint32_t eth0_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23976
23977         /* ETH1_TRF_MAP */
23978         uint32_t eth1_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23979
23980         /* ETH2_TRF_MAP */
23981         uint32_t eth2_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23982
23983         /* ETH3_TRF_MAP */
23984         uint32_t eth3_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23985
23986         /* ETH4_TRF_MAP */
23987         uint32_t eth4_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23988
23989         /* GPON_TRF_MAP */
23990         uint32_t gpon_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23991
23992         /* RNRA_TRF_MAP */
23993         uint32_t rnra_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23994
23995         /* RNRB_TRF_MAP */
23996         uint32_t rnrb_trf_map   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
23997
23998         /* PCIE0_TRF_MAP */
23999         uint32_t pcie0_trf_map  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24000
24001         /* PCIE1_TRF_MAP */
24002         uint32_t pcie1_trf_map  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24003
24004         /* RSV */
24005         uint32_t rsv            : 22 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24006 }
24007 __PACKING_ATTRIBUTE_STRUCT_END__
24008 IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG ;
24009 #endif
24010
24011 /*****************************************************************************************/
24012 /* PARSE_LAYER_PER_PORT_CFG                                                              */
24013 /* Each phyisical ingres port has its own configuration related to Parsing Layer Depth   */
24014 /* Note: pcie0 and pcie1 are sharing same configuration                                  */
24015 /*****************************************************************************************/
24016
24017 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RSV_RSV_VALUE                                       ( 0x0 )
24018 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RSV_RSV_VALUE_RESET_VALUE                           ( 0x0 )
24019 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE1_PARSE_LAYER_STG_PARSE_LAYER_VALUE             ( 0x3 )
24020 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE1_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE ( 0x3 )
24021 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE0_PARSE_LAYER_STG_PARSE_LAYER_VALUE             ( 0x3 )
24022 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_PCIE0_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE ( 0x3 )
24023 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRB_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24024 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRB_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24025 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRA_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24026 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_RNRA_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24027 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_GPON_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24028 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_GPON_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24029 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH4_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24030 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH4_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24031 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH3_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24032 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH3_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24033 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH2_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24034 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH2_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24035 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH1_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24036 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH1_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24037 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH0_PARSE_LAYER_STG_PARSE_LAYER_VALUE              ( 0x3 )
24038 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ETH0_PARSE_LAYER_STG_PARSE_LAYER_VALUE_RESET_VALUE  ( 0x3 )
24039
24040
24041 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_OFFSET ( 0x00000244 )
24042
24043 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_OFFSET )
24044 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ADDRESS ), (r) )
24045 #define IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG_ADDRESS ), (v) )
24046
24047 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
24048 typedef struct
24049 {
24050         /* rsv */
24051         uint32_t rsv                    : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24052
24053         /* PCIE1_PARSE_LAYER_STG */
24054         uint32_t pcie1_parse_layer_stg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24055
24056         /* PCIE0_PARSE_LAYER_STG */
24057         uint32_t pcie0_parse_layer_stg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24058
24059         /* RNRB_PARSE_LAYER_STG */
24060         uint32_t rnrb_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24061
24062         /* RNRA_PARSE_LAYER_STG */
24063         uint32_t rnra_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24064
24065         /* GPON_PARSE_LAYER_STG */
24066         uint32_t gpon_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24067
24068         /* ETH4_PARSE_LAYER_STG */
24069         uint32_t eth4_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24070
24071         /* ETH3_PARSE_LAYER_STG */
24072         uint32_t eth3_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24073
24074         /* ETH2_PARSE_LAYER_STG */
24075         uint32_t eth2_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24076
24077         /* ETH1_PARSE_LAYER_STG */
24078         uint32_t eth1_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24079
24080         /* ETH0_PARSE_LAYER_STG */
24081         uint32_t eth0_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24082 }
24083 __PACKING_ATTRIBUTE_STRUCT_END__
24084 IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG ;
24085 #else
24086 typedef struct
24087 {
24088         /* ETH0_PARSE_LAYER_STG */
24089         uint32_t eth0_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24090
24091         /* ETH1_PARSE_LAYER_STG */
24092         uint32_t eth1_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24093
24094         /* ETH2_PARSE_LAYER_STG */
24095         uint32_t eth2_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24096
24097         /* ETH3_PARSE_LAYER_STG */
24098         uint32_t eth3_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24099
24100         /* ETH4_PARSE_LAYER_STG */
24101         uint32_t eth4_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24102
24103         /* GPON_PARSE_LAYER_STG */
24104         uint32_t gpon_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24105
24106         /* RNRA_PARSE_LAYER_STG */
24107         uint32_t rnra_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24108
24109         /* RNRB_PARSE_LAYER_STG */
24110         uint32_t rnrb_parse_layer_stg   : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24111
24112         /* PCIE0_PARSE_LAYER_STG */
24113         uint32_t pcie0_parse_layer_stg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24114
24115         /* PCIE1_PARSE_LAYER_STG */
24116         uint32_t pcie1_parse_layer_stg  : 2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24117
24118         /* rsv */
24119         uint32_t rsv                    : 12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24120 }
24121 __PACKING_ATTRIBUTE_STRUCT_END__
24122 IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG ;
24123 #endif
24124
24125 /*****************************************************************************************/
24126 /* PROP_SIZE_PER_PORT_CFG0                                                               */
24127 /* Each phyisical ingres port has its own configuration related to Propitiatory tag size */
24128 /* , valid option are 0, 4 ,6 or 8 bytes.  The option of 2 bytes is reserved for user, b */
24129 /* ut supported by HW. This option should be masked by driver API.  This register is rel */
24130 /* ated to following source ports (source port is taken from Packet Header Descriptor):  */
24131 /*  - Eth0-4  - GPON (or Eth5)  - Runner A/B                                             */
24132 /*****************************************************************************************/
24133
24134 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24135 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24136 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24137 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24138 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24139 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24140 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24141 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24142 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24143 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24144 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24145 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24146 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24147 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24148 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24149 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24150 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRB_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24151 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24152 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24153 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24154 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24155 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24156 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24157 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24158 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24159 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24160 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24161 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24162 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24163 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24164 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24165 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24166 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24167 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_RNRA_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24168 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24169 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24170 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24171 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24172 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24173 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24174 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24175 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24176 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24177 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24178 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24179 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24180 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24181 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24182 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24183 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24184 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_GPON_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24185 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24186 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24187 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24188 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24189 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24190 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24191 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24192 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24193 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24194 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24195 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24196 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24197 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24198 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24199 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24200 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24201 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH4_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24202 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24203 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24204 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24205 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24206 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24207 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24208 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24209 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24210 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24211 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24212 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24213 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24214 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24215 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24216 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24217 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24218 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH3_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24219 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24220 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24221 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24222 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24223 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24224 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24225 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24226 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24227 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24228 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24229 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24230 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24231 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24232 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24233 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24234 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24235 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH2_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24236 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24237 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24238 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24239 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24240 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24241 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24242 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24243 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24244 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24245 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24246 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24247 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24248 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24249 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24250 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24251 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24252 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH1_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24253 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24254 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24255 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24256 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24257 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24258 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24259 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24260 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24261 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24262 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24263 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24264 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24265 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24266 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24267 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24268 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24269 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ETH0_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24270
24271
24272 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_OFFSET ( 0x00000248 )
24273
24274 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_OFFSET )
24275 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ADDRESS ), (r) )
24276 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0_ADDRESS ), (v) )
24277
24278 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
24279 typedef struct
24280 {
24281         /* RNRB_PROP_TAG_SIZE */
24282         uint32_t rnrb_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24283
24284         /* RNRA_PROP_TAG_SIZE */
24285         uint32_t rnra_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24286
24287         /* GPON_PROP_TAG_SIZE */
24288         uint32_t gpon_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24289
24290         /* ETH4_PROP_TAG_SIZE */
24291         uint32_t eth4_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24292
24293         /* ETH3_PROP_TAG_SIZE */
24294         uint32_t eth3_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24295
24296         /* ETH2_PROP_TAG_SIZE */
24297         uint32_t eth2_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24298
24299         /* ETH1_PROP_TAG_SIZE */
24300         uint32_t eth1_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24301
24302         /* ETH0_PROP_TAG_SIZE */
24303         uint32_t eth0_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24304 }
24305 __PACKING_ATTRIBUTE_STRUCT_END__
24306 IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0 ;
24307 #else
24308 typedef struct
24309 {
24310         /* ETH0_PROP_TAG_SIZE */
24311         uint32_t eth0_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24312
24313         /* ETH1_PROP_TAG_SIZE */
24314         uint32_t eth1_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24315
24316         /* ETH2_PROP_TAG_SIZE */
24317         uint32_t eth2_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24318
24319         /* ETH3_PROP_TAG_SIZE */
24320         uint32_t eth3_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24321
24322         /* ETH4_PROP_TAG_SIZE */
24323         uint32_t eth4_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24324
24325         /* GPON_PROP_TAG_SIZE */
24326         uint32_t gpon_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24327
24328         /* RNRA_PROP_TAG_SIZE */
24329         uint32_t rnra_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24330
24331         /* RNRB_PROP_TAG_SIZE */
24332         uint32_t rnrb_prop_tag_size     : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24333 }
24334 __PACKING_ATTRIBUTE_STRUCT_END__
24335 IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0 ;
24336 #endif
24337
24338 /*****************************************************************************************/
24339 /* PROP_SIZE_PER_PORT_CFG1                                                               */
24340 /* Each phyisical ingres port has its own configuration related to Propitiatory tag size */
24341 /* , valid option are 0, 4 ,6 or 8 bytes.  The option of 2 bytes is reserved for user, b */
24342 /* ut supported by HW. This option should be masked by driver API.  This register is rel */
24343 /* ated to following source ports (source port is taken from Packet Header Descriptor):  */
24344 /*  - Pcie0  - Pcie1                                                                     */
24345 /*****************************************************************************************/
24346
24347 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_RSV_RSV_VALUE                                    ( 0x0 )
24348 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
24349 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24350 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24351 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24352 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24353 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24354 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24355 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24356 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24357 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24358 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24359 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24360 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24361 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24362 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24363 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24364 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24365 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE1_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24366 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE             ( 0x0 )
24367 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_0_VALUE_RESET_VALUE ( 0x0 )
24368 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV1_VALUE                   ( 0x1 )
24369 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RESERVED_TAG_SIZE_2_VALUE    ( 0x2 )
24370 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV3_VALUE                   ( 0x3 )
24371 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_4_VALUE             ( 0x4 )
24372 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV5_VALUE                   ( 0x5 )
24373 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_6_VALUE             ( 0x6 )
24374 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV7_VALUE                   ( 0x7 )
24375 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_TAG_SIZE_8_VALUE             ( 0x8 )
24376 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV9_VALUE                   ( 0x9 )
24377 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV10_VALUE                  ( 0xA )
24378 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV11_VALUE                  ( 0xB )
24379 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV12_VALUE                  ( 0xC )
24380 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV13_VALUE                  ( 0xD )
24381 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV14_VALUE                  ( 0xE )
24382 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_PCIE0_PROP_TAG_SIZE_RSV15_VALUE                  ( 0xF )
24383
24384
24385 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_OFFSET ( 0x0000024C )
24386
24387 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_OFFSET )
24388 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_ADDRESS ), (r) )
24389 #define IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1_ADDRESS ), (v) )
24390
24391 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
24392 typedef struct
24393 {
24394         /* rsv */
24395         uint32_t rsv                    : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24396
24397         /* PCIE1_PROP_TAG_SIZE */
24398         uint32_t pcie1_prop_tag_size    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24399
24400         /* PCIE0_PROP_TAG_SIZE */
24401         uint32_t pcie0_prop_tag_size    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24402 }
24403 __PACKING_ATTRIBUTE_STRUCT_END__
24404 IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1 ;
24405 #else
24406 typedef struct
24407 {
24408         /* PCIE0_PROP_TAG_SIZE */
24409         uint32_t pcie0_prop_tag_size    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24410
24411         /* PCIE1_PROP_TAG_SIZE */
24412         uint32_t pcie1_prop_tag_size    : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24413
24414         /* rsv */
24415         uint32_t rsv                    : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24416 }
24417 __PACKING_ATTRIBUTE_STRUCT_END__
24418 IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1 ;
24419 #endif
24420
24421 /*****************************************************************************************/
24422 /* IH_CLSF_MAPL_CFG                                                                      */
24423 /* There are 16 Classifier sets (keys+mask) that in case of match performs mapping of ma */
24424 /* tched set to IH class. The register includes Class ID for lowest sets [0...7]         */
24425 /*****************************************************************************************/
24426
24427 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET7_MAP_CLASS_ID_VALUE             ( 0x7 )
24428 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET7_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x7 )
24429 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET6_MAP_CLASS_ID_VALUE             ( 0x6 )
24430 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET6_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x6 )
24431 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET5_MAP_CLASS_ID_VALUE             ( 0x5 )
24432 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET5_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x5 )
24433 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET4_MAP_CLASS_ID_VALUE             ( 0x4 )
24434 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET4_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x4 )
24435 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET3_MAP_CLASS_ID_VALUE             ( 0x3 )
24436 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET3_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x3 )
24437 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET2_MAP_CLASS_ID_VALUE             ( 0x2 )
24438 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET2_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x2 )
24439 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET1_MAP_CLASS_ID_VALUE             ( 0x1 )
24440 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET1_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x1 )
24441 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET0_MAP_CLASS_ID_VALUE             ( 0x0 )
24442 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_CLSF_SET0_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0x0 )
24443
24444
24445 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_OFFSET ( 0x00000250 )
24446
24447 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_OFFSET )
24448 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_ADDRESS ), (r) )
24449 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG_ADDRESS ), (v) )
24450
24451 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
24452 typedef struct
24453 {
24454         /* CLSF_SET7_MAP */
24455         uint32_t clsf_set7_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24456
24457         /* CLSF_SET6_MAP */
24458         uint32_t clsf_set6_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24459
24460         /* CLSF_SET5_MAP */
24461         uint32_t clsf_set5_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24462
24463         /* CLSF_SET4_MAP */
24464         uint32_t clsf_set4_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24465
24466         /* CLSF_SET3_MAP */
24467         uint32_t clsf_set3_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24468
24469         /* CLSF_SET2_MAP */
24470         uint32_t clsf_set2_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24471
24472         /* CLSF_SET1_MAP */
24473         uint32_t clsf_set1_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24474
24475         /* CLSF_SET0_MAP */
24476         uint32_t clsf_set0_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24477 }
24478 __PACKING_ATTRIBUTE_STRUCT_END__
24479 IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG ;
24480 #else
24481 typedef struct
24482 {
24483         /* CLSF_SET0_MAP */
24484         uint32_t clsf_set0_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24485
24486         /* CLSF_SET1_MAP */
24487         uint32_t clsf_set1_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24488
24489         /* CLSF_SET2_MAP */
24490         uint32_t clsf_set2_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24491
24492         /* CLSF_SET3_MAP */
24493         uint32_t clsf_set3_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24494
24495         /* CLSF_SET4_MAP */
24496         uint32_t clsf_set4_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24497
24498         /* CLSF_SET5_MAP */
24499         uint32_t clsf_set5_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24500
24501         /* CLSF_SET6_MAP */
24502         uint32_t clsf_set6_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24503
24504         /* CLSF_SET7_MAP */
24505         uint32_t clsf_set7_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24506 }
24507 __PACKING_ATTRIBUTE_STRUCT_END__
24508 IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG ;
24509 #endif
24510
24511 /*****************************************************************************************/
24512 /* IH_CLSF_MAPH_CFG                                                                      */
24513 /* There are 16 Classifier sets (keys+mask) that in case of match performs mapping of ma */
24514 /* tched set to IH class. The register includes Class ID for highest sets [8...15]       */
24515 /*****************************************************************************************/
24516
24517 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET15_MAP_CLASS_ID_VALUE             ( 0xF )
24518 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET15_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xF )
24519 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET14_MAP_CLASS_ID_VALUE             ( 0xE )
24520 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET14_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xE )
24521 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET13_MAP_CLASS_ID_VALUE             ( 0xD )
24522 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET13_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xD )
24523 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET12_MAP_CLASS_ID_VALUE             ( 0xC )
24524 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET12_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xC )
24525 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET11_MAP_CLASS_ID_VALUE             ( 0xB )
24526 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET11_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xB )
24527 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET10_MAP_CLASS_ID_VALUE             ( 0xA )
24528 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET10_MAP_CLASS_ID_VALUE_RESET_VALUE ( 0xA )
24529 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET9_MAP_CLASS_ID_VALUE              ( 0x9 )
24530 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET9_MAP_CLASS_ID_VALUE_RESET_VALUE  ( 0x9 )
24531 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET8_MAP_CLASS_ID_VALUE              ( 0x8 )
24532 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_CLSF_SET8_MAP_CLASS_ID_VALUE_RESET_VALUE  ( 0x8 )
24533
24534
24535 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_OFFSET ( 0x00000254 )
24536
24537 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_OFFSET )
24538 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_ADDRESS ), (r) )
24539 #define IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG_ADDRESS ), (v) )
24540
24541 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
24542 typedef struct
24543 {
24544         /* CLSF_SET15_MAP */
24545         uint32_t clsf_set15_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24546
24547         /* CLSF_SET14_MAP */
24548         uint32_t clsf_set14_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24549
24550         /* CLSF_SET13_MAP */
24551         uint32_t clsf_set13_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24552
24553         /* CLSF_SET12_MAP */
24554         uint32_t clsf_set12_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24555
24556         /* CLSF_SET11_MAP */
24557         uint32_t clsf_set11_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24558
24559         /* CLSF_SET10_MAP */
24560         uint32_t clsf_set10_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24561
24562         /* CLSF_SET9_MAP */
24563         uint32_t clsf_set9_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24564
24565         /* CLSF_SET8_MAP */
24566         uint32_t clsf_set8_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24567 }
24568 __PACKING_ATTRIBUTE_STRUCT_END__
24569 IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG ;
24570 #else
24571 typedef struct
24572 {
24573         /* CLSF_SET8_MAP */
24574         uint32_t clsf_set8_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24575
24576         /* CLSF_SET9_MAP */
24577         uint32_t clsf_set9_map  : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24578
24579         /* CLSF_SET10_MAP */
24580         uint32_t clsf_set10_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24581
24582         /* CLSF_SET11_MAP */
24583         uint32_t clsf_set11_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24584
24585         /* CLSF_SET12_MAP */
24586         uint32_t clsf_set12_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24587
24588         /* CLSF_SET13_MAP */
24589         uint32_t clsf_set13_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24590
24591         /* CLSF_SET14_MAP */
24592         uint32_t clsf_set14_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24593
24594         /* CLSF_SET15_MAP */
24595         uint32_t clsf_set15_map : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24596 }
24597 __PACKING_ATTRIBUTE_STRUCT_END__
24598 IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG ;
24599 #endif
24600
24601 /*****************************************************************************************/
24602 /* TRGT_MTRX_PCIE0_SP_CFG                                                                */
24603 /* Target matrix configuration for Source Port PCIE0    Used for decision on Target memo */
24604 /* ry and Local switch as function of extracted destination port that can be as followin */
24605 /* g:  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CP */
24606 /* U  - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local sw */
24607 /* itch info)  -Spare                                                                    */
24608 /*****************************************************************************************/
24609
24610 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
24611 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
24612 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
24613 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
24614 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
24615 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
24616 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
24617 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
24618 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
24619 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24620 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
24621 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
24622 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
24623 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
24624 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
24625 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
24626 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
24627 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
24628 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
24629 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
24630 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
24631 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
24632 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
24633 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
24634 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24635 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
24636 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
24637 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24638 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
24639 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
24640 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24641 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
24642 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
24643 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24644 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
24645 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
24646 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24647 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
24648 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
24649 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24650 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
24651 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
24652 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
24653 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
24654 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
24655 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
24656 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
24657 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
24658 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
24659 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
24660 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
24661 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
24662 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
24663 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
24664 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
24665 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
24666 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
24667 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
24668 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24669 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24670 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24671 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24672 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24673 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24674 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24675 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24676 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24677 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24678 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24679 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24680 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24681 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24682 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24683 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24684 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24685 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24686
24687
24688 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_OFFSET ( 0x00000258 )
24689
24690 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_OFFSET )
24691 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_ADDRESS ), (r) )
24692 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG_ADDRESS ), (v) )
24693
24694 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
24695 typedef struct
24696 {
24697         /* RSV2 */
24698         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24699
24700         /* DP_SPARE_LS_CFG */
24701         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24702
24703         /* DP_PCIE1_LS_CFG */
24704         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24705
24706         /* DP_SRAM_LS_CFG */
24707         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24708
24709         /* DP_DDR_LS_CFG */
24710         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24711
24712         /* DP_MC_LS_CFG */
24713         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24714
24715         /* DP_CPU_LS_CFG */
24716         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24717
24718         /* DP_PCIE0_LS_CFG */
24719         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24720
24721         /* DP_GPON_LS_CFG */
24722         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24723
24724         /* DP_ETH4_LS_CFG */
24725         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24726
24727         /* DP_ETH3_LS_CFG */
24728         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24729
24730         /* DP_ETH2_LS_CFG */
24731         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24732
24733         /* DP_ETH1_LS_CFG */
24734         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24735
24736         /* DP_ETH0_LS_CFG */
24737         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24738
24739         /* rsv1 */
24740         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24741
24742         /* DP_SPARE_TM_CFG */
24743         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24744
24745         /* DP_PCIE1_TM_CFG */
24746         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24747
24748         /* DP_MC_TM_CFG */
24749         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24750
24751         /* DP_CPU_TM_CFG */
24752         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24753
24754         /* DP_PCIE0_TM_CFG */
24755         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24756
24757         /* DP_GPON_TM_CFG */
24758         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24759
24760         /* DP_ETH4_TM_CFG */
24761         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24762
24763         /* DP_ETH3_TM_CFG */
24764         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24765
24766         /* DP_ETH2_TM_CFG */
24767         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24768
24769         /* DP_ETH1_TM_CFG */
24770         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24771
24772         /* DP_ETH0_TM_CFG */
24773         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24774 }
24775 __PACKING_ATTRIBUTE_STRUCT_END__
24776 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG ;
24777 #else
24778 typedef struct
24779 {
24780         /* DP_ETH0_TM_CFG */
24781         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24782
24783         /* DP_ETH1_TM_CFG */
24784         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24785
24786         /* DP_ETH2_TM_CFG */
24787         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24788
24789         /* DP_ETH3_TM_CFG */
24790         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24791
24792         /* DP_ETH4_TM_CFG */
24793         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24794
24795         /* DP_GPON_TM_CFG */
24796         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24797
24798         /* DP_PCIE0_TM_CFG */
24799         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24800
24801         /* DP_CPU_TM_CFG */
24802         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24803
24804         /* DP_MC_TM_CFG */
24805         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24806
24807         /* DP_PCIE1_TM_CFG */
24808         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24809
24810         /* DP_SPARE_TM_CFG */
24811         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24812
24813         /* rsv1 */
24814         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24815
24816         /* DP_ETH0_LS_CFG */
24817         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24818
24819         /* DP_ETH1_LS_CFG */
24820         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24821
24822         /* DP_ETH2_LS_CFG */
24823         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24824
24825         /* DP_ETH3_LS_CFG */
24826         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24827
24828         /* DP_ETH4_LS_CFG */
24829         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24830
24831         /* DP_GPON_LS_CFG */
24832         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24833
24834         /* DP_PCIE0_LS_CFG */
24835         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24836
24837         /* DP_CPU_LS_CFG */
24838         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24839
24840         /* DP_MC_LS_CFG */
24841         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24842
24843         /* DP_DDR_LS_CFG */
24844         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24845
24846         /* DP_SRAM_LS_CFG */
24847         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24848
24849         /* DP_PCIE1_LS_CFG */
24850         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24851
24852         /* DP_SPARE_LS_CFG */
24853         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24854
24855         /* RSV2 */
24856         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24857 }
24858 __PACKING_ATTRIBUTE_STRUCT_END__
24859 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG ;
24860 #endif
24861
24862 /*****************************************************************************************/
24863 /* TRGT_MTRX_PCIE1_SP_CFG                                                                */
24864 /* Target matrix configuration for Source Port PCIE0    Used for decision on Target memo */
24865 /* ry and Local switch as function of extracted destination port that can be as followin */
24866 /* g:  - Eth0  - Eth1  - Eth2  - Eth3  - Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CP */
24867 /* U  - Always DDR (relevant for local switch info)  - Always SRAM(relevant for local sw */
24868 /* itch info)  -Spare                                                                    */
24869 /*****************************************************************************************/
24870
24871 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE                                      ( 0x0 )
24872 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                          ( 0x0 )
24873 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE                         ( 0x0 )
24874 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
24875 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_LS_CFG_TRUE_VALUE                          ( 0x1 )
24876 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE                         ( 0x0 )
24877 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
24878 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_LS_CFG_TRUE_VALUE                          ( 0x1 )
24879 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE                          ( 0x0 )
24880 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SRAM_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24881 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SRAM_LS_CFG_TRUE_VALUE                           ( 0x1 )
24882 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE                           ( 0x0 )
24883 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_DDR_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
24884 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_DDR_LS_CFG_TRUE_VALUE                            ( 0x1 )
24885 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE                            ( 0x0 )
24886 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_LS_CFG_FALSE_VALUE_RESET_VALUE                ( 0x0 )
24887 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_LS_CFG_TRUE_VALUE                             ( 0x1 )
24888 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE                           ( 0x0 )
24889 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_LS_CFG_FALSE_VALUE_RESET_VALUE               ( 0x0 )
24890 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_LS_CFG_TRUE_VALUE                            ( 0x1 )
24891 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE                         ( 0x0 )
24892 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_LS_CFG_FALSE_VALUE_RESET_VALUE             ( 0x0 )
24893 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_LS_CFG_TRUE_VALUE                          ( 0x1 )
24894 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE                          ( 0x0 )
24895 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24896 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_LS_CFG_TRUE_VALUE                           ( 0x1 )
24897 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE                          ( 0x0 )
24898 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24899 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_LS_CFG_TRUE_VALUE                           ( 0x1 )
24900 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE                          ( 0x0 )
24901 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24902 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_LS_CFG_TRUE_VALUE                           ( 0x1 )
24903 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE                          ( 0x0 )
24904 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24905 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_LS_CFG_TRUE_VALUE                           ( 0x1 )
24906 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE                          ( 0x0 )
24907 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24908 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_LS_CFG_TRUE_VALUE                           ( 0x1 )
24909 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE                          ( 0x0 )
24910 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_LS_CFG_FALSE_VALUE_RESET_VALUE              ( 0x0 )
24911 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_LS_CFG_TRUE_VALUE                           ( 0x1 )
24912 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV1_RSV_VALUE                                      ( 0x0 )
24913 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_RSV1_RSV_VALUE_RESET_VALUE                          ( 0x0 )
24914 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
24915 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
24916 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_SPARE_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
24917 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
24918 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
24919 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE1_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
24920 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE                ( 0x0 )
24921 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE    ( 0x0 )
24922 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_MC_TM_CFG_SRAM_TARGET_MEMORY_VALUE               ( 0x1 )
24923 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE               ( 0x0 )
24924 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE   ( 0x0 )
24925 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_CPU_TM_CFG_SRAM_TARGET_MEMORY_VALUE              ( 0x1 )
24926 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE             ( 0x0 )
24927 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE ( 0x0 )
24928 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_PCIE0_TM_CFG_SRAM_TARGET_MEMORY_VALUE            ( 0x1 )
24929 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24930 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24931 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_GPON_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24932 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24933 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24934 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH4_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24935 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24936 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24937 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH3_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24938 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24939 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24940 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH2_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24941 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24942 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24943 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH1_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24944 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE              ( 0x0 )
24945 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_TM_CFG_DDR_TARGET_MEMORY_VALUE_RESET_VALUE  ( 0x0 )
24946 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_DP_ETH0_TM_CFG_SRAM_TARGET_MEMORY_VALUE             ( 0x1 )
24947
24948
24949 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_OFFSET ( 0x0000025C )
24950
24951 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_OFFSET )
24952 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_ADDRESS ), (r) )
24953 #define IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG_ADDRESS ), (v) )
24954
24955 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
24956 typedef struct
24957 {
24958         /* RSV2 */
24959         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24960
24961         /* DP_SPARE_LS_CFG */
24962         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24963
24964         /* DP_PCIE1_LS_CFG */
24965         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24966
24967         /* DP_SRAM_LS_CFG */
24968         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24969
24970         /* DP_DDR_LS_CFG */
24971         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24972
24973         /* DP_MC_LS_CFG */
24974         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24975
24976         /* DP_CPU_LS_CFG */
24977         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24978
24979         /* DP_PCIE0_LS_CFG */
24980         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24981
24982         /* DP_GPON_LS_CFG */
24983         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24984
24985         /* DP_ETH4_LS_CFG */
24986         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24987
24988         /* DP_ETH3_LS_CFG */
24989         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24990
24991         /* DP_ETH2_LS_CFG */
24992         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24993
24994         /* DP_ETH1_LS_CFG */
24995         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24996
24997         /* DP_ETH0_LS_CFG */
24998         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
24999
25000         /* rsv1 */
25001         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25002
25003         /* DP_SPARE_TM_CFG */
25004         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25005
25006         /* DP_PCIE1_TM_CFG */
25007         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25008
25009         /* DP_MC_TM_CFG */
25010         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25011
25012         /* DP_CPU_TM_CFG */
25013         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25014
25015         /* DP_PCIE0_TM_CFG */
25016         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25017
25018         /* DP_GPON_TM_CFG */
25019         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25020
25021         /* DP_ETH4_TM_CFG */
25022         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25023
25024         /* DP_ETH3_TM_CFG */
25025         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25026
25027         /* DP_ETH2_TM_CFG */
25028         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25029
25030         /* DP_ETH1_TM_CFG */
25031         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25032
25033         /* DP_ETH0_TM_CFG */
25034         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25035 }
25036 __PACKING_ATTRIBUTE_STRUCT_END__
25037 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG ;
25038 #else
25039 typedef struct
25040 {
25041         /* DP_ETH0_TM_CFG */
25042         uint32_t dp_eth0_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25043
25044         /* DP_ETH1_TM_CFG */
25045         uint32_t dp_eth1_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25046
25047         /* DP_ETH2_TM_CFG */
25048         uint32_t dp_eth2_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25049
25050         /* DP_ETH3_TM_CFG */
25051         uint32_t dp_eth3_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25052
25053         /* DP_ETH4_TM_CFG */
25054         uint32_t dp_eth4_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25055
25056         /* DP_GPON_TM_CFG */
25057         uint32_t dp_gpon_tm_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25058
25059         /* DP_PCIE0_TM_CFG */
25060         uint32_t dp_pcie0_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25061
25062         /* DP_CPU_TM_CFG */
25063         uint32_t dp_cpu_tm_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25064
25065         /* DP_MC_TM_CFG */
25066         uint32_t dp_mc_tm_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25067
25068         /* DP_PCIE1_TM_CFG */
25069         uint32_t dp_pcie1_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25070
25071         /* DP_SPARE_TM_CFG */
25072         uint32_t dp_spare_tm_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25073
25074         /* rsv1 */
25075         uint32_t rsv1                   : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25076
25077         /* DP_ETH0_LS_CFG */
25078         uint32_t dp_eth0_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25079
25080         /* DP_ETH1_LS_CFG */
25081         uint32_t dp_eth1_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25082
25083         /* DP_ETH2_LS_CFG */
25084         uint32_t dp_eth2_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25085
25086         /* DP_ETH3_LS_CFG */
25087         uint32_t dp_eth3_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25088
25089         /* DP_ETH4_LS_CFG */
25090         uint32_t dp_eth4_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25091
25092         /* DP_GPON_LS_CFG */
25093         uint32_t dp_gpon_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25094
25095         /* DP_PCIE0_LS_CFG */
25096         uint32_t dp_pcie0_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25097
25098         /* DP_CPU_LS_CFG */
25099         uint32_t dp_cpu_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25100
25101         /* DP_MC_LS_CFG */
25102         uint32_t dp_mc_ls_cfg           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25103
25104         /* DP_DDR_LS_CFG */
25105         uint32_t dp_ddr_ls_cfg          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25106
25107         /* DP_SRAM_LS_CFG */
25108         uint32_t dp_sram_ls_cfg         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25109
25110         /* DP_PCIE1_LS_CFG */
25111         uint32_t dp_pcie1_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25112
25113         /* DP_SPARE_LS_CFG */
25114         uint32_t dp_spare_ls_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25115
25116         /* RSV2 */
25117         uint32_t rsv2                   : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25118 }
25119 __PACKING_ATTRIBUTE_STRUCT_END__
25120 IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG ;
25121 #endif
25122
25123 /*****************************************************************************************/
25124 /* FW_EN_MTRX_ETH0_SP_CFG                                                                */
25125 /* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
25126 /* 0    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
25127 /* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
25128 /* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
25129 /* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
25130 /*****************************************************************************************/
25131
25132 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
25133 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
25134 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
25135 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
25136 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
25137 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25138 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25139 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25140 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25141 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25142 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25143 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25144 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25145 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25146 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25147 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25148 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25149 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25150 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25151 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25152 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
25153 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
25154 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
25155 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25156 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25157 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25158 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25159 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25160 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25161 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25162 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25163 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25164 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25165 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25166 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25167 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25168 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25169 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25170 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25171 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25172 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25173 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25174 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25175 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25176
25177
25178 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_OFFSET ( 0x00000260 )
25179
25180 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_OFFSET )
25181 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_ADDRESS ), (r) )
25182 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG_ADDRESS ), (v) )
25183
25184 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
25185 typedef struct
25186 {
25187         /* RSV2 */
25188         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25189
25190         /* SPARE */
25191         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25192
25193         /* DP_SPARE_FW_EN_CFG */
25194         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25195
25196         /* DP_PCIE1_FW_EN_CFG */
25197         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25198
25199         /* DP_SRAM_FW_EN_CFG */
25200         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25201
25202         /* DP_DDR_FW_EN_CFG */
25203         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25204
25205         /* DP_CPU_FW_EN_CFG */
25206         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25207
25208         /* DP_MC_FW_EN_CFG */
25209         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25210
25211         /* DP_PCIE0_FW_EN_CFG */
25212         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25213
25214         /* DP_GPON_FW_EN_CFG */
25215         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25216
25217         /* DP_ETH4_FW_EN_CFG */
25218         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25219
25220         /* DP_ETH3_FW_EN_CFG */
25221         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25222
25223         /* DP_ETH2_FW_EN_CFG */
25224         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25225
25226         /* DP_ETH1_FW_EN_CFG */
25227         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25228
25229         /* DP_ETH0_FW_EN_CFG */
25230         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25231 }
25232 __PACKING_ATTRIBUTE_STRUCT_END__
25233 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG ;
25234 #else
25235 typedef struct
25236 {
25237         /* DP_ETH0_FW_EN_CFG */
25238         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25239
25240         /* DP_ETH1_FW_EN_CFG */
25241         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25242
25243         /* DP_ETH2_FW_EN_CFG */
25244         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25245
25246         /* DP_ETH3_FW_EN_CFG */
25247         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25248
25249         /* DP_ETH4_FW_EN_CFG */
25250         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25251
25252         /* DP_GPON_FW_EN_CFG */
25253         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25254
25255         /* DP_PCIE0_FW_EN_CFG */
25256         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25257
25258         /* DP_MC_FW_EN_CFG */
25259         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25260
25261         /* DP_CPU_FW_EN_CFG */
25262         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25263
25264         /* DP_DDR_FW_EN_CFG */
25265         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25266
25267         /* DP_SRAM_FW_EN_CFG */
25268         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25269
25270         /* DP_PCIE1_FW_EN_CFG */
25271         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25272
25273         /* DP_SPARE_FW_EN_CFG */
25274         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25275
25276         /* SPARE */
25277         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25278
25279         /* RSV2 */
25280         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25281 }
25282 __PACKING_ATTRIBUTE_STRUCT_END__
25283 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG ;
25284 #endif
25285
25286 /*****************************************************************************************/
25287 /* FW_EN_MTRX_ETH1_SP_CFG                                                                */
25288 /* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
25289 /* 1    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
25290 /* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
25291 /* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
25292 /* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
25293 /*****************************************************************************************/
25294
25295 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
25296 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
25297 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
25298 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
25299 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
25300 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25301 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25302 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25303 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25304 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25305 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25306 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25307 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25308 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25309 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25310 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25311 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25312 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25313 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25314 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25315 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
25316 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
25317 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
25318 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25319 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25320 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25321 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25322 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25323 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25324 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25325 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25326 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25327 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25328 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25329 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25330 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25331 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25332 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25333 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25334 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25335 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25336 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25337 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25338 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25339
25340
25341 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_OFFSET ( 0x00000264 )
25342
25343 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_OFFSET )
25344 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_ADDRESS ), (r) )
25345 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG_ADDRESS ), (v) )
25346
25347 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
25348 typedef struct
25349 {
25350         /* RSV2 */
25351         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25352
25353         /* SPARE */
25354         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25355
25356         /* DP_SPARE_FW_EN_CFG */
25357         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25358
25359         /* DP_PCIE1_FW_EN_CFG */
25360         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25361
25362         /* DP_SRAM_FW_EN_CFG */
25363         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25364
25365         /* DP_DDR_FW_EN_CFG */
25366         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25367
25368         /* DP_CPU_FW_EN_CFG */
25369         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25370
25371         /* DP_MC_FW_EN_CFG */
25372         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25373
25374         /* DP_PCIE0_FW_EN_CFG */
25375         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25376
25377         /* DP_GPON_FW_EN_CFG */
25378         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25379
25380         /* DP_ETH4_FW_EN_CFG */
25381         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25382
25383         /* DP_ETH3_FW_EN_CFG */
25384         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25385
25386         /* DP_ETH2_FW_EN_CFG */
25387         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25388
25389         /* DP_ETH1_FW_EN_CFG */
25390         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25391
25392         /* DP_ETH0_FW_EN_CFG */
25393         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25394 }
25395 __PACKING_ATTRIBUTE_STRUCT_END__
25396 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG ;
25397 #else
25398 typedef struct
25399 {
25400         /* DP_ETH0_FW_EN_CFG */
25401         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25402
25403         /* DP_ETH1_FW_EN_CFG */
25404         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25405
25406         /* DP_ETH2_FW_EN_CFG */
25407         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25408
25409         /* DP_ETH3_FW_EN_CFG */
25410         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25411
25412         /* DP_ETH4_FW_EN_CFG */
25413         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25414
25415         /* DP_GPON_FW_EN_CFG */
25416         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25417
25418         /* DP_PCIE0_FW_EN_CFG */
25419         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25420
25421         /* DP_MC_FW_EN_CFG */
25422         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25423
25424         /* DP_CPU_FW_EN_CFG */
25425         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25426
25427         /* DP_DDR_FW_EN_CFG */
25428         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25429
25430         /* DP_SRAM_FW_EN_CFG */
25431         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25432
25433         /* DP_PCIE1_FW_EN_CFG */
25434         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25435
25436         /* DP_SPARE_FW_EN_CFG */
25437         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25438
25439         /* SPARE */
25440         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25441
25442         /* RSV2 */
25443         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25444 }
25445 __PACKING_ATTRIBUTE_STRUCT_END__
25446 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG ;
25447 #endif
25448
25449 /*****************************************************************************************/
25450 /* FW_EN_MTRX_ETH2_SP_CFG                                                                */
25451 /* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
25452 /* 2    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
25453 /* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
25454 /* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
25455 /* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
25456 /*****************************************************************************************/
25457
25458 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
25459 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
25460 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
25461 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
25462 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
25463 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25464 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25465 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25466 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25467 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25468 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25469 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25470 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25471 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25472 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25473 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25474 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25475 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25476 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25477 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25478 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
25479 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
25480 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
25481 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25482 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25483 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25484 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25485 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25486 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25487 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25488 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25489 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25490 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25491 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25492 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25493 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25494 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25495 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25496 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25497 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25498 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25499 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25500 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25501 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25502
25503
25504 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_OFFSET ( 0x00000268 )
25505
25506 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_OFFSET )
25507 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_ADDRESS ), (r) )
25508 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG_ADDRESS ), (v) )
25509
25510 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
25511 typedef struct
25512 {
25513         /* RSV2 */
25514         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25515
25516         /* SPARE */
25517         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25518
25519         /* DP_SPARE_FW_EN_CFG */
25520         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25521
25522         /* DP_PCIE1_FW_EN_CFG */
25523         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25524
25525         /* DP_SRAM_FW_EN_CFG */
25526         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25527
25528         /* DP_DDR_FW_EN_CFG */
25529         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25530
25531         /* DP_CPU_FW_EN_CFG */
25532         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25533
25534         /* DP_MC_FW_EN_CFG */
25535         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25536
25537         /* DP_PCIE0_FW_EN_CFG */
25538         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25539
25540         /* DP_GPON_FW_EN_CFG */
25541         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25542
25543         /* DP_ETH4_FW_EN_CFG */
25544         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25545
25546         /* DP_ETH3_FW_EN_CFG */
25547         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25548
25549         /* DP_ETH2_FW_EN_CFG */
25550         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25551
25552         /* DP_ETH1_FW_EN_CFG */
25553         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25554
25555         /* DP_ETH0_FW_EN_CFG */
25556         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25557 }
25558 __PACKING_ATTRIBUTE_STRUCT_END__
25559 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG ;
25560 #else
25561 typedef struct
25562 {
25563         /* DP_ETH0_FW_EN_CFG */
25564         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25565
25566         /* DP_ETH1_FW_EN_CFG */
25567         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25568
25569         /* DP_ETH2_FW_EN_CFG */
25570         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25571
25572         /* DP_ETH3_FW_EN_CFG */
25573         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25574
25575         /* DP_ETH4_FW_EN_CFG */
25576         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25577
25578         /* DP_GPON_FW_EN_CFG */
25579         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25580
25581         /* DP_PCIE0_FW_EN_CFG */
25582         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25583
25584         /* DP_MC_FW_EN_CFG */
25585         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25586
25587         /* DP_CPU_FW_EN_CFG */
25588         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25589
25590         /* DP_DDR_FW_EN_CFG */
25591         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25592
25593         /* DP_SRAM_FW_EN_CFG */
25594         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25595
25596         /* DP_PCIE1_FW_EN_CFG */
25597         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25598
25599         /* DP_SPARE_FW_EN_CFG */
25600         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25601
25602         /* SPARE */
25603         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25604
25605         /* RSV2 */
25606         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25607 }
25608 __PACKING_ATTRIBUTE_STRUCT_END__
25609 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG ;
25610 #endif
25611
25612 /*****************************************************************************************/
25613 /* FW_EN_MTRX_ETH3_SP_CFG                                                                */
25614 /* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
25615 /* 3    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
25616 /* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
25617 /* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
25618 /* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
25619 /*****************************************************************************************/
25620
25621 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
25622 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
25623 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
25624 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
25625 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
25626 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25627 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25628 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25629 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25630 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25631 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25632 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25633 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25634 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25635 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25636 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25637 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25638 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25639 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25640 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25641 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
25642 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
25643 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
25644 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25645 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25646 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25647 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25648 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25649 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25650 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25651 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25652 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25653 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25654 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25655 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25656 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25657 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25658 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25659 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25660 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25661 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25662 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25663 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25664 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25665
25666
25667 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_OFFSET ( 0x0000026C )
25668
25669 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_OFFSET )
25670 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_ADDRESS ), (r) )
25671 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG_ADDRESS ), (v) )
25672
25673 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
25674 typedef struct
25675 {
25676         /* RSV2 */
25677         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25678
25679         /* SPARE */
25680         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25681
25682         /* DP_SPARE_FW_EN_CFG */
25683         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25684
25685         /* DP_PCIE1_FW_EN_CFG */
25686         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25687
25688         /* DP_SRAM_FW_EN_CFG */
25689         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25690
25691         /* DP_DDR_FW_EN_CFG */
25692         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25693
25694         /* DP_CPU_FW_EN_CFG */
25695         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25696
25697         /* DP_MC_FW_EN_CFG */
25698         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25699
25700         /* DP_PCIE0_FW_EN_CFG */
25701         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25702
25703         /* DP_GPON_FW_EN_CFG */
25704         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25705
25706         /* DP_ETH4_FW_EN_CFG */
25707         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25708
25709         /* DP_ETH3_FW_EN_CFG */
25710         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25711
25712         /* DP_ETH2_FW_EN_CFG */
25713         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25714
25715         /* DP_ETH1_FW_EN_CFG */
25716         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25717
25718         /* DP_ETH0_FW_EN_CFG */
25719         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25720 }
25721 __PACKING_ATTRIBUTE_STRUCT_END__
25722 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG ;
25723 #else
25724 typedef struct
25725 {
25726         /* DP_ETH0_FW_EN_CFG */
25727         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25728
25729         /* DP_ETH1_FW_EN_CFG */
25730         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25731
25732         /* DP_ETH2_FW_EN_CFG */
25733         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25734
25735         /* DP_ETH3_FW_EN_CFG */
25736         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25737
25738         /* DP_ETH4_FW_EN_CFG */
25739         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25740
25741         /* DP_GPON_FW_EN_CFG */
25742         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25743
25744         /* DP_PCIE0_FW_EN_CFG */
25745         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25746
25747         /* DP_MC_FW_EN_CFG */
25748         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25749
25750         /* DP_CPU_FW_EN_CFG */
25751         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25752
25753         /* DP_DDR_FW_EN_CFG */
25754         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25755
25756         /* DP_SRAM_FW_EN_CFG */
25757         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25758
25759         /* DP_PCIE1_FW_EN_CFG */
25760         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25761
25762         /* DP_SPARE_FW_EN_CFG */
25763         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25764
25765         /* SPARE */
25766         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25767
25768         /* RSV2 */
25769         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25770 }
25771 __PACKING_ATTRIBUTE_STRUCT_END__
25772 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG ;
25773 #endif
25774
25775 /*****************************************************************************************/
25776 /* FW_EN_MTRX_ETH4_SP_CFG                                                                */
25777 /* Forward Enable configurations for each path in target matrix, while Source Port = Eth */
25778 /* 4    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
25779 /* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
25780 /* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
25781 /* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
25782 /*****************************************************************************************/
25783
25784 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
25785 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
25786 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
25787 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
25788 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
25789 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25790 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25791 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25792 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25793 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25794 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25795 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25796 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25797 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25798 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25799 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25800 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25801 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25802 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25803 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25804 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
25805 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
25806 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
25807 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25808 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25809 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25810 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25811 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25812 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25813 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25814 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25815 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25816 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25817 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25818 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25819 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25820 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25821 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25822 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25823 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25824 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25825 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25826 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25827 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25828
25829
25830 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_OFFSET ( 0x00000270 )
25831
25832 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_OFFSET )
25833 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_ADDRESS ), (r) )
25834 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG_ADDRESS ), (v) )
25835
25836 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
25837 typedef struct
25838 {
25839         /* RSV2 */
25840         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25841
25842         /* SPARE */
25843         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25844
25845         /* DP_SPARE_FW_EN_CFG */
25846         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25847
25848         /* DP_PCIE1_FW_EN_CFG */
25849         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25850
25851         /* DP_SRAM_FW_EN_CFG */
25852         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25853
25854         /* DP_DDR_FW_EN_CFG */
25855         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25856
25857         /* DP_CPU_FW_EN_CFG */
25858         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25859
25860         /* DP_MC_FW_EN_CFG */
25861         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25862
25863         /* DP_PCIE0_FW_EN_CFG */
25864         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25865
25866         /* DP_GPON_FW_EN_CFG */
25867         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25868
25869         /* DP_ETH4_FW_EN_CFG */
25870         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25871
25872         /* DP_ETH3_FW_EN_CFG */
25873         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25874
25875         /* DP_ETH2_FW_EN_CFG */
25876         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25877
25878         /* DP_ETH1_FW_EN_CFG */
25879         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25880
25881         /* DP_ETH0_FW_EN_CFG */
25882         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25883 }
25884 __PACKING_ATTRIBUTE_STRUCT_END__
25885 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG ;
25886 #else
25887 typedef struct
25888 {
25889         /* DP_ETH0_FW_EN_CFG */
25890         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25891
25892         /* DP_ETH1_FW_EN_CFG */
25893         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25894
25895         /* DP_ETH2_FW_EN_CFG */
25896         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25897
25898         /* DP_ETH3_FW_EN_CFG */
25899         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25900
25901         /* DP_ETH4_FW_EN_CFG */
25902         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25903
25904         /* DP_GPON_FW_EN_CFG */
25905         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25906
25907         /* DP_PCIE0_FW_EN_CFG */
25908         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25909
25910         /* DP_MC_FW_EN_CFG */
25911         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25912
25913         /* DP_CPU_FW_EN_CFG */
25914         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25915
25916         /* DP_DDR_FW_EN_CFG */
25917         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25918
25919         /* DP_SRAM_FW_EN_CFG */
25920         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25921
25922         /* DP_PCIE1_FW_EN_CFG */
25923         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25924
25925         /* DP_SPARE_FW_EN_CFG */
25926         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25927
25928         /* SPARE */
25929         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25930
25931         /* RSV2 */
25932         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
25933 }
25934 __PACKING_ATTRIBUTE_STRUCT_END__
25935 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG ;
25936 #endif
25937
25938 /*****************************************************************************************/
25939 /* FW_EN_MTRX_GPON_SP_CFG                                                                */
25940 /* Forward Enable configurations for each path in target matrix, while Source Port = GPO */
25941 /* N    Used by FW as enable information for each path in Target Matrix. Forwarded in RI */
25942 /* B, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  -  */
25943 /* Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local sw */
25944 /* itch info)  - Always SRAM(relevant for local switch info)  -Spare                     */
25945 /*****************************************************************************************/
25946
25947 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
25948 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
25949 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
25950 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
25951 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
25952 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25953 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25954 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25955 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25956 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25957 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25958 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25959 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25960 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25961 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25962 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25963 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25964 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
25965 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
25966 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
25967 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
25968 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
25969 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
25970 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
25971 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
25972 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
25973 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25974 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25975 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25976 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25977 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25978 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25979 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25980 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25981 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25982 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25983 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25984 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25985 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25986 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25987 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25988 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
25989 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
25990 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
25991
25992
25993 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_OFFSET ( 0x00000274 )
25994
25995 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_OFFSET )
25996 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_ADDRESS ), (r) )
25997 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG_ADDRESS ), (v) )
25998
25999 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26000 typedef struct
26001 {
26002         /* RSV2 */
26003         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26004
26005         /* SPARE */
26006         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26007
26008         /* DP_SPARE_FW_EN_CFG */
26009         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26010
26011         /* DP_PCIE1_FW_EN_CFG */
26012         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26013
26014         /* DP_SRAM_FW_EN_CFG */
26015         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26016
26017         /* DP_DDR_FW_EN_CFG */
26018         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26019
26020         /* DP_CPU_FW_EN_CFG */
26021         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26022
26023         /* DP_MC_FW_EN_CFG */
26024         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26025
26026         /* DP_PCIE0_FW_EN_CFG */
26027         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26028
26029         /* DP_GPON_FW_EN_CFG */
26030         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26031
26032         /* DP_ETH4_FW_EN_CFG */
26033         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26034
26035         /* DP_ETH3_FW_EN_CFG */
26036         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26037
26038         /* DP_ETH2_FW_EN_CFG */
26039         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26040
26041         /* DP_ETH1_FW_EN_CFG */
26042         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26043
26044         /* DP_ETH0_FW_EN_CFG */
26045         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26046 }
26047 __PACKING_ATTRIBUTE_STRUCT_END__
26048 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG ;
26049 #else
26050 typedef struct
26051 {
26052         /* DP_ETH0_FW_EN_CFG */
26053         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26054
26055         /* DP_ETH1_FW_EN_CFG */
26056         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26057
26058         /* DP_ETH2_FW_EN_CFG */
26059         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26060
26061         /* DP_ETH3_FW_EN_CFG */
26062         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26063
26064         /* DP_ETH4_FW_EN_CFG */
26065         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26066
26067         /* DP_GPON_FW_EN_CFG */
26068         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26069
26070         /* DP_PCIE0_FW_EN_CFG */
26071         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26072
26073         /* DP_MC_FW_EN_CFG */
26074         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26075
26076         /* DP_CPU_FW_EN_CFG */
26077         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26078
26079         /* DP_DDR_FW_EN_CFG */
26080         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26081
26082         /* DP_SRAM_FW_EN_CFG */
26083         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26084
26085         /* DP_PCIE1_FW_EN_CFG */
26086         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26087
26088         /* DP_SPARE_FW_EN_CFG */
26089         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26090
26091         /* SPARE */
26092         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26093
26094         /* RSV2 */
26095         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26096 }
26097 __PACKING_ATTRIBUTE_STRUCT_END__
26098 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG ;
26099 #endif
26100
26101 /*****************************************************************************************/
26102 /* FW_EN_MTRX_PCIE0_SP_CFG                                                               */
26103 /* Forward Enable configurations for each path in target matrix, while Source Port = PCI */
26104 /* E0    Used by FW as enable information for each path in Target Matrix. Forwarded in R */
26105 /* IB, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  - */
26106 /*  Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local s */
26107 /* witch info)  - Always SRAM(relevant for local switch info)  -Spare                    */
26108 /*****************************************************************************************/
26109
26110 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
26111 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
26112 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
26113 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
26114 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
26115 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
26116 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
26117 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
26118 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
26119 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
26120 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
26121 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26122 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26123 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26124 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
26125 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
26126 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
26127 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
26128 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
26129 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
26130 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
26131 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
26132 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
26133 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
26134 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
26135 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
26136 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26137 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26138 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26139 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26140 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26141 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26142 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26143 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26144 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26145 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26146 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26147 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26148 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26149 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26150 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26151 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26152 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26153 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26154
26155
26156 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_OFFSET ( 0x00000278 )
26157
26158 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_OFFSET )
26159 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_ADDRESS ), (r) )
26160 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG_ADDRESS ), (v) )
26161
26162 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26163 typedef struct
26164 {
26165         /* RSV2 */
26166         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26167
26168         /* SPARE */
26169         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26170
26171         /* DP_SPARE_FW_EN_CFG */
26172         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26173
26174         /* DP_PCIE1_FW_EN_CFG */
26175         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26176
26177         /* DP_SRAM_FW_EN_CFG */
26178         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26179
26180         /* DP_DDR_FW_EN_CFG */
26181         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26182
26183         /* DP_CPU_FW_EN_CFG */
26184         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26185
26186         /* DP_MC_FW_EN_CFG */
26187         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26188
26189         /* DP_PCIE0_FW_EN_CFG */
26190         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26191
26192         /* DP_GPON_FW_EN_CFG */
26193         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26194
26195         /* DP_ETH4_FW_EN_CFG */
26196         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26197
26198         /* DP_ETH3_FW_EN_CFG */
26199         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26200
26201         /* DP_ETH2_FW_EN_CFG */
26202         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26203
26204         /* DP_ETH1_FW_EN_CFG */
26205         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26206
26207         /* DP_ETH0_FW_EN_CFG */
26208         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26209 }
26210 __PACKING_ATTRIBUTE_STRUCT_END__
26211 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG ;
26212 #else
26213 typedef struct
26214 {
26215         /* DP_ETH0_FW_EN_CFG */
26216         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26217
26218         /* DP_ETH1_FW_EN_CFG */
26219         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26220
26221         /* DP_ETH2_FW_EN_CFG */
26222         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26223
26224         /* DP_ETH3_FW_EN_CFG */
26225         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26226
26227         /* DP_ETH4_FW_EN_CFG */
26228         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26229
26230         /* DP_GPON_FW_EN_CFG */
26231         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26232
26233         /* DP_PCIE0_FW_EN_CFG */
26234         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26235
26236         /* DP_MC_FW_EN_CFG */
26237         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26238
26239         /* DP_CPU_FW_EN_CFG */
26240         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26241
26242         /* DP_DDR_FW_EN_CFG */
26243         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26244
26245         /* DP_SRAM_FW_EN_CFG */
26246         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26247
26248         /* DP_PCIE1_FW_EN_CFG */
26249         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26250
26251         /* DP_SPARE_FW_EN_CFG */
26252         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26253
26254         /* SPARE */
26255         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26256
26257         /* RSV2 */
26258         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26259 }
26260 __PACKING_ATTRIBUTE_STRUCT_END__
26261 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG ;
26262 #endif
26263
26264 /*****************************************************************************************/
26265 /* FW_EN_MTRX_PCIE1_SP_CFG                                                               */
26266 /* Forward Enable configurations for each path in target matrix, while Source Port = PCI */
26267 /* E1    Used by FW as enable information for each path in Target Matrix. Forwarded in R */
26268 /* IB, Configuration per following destination ports:  - Eth0  - Eth1  - Eth2  - Eth3  - */
26269 /*  Eth4  - GPON  - PCIe0/1  - Multicast (MC)  - CPU  - Always DDR (relevant for local s */
26270 /* witch info)  - Always SRAM(relevant for local switch info)  -Spare                    */
26271 /*****************************************************************************************/
26272
26273 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE                             ( 0x0 )
26274 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_RSV2_RSV_VALUE_RESET_VALUE                 ( 0x0 )
26275 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_SPARE_FALSE_VALUE                          ( 0x0 )
26276 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_SPARE_FALSE_VALUE_RESET_VALUE              ( 0x0 )
26277 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_SPARE_TRUE_VALUE                           ( 0x1 )
26278 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
26279 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SPARE_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
26280 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SPARE_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
26281 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
26282 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
26283 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE1_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
26284 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26285 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SRAM_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26286 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_SRAM_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26287 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
26288 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_DDR_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
26289 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_DDR_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
26290 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE               ( 0x0 )
26291 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_CPU_FW_EN_CFG_FALSE_VALUE_RESET_VALUE   ( 0x0 )
26292 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_CPU_FW_EN_CFG_TRUE_VALUE                ( 0x1 )
26293 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE                ( 0x0 )
26294 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_MC_FW_EN_CFG_FALSE_VALUE_RESET_VALUE    ( 0x0 )
26295 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_MC_FW_EN_CFG_TRUE_VALUE                 ( 0x1 )
26296 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE             ( 0x0 )
26297 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE ( 0x0 )
26298 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_PCIE0_FW_EN_CFG_TRUE_VALUE              ( 0x1 )
26299 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26300 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_GPON_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26301 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_GPON_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26302 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26303 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH4_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26304 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH4_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26305 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26306 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH3_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26307 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH3_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26308 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26309 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH2_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26310 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH2_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26311 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26312 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH1_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26313 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH1_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26314 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE              ( 0x0 )
26315 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH0_FW_EN_CFG_FALSE_VALUE_RESET_VALUE  ( 0x0 )
26316 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_DP_ETH0_FW_EN_CFG_TRUE_VALUE               ( 0x1 )
26317
26318
26319 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_OFFSET ( 0x0000027C )
26320
26321 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_ADDRESS           ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_OFFSET )
26322 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_READ( r )         READ_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_ADDRESS ), (r) )
26323 #define IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_WRITE( v )        WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG_ADDRESS ), (v) )
26324
26325 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26326 typedef struct
26327 {
26328         /* RSV2 */
26329         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26330
26331         /* SPARE */
26332         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26333
26334         /* DP_SPARE_FW_EN_CFG */
26335         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26336
26337         /* DP_PCIE1_FW_EN_CFG */
26338         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26339
26340         /* DP_SRAM_FW_EN_CFG */
26341         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26342
26343         /* DP_DDR_FW_EN_CFG */
26344         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26345
26346         /* DP_CPU_FW_EN_CFG */
26347         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26348
26349         /* DP_MC_FW_EN_CFG */
26350         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26351
26352         /* DP_PCIE0_FW_EN_CFG */
26353         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26354
26355         /* DP_GPON_FW_EN_CFG */
26356         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26357
26358         /* DP_ETH4_FW_EN_CFG */
26359         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26360
26361         /* DP_ETH3_FW_EN_CFG */
26362         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26363
26364         /* DP_ETH2_FW_EN_CFG */
26365         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26366
26367         /* DP_ETH1_FW_EN_CFG */
26368         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26369
26370         /* DP_ETH0_FW_EN_CFG */
26371         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26372 }
26373 __PACKING_ATTRIBUTE_STRUCT_END__
26374 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG ;
26375 #else
26376 typedef struct
26377 {
26378         /* DP_ETH0_FW_EN_CFG */
26379         uint32_t dp_eth0_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26380
26381         /* DP_ETH1_FW_EN_CFG */
26382         uint32_t dp_eth1_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26383
26384         /* DP_ETH2_FW_EN_CFG */
26385         uint32_t dp_eth2_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26386
26387         /* DP_ETH3_FW_EN_CFG */
26388         uint32_t dp_eth3_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26389
26390         /* DP_ETH4_FW_EN_CFG */
26391         uint32_t dp_eth4_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26392
26393         /* DP_GPON_FW_EN_CFG */
26394         uint32_t dp_gpon_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26395
26396         /* DP_PCIE0_FW_EN_CFG */
26397         uint32_t dp_pcie0_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26398
26399         /* DP_MC_FW_EN_CFG */
26400         uint32_t dp_mc_fw_en_cfg        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26401
26402         /* DP_CPU_FW_EN_CFG */
26403         uint32_t dp_cpu_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26404
26405         /* DP_DDR_FW_EN_CFG */
26406         uint32_t dp_ddr_fw_en_cfg       : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26407
26408         /* DP_SRAM_FW_EN_CFG */
26409         uint32_t dp_sram_fw_en_cfg      : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26410
26411         /* DP_PCIE1_FW_EN_CFG */
26412         uint32_t dp_pcie1_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26413
26414         /* DP_SPARE_FW_EN_CFG */
26415         uint32_t dp_spare_fw_en_cfg     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26416
26417         /* SPARE */
26418         uint32_t spare                  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26419
26420         /* RSV2 */
26421         uint32_t rsv2                   : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26422 }
26423 __PACKING_ATTRIBUTE_STRUCT_END__
26424 IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG ;
26425 #endif
26426
26427 /*****************************************************************************************/
26428 /* PH_MEM_RD_RQST_CFG                                                                    */
26429 /* Packet Header Memory Read request register.    The read of Packet Header memory is us */
26430 /* ed for debug needs. We can actually print out all Ingress Buffers = (Packet Headers f */
26431 /* iled by BBH/Runner to their slots). The read is done by inderect way: user puts addre */
26432 /* ss of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the */
26433 /*  BSY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_ */
26434 /* DATA_HIGH                                                                             */
26435 /*****************************************************************************************/
26436
26437 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_BSY_NON_BUSY_VALUE             ( 0x0 )
26438 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_BSY_NON_BUSY_VALUE_RESET_VALUE ( 0x0 )
26439 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_BSY_BUSY_VALUE                 ( 0x1 )
26440 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_RSV_RSV_VALUE                                 ( 0x0 )
26441 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_RSV_RSV_VALUE_RESET_VALUE                     ( 0x0 )
26442 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_ADDR_VALUE_VALUE               ( 0x0 )
26443 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_PH_MEM_RD_RQST_ADDR_VALUE_VALUE_RESET_VALUE   ( 0x0 )
26444
26445
26446 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_OFFSET ( 0x00000280 )
26447
26448 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_OFFSET )
26449 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_ADDRESS ), (r) )
26450 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG_ADDRESS ), (v) )
26451
26452 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26453 typedef struct
26454 {
26455         /* PH_MEM_RD_RQST_BSY */
26456         uint32_t ph_mem_rd_rqst_bsy     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26457
26458         /* RSV */
26459         uint32_t rsv                    : 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26460
26461         /* PH_MEM_RD_RQST_ADDR */
26462         uint32_t ph_mem_rd_rqst_addr    : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26463 }
26464 __PACKING_ATTRIBUTE_STRUCT_END__
26465 IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG ;
26466 #else
26467 typedef struct
26468 {
26469         /* PH_MEM_RD_RQST_ADDR */
26470         uint32_t ph_mem_rd_rqst_addr    : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26471
26472         /* RSV */
26473         uint32_t rsv                    : 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26474
26475         /* PH_MEM_RD_RQST_BSY */
26476         uint32_t ph_mem_rd_rqst_bsy     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26477 }
26478 __PACKING_ATTRIBUTE_STRUCT_END__
26479 IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG ;
26480 #endif
26481
26482 /*****************************************************************************************/
26483 /* PH_MEM_RD_DATA_LOW                                                                    */
26484 /* Packet Header Memory Read data low [31:0]    The read of Packet Header memory is used */
26485 /*  for debug needs. We can actually print out all Ingress Buffers = (Packet Headers fil */
26486 /* ed by BBH/Runner to their slots). The read is done by inderect way: user puts address */
26487 /*  of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the B */
26488 /* SY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_DA */
26489 /* TA_HIGH                                                                               */
26490 /*****************************************************************************************/
26491
26492 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_DATA_VALUE_VALUE             ( 0x0 )
26493 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
26494
26495
26496 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_OFFSET ( 0x00000284 )
26497
26498 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_ADDRESS        ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_OFFSET )
26499 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_READ( r )      READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_ADDRESS ), (r) )
26500 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_WRITE( v )     WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW_ADDRESS ), (v) )
26501
26502 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26503 typedef struct
26504 {
26505         /* DATA */
26506         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26507 }
26508 __PACKING_ATTRIBUTE_STRUCT_END__
26509 IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW ;
26510 #else
26511 typedef struct
26512 {
26513         /* DATA */
26514         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26515 }
26516 __PACKING_ATTRIBUTE_STRUCT_END__
26517 IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW ;
26518 #endif
26519
26520 /*****************************************************************************************/
26521 /* PH_MEM_RD_DATA_HIGH                                                                   */
26522 /* Packet Header Memory Read data high [63:32]    The read of Packet Header memory is us */
26523 /* ed for debug needs. We can actually print out all Ingress Buffers = (Packet Headers f */
26524 /* iled by BBH/Runner to their slots). The read is done by inderect way: user puts addre */
26525 /* ss of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the */
26526 /*  BSY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_ */
26527 /* DATA_HIGH                                                                             */
26528 /*****************************************************************************************/
26529
26530 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE             ( 0x0 )
26531 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
26532
26533
26534 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_OFFSET ( 0x00000288 )
26535
26536 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_ADDRESS       ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_OFFSET )
26537 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_READ( r )     READ_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_ADDRESS ), (r) )
26538 #define IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_WRITE( v )    WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH_ADDRESS ), (v) )
26539
26540 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26541 typedef struct
26542 {
26543         /* DATA */
26544         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26545 }
26546 __PACKING_ATTRIBUTE_STRUCT_END__
26547 IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH ;
26548 #else
26549 typedef struct
26550 {
26551         /* DATA */
26552         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26553 }
26554 __PACKING_ATTRIBUTE_STRUCT_END__
26555 IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH ;
26556 #endif
26557
26558 /*****************************************************************************************/
26559 /* SN_REG_0                                                                              */
26560 /* Serial Number status register0 for ports:  - Eth0  - Eth1    This register is used fo */
26561 /* r debug only                                                                          */
26562 /*****************************************************************************************/
26563
26564 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH1_SN_VALUE             ( 0x0 )
26565 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH1_SN_VALUE_RESET_VALUE ( 0x0 )
26566 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH0_SN_VALUE             ( 0x0 )
26567 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_SN_ETH0_SN_VALUE_RESET_VALUE ( 0x0 )
26568
26569
26570 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_OFFSET ( 0x0000028C )
26571
26572 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_OFFSET )
26573 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_ADDRESS ), (r) )
26574 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_0_ADDRESS ), (v) )
26575
26576 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26577 typedef struct
26578 {
26579         /* SN_ETH1 */
26580         uint32_t sn_eth1        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26581
26582         /* SN_ETH0 */
26583         uint32_t sn_eth0        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26584 }
26585 __PACKING_ATTRIBUTE_STRUCT_END__
26586 IH_REGS_GENERAL_CONFIGURATION_SN_REG_0 ;
26587 #else
26588 typedef struct
26589 {
26590         /* SN_ETH0 */
26591         uint32_t sn_eth0        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26592
26593         /* SN_ETH1 */
26594         uint32_t sn_eth1        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26595 }
26596 __PACKING_ATTRIBUTE_STRUCT_END__
26597 IH_REGS_GENERAL_CONFIGURATION_SN_REG_0 ;
26598 #endif
26599
26600 /*****************************************************************************************/
26601 /* SN_REG_1                                                                              */
26602 /* Serial Number status register1 for ports:  - Eth2  - Eth3  This register is used for  */
26603 /* debug only                                                                            */
26604 /*****************************************************************************************/
26605
26606 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH3_SN_VALUE             ( 0x0 )
26607 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH3_SN_VALUE_RESET_VALUE ( 0x0 )
26608 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH2_SN_VALUE             ( 0x0 )
26609 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_SN_ETH2_SN_VALUE_RESET_VALUE ( 0x0 )
26610
26611
26612 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_OFFSET ( 0x00000290 )
26613
26614 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_OFFSET )
26615 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_ADDRESS ), (r) )
26616 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_1_ADDRESS ), (v) )
26617
26618 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26619 typedef struct
26620 {
26621         /* SN_ETH3 */
26622         uint32_t sn_eth3        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26623
26624         /* SN_ETH2 */
26625         uint32_t sn_eth2        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26626 }
26627 __PACKING_ATTRIBUTE_STRUCT_END__
26628 IH_REGS_GENERAL_CONFIGURATION_SN_REG_1 ;
26629 #else
26630 typedef struct
26631 {
26632         /* SN_ETH2 */
26633         uint32_t sn_eth2        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26634
26635         /* SN_ETH3 */
26636         uint32_t sn_eth3        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26637 }
26638 __PACKING_ATTRIBUTE_STRUCT_END__
26639 IH_REGS_GENERAL_CONFIGURATION_SN_REG_1 ;
26640 #endif
26641
26642 /*****************************************************************************************/
26643 /* SN_REG_2                                                                              */
26644 /* Serial Number status register2 for ports:  - Eth4  - GPON  This register is used for  */
26645 /* debug only                                                                            */
26646 /*****************************************************************************************/
26647
26648 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_GPON_SN_VALUE             ( 0x0 )
26649 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_GPON_SN_VALUE_RESET_VALUE ( 0x0 )
26650 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_ETH4_SN_VALUE             ( 0x0 )
26651 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_SN_ETH4_SN_VALUE_RESET_VALUE ( 0x0 )
26652
26653
26654 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_OFFSET ( 0x00000294 )
26655
26656 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_OFFSET )
26657 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_ADDRESS ), (r) )
26658 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_2_ADDRESS ), (v) )
26659
26660 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26661 typedef struct
26662 {
26663         /* SN_GPON */
26664         uint32_t sn_gpon        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26665
26666         /* SN_ETH4 */
26667         uint32_t sn_eth4        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26668 }
26669 __PACKING_ATTRIBUTE_STRUCT_END__
26670 IH_REGS_GENERAL_CONFIGURATION_SN_REG_2 ;
26671 #else
26672 typedef struct
26673 {
26674         /* SN_ETH4 */
26675         uint32_t sn_eth4        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26676
26677         /* SN_GPON */
26678         uint32_t sn_gpon        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26679 }
26680 __PACKING_ATTRIBUTE_STRUCT_END__
26681 IH_REGS_GENERAL_CONFIGURATION_SN_REG_2 ;
26682 #endif
26683
26684 /*****************************************************************************************/
26685 /* SN_REG_3                                                                              */
26686 /* Serial Number status register3 for ports:  - Runner A  - Runner B  This register is u */
26687 /* sed for debug only                                                                    */
26688 /*****************************************************************************************/
26689
26690 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRB_SN_VALUE             ( 0x0 )
26691 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRB_SN_VALUE_RESET_VALUE ( 0x0 )
26692 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRA_SN_VALUE             ( 0x0 )
26693 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_SN_RNRA_SN_VALUE_RESET_VALUE ( 0x0 )
26694
26695
26696 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_OFFSET ( 0x00000298 )
26697
26698 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_ADDRESS          ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_OFFSET )
26699 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_READ( r )        READ_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_ADDRESS ), (r) )
26700 #define IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_WRITE( v )       WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_SN_REG_3_ADDRESS ), (v) )
26701
26702 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26703 typedef struct
26704 {
26705         /* SN_RNRB */
26706         uint32_t sn_rnrb        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26707
26708         /* SN_RNRA */
26709         uint32_t sn_rnra        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26710 }
26711 __PACKING_ATTRIBUTE_STRUCT_END__
26712 IH_REGS_GENERAL_CONFIGURATION_SN_REG_3 ;
26713 #else
26714 typedef struct
26715 {
26716         /* SN_RNRA */
26717         uint32_t sn_rnra        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26718
26719         /* SN_RNRB */
26720         uint32_t sn_rnrb        : 16 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26721 }
26722 __PACKING_ATTRIBUTE_STRUCT_END__
26723 IH_REGS_GENERAL_CONFIGURATION_SN_REG_3 ;
26724 #endif
26725
26726 /*****************************************************************************************/
26727 /* LOCAL_MEM_RD_RQST_CFG                                                                 */
26728 /* Local Memory Read request register.    The read of one of 5 Local memories is used fo */
26729 /* r debug needs. We can actually print out all in-pipe Runner Buffers = (Packet Headers */
26730 /*  + Parser results + Look-up results: memory filling depends on pipe stage). The read  */
26731 /* is done by inderect way: user puts RAM number(0,1,2,3 or 4) & address of RAM (address */
26732 /*  space from 0x0 to 0x1F) and performs polling on BSY bit, while the BSY=0 -> read suc */
26733 /* ceeded and data is ready in registers LOCAL_MEM_RD_DATA_LOW/LOCAL_MEM_RD_DATA_HIGH    */
26734 /*****************************************************************************************/
26735
26736 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_BSY_NON_BUSY_VALUE             ( 0x0 )
26737 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_BSY_NON_BUSY_VALUE_RESET_VALUE ( 0x0 )
26738 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_BSY_BUSY_VALUE                 ( 0x1 )
26739 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_RSV_RSV_VALUE                                    ( 0x0 )
26740 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
26741 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_NUM_VALUE_VALUE                ( 0x0 )
26742 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_NUM_VALUE_VALUE_RESET_VALUE    ( 0x0 )
26743 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_ADDR_VALUE_VALUE               ( 0x0 )
26744 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_LOCAL_MEM_RD_RQST_ADDR_VALUE_VALUE_RESET_VALUE   ( 0x0 )
26745
26746
26747 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_OFFSET ( 0x0000029C )
26748
26749 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_OFFSET )
26750 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_ADDRESS ), (r) )
26751 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG_ADDRESS ), (v) )
26752
26753 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26754 typedef struct
26755 {
26756         /* LOCAL_MEM_RD_RQST_BSY */
26757         uint32_t local_mem_rd_rqst_bsy  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26758
26759         /* RSV */
26760         uint32_t rsv                    : 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26761
26762         /* LOCAL_MEM_RD_RQST_NUM */
26763         uint32_t local_mem_rd_rqst_num  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26764
26765         /* LOCAL_MEM_RD_RQST_ADDR */
26766         uint32_t local_mem_rd_rqst_addr : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26767 }
26768 __PACKING_ATTRIBUTE_STRUCT_END__
26769 IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG ;
26770 #else
26771 typedef struct
26772 {
26773         /* LOCAL_MEM_RD_RQST_ADDR */
26774         uint32_t local_mem_rd_rqst_addr : 5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26775
26776         /* LOCAL_MEM_RD_RQST_NUM */
26777         uint32_t local_mem_rd_rqst_num  : 3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26778
26779         /* RSV */
26780         uint32_t rsv                    : 23 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26781
26782         /* LOCAL_MEM_RD_RQST_BSY */
26783         uint32_t local_mem_rd_rqst_bsy  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26784 }
26785 __PACKING_ATTRIBUTE_STRUCT_END__
26786 IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG ;
26787 #endif
26788
26789 /*****************************************************************************************/
26790 /* LOCAL_MEM_RD_DATA_LOW                                                                 */
26791 /* Packet Header Memory Read data low [31:0]    The read of Packet Header memory is used */
26792 /*  for debug needs. We can actually print out all Ingress Buffers = (Packet Headers fil */
26793 /* ed by BBH/Runner to their slots). The read is done by inderect way: user puts address */
26794 /*  of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the B */
26795 /* SY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_DA */
26796 /* TA_HIGH                                                                               */
26797 /*****************************************************************************************/
26798
26799 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_DATA_VALUE_VALUE             ( 0x0 )
26800 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
26801
26802
26803 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_OFFSET ( 0x000002A0 )
26804
26805 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_OFFSET )
26806 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_ADDRESS ), (r) )
26807 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW_ADDRESS ), (v) )
26808
26809 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26810 typedef struct
26811 {
26812         /* DATA */
26813         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26814 }
26815 __PACKING_ATTRIBUTE_STRUCT_END__
26816 IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW ;
26817 #else
26818 typedef struct
26819 {
26820         /* DATA */
26821         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26822 }
26823 __PACKING_ATTRIBUTE_STRUCT_END__
26824 IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW ;
26825 #endif
26826
26827 /*****************************************************************************************/
26828 /* LOCAL_MEM_RD_DATA_HIGH                                                                */
26829 /* Packet Header Memory Read data high [63:32]    The read of Packet Header memory is us */
26830 /* ed for debug needs. We can actually print out all Ingress Buffers = (Packet Headers f */
26831 /* iled by BBH/Runner to their slots). The read is done by inderect way: user puts addre */
26832 /* ss of RAM (address space from 0x0 to 0xFF) and performs polling on BSY bit, while the */
26833 /*  BSY=0 -> read succeeded and data is ready in registers PH_MEM_RD_DATA_LOW/PH_MEM_RD_ */
26834 /* DATA_HIGH                                                                             */
26835 /*****************************************************************************************/
26836
26837 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE             ( 0x0 )
26838 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_DATA_VALUE_VALUE_RESET_VALUE ( 0x0 )
26839
26840
26841 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_OFFSET ( 0x000002A4 )
26842
26843 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_ADDRESS    ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_OFFSET )
26844 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_READ( r )  READ_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_ADDRESS ), (r) )
26845 #define IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_WRITE( v ) WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH_ADDRESS ), (v) )
26846
26847 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26848 typedef struct
26849 {
26850         /* DATA */
26851         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26852 }
26853 __PACKING_ATTRIBUTE_STRUCT_END__
26854 IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH ;
26855 #else
26856 typedef struct
26857 {
26858         /* DATA */
26859         uint32_t data   : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26860 }
26861 __PACKING_ATTRIBUTE_STRUCT_END__
26862 IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH ;
26863 #endif
26864
26865 /*****************************************************************************************/
26866 /* DBG_KEY1_LOW                                                                          */
26867 /* Serach Key1 low part [31:0]    The read of Search Key is used for debug needs. We can */
26868 /*  actually print out all generated key (according to key configs + parser results). Ke */
26869 /* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
26870 /*****************************************************************************************/
26871
26872 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
26873 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
26874
26875
26876 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_OFFSET ( 0x000002A8 )
26877
26878 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_OFFSET )
26879 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_ADDRESS ), (r) )
26880 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW_ADDRESS ), (v) )
26881
26882 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26883 typedef struct
26884 {
26885         /* KEY_VALUE */
26886         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26887 }
26888 __PACKING_ATTRIBUTE_STRUCT_END__
26889 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW ;
26890 #else
26891 typedef struct
26892 {
26893         /* KEY_VALUE */
26894         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26895 }
26896 __PACKING_ATTRIBUTE_STRUCT_END__
26897 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW ;
26898 #endif
26899
26900 /*****************************************************************************************/
26901 /* DBG_KEY1_HIGH                                                                         */
26902 /* Serach Key1 high part [63:32]    The read of Search Key is used for debug needs. We c */
26903 /* an actually print out all generated key (according to key configs + parser results).  */
26904 /* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
26905 /* H                                                                                     */
26906 /*****************************************************************************************/
26907
26908 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_RSV_RSV_VALUE                     ( 0x0 )
26909 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
26910 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
26911 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
26912
26913
26914 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_OFFSET ( 0x000002AC )
26915
26916 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_OFFSET )
26917 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_ADDRESS ), (r) )
26918 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH_ADDRESS ), (v) )
26919
26920 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26921 typedef struct
26922 {
26923         /* RSV */
26924         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26925
26926         /* KEY_VALUE */
26927         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26928 }
26929 __PACKING_ATTRIBUTE_STRUCT_END__
26930 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH ;
26931 #else
26932 typedef struct
26933 {
26934         /* KEY_VALUE */
26935         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26936
26937         /* RSV */
26938         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26939 }
26940 __PACKING_ATTRIBUTE_STRUCT_END__
26941 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH ;
26942 #endif
26943
26944 /*****************************************************************************************/
26945 /* DBG_KEY2_LOW                                                                          */
26946 /* Search Key2 low part [31:0]    The read of Search Key is used for debug needs. We can */
26947 /*  actually print out all generated key (according to key configs + parser results). Ke */
26948 /* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
26949 /*****************************************************************************************/
26950
26951 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
26952 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
26953
26954
26955 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_OFFSET ( 0x000002B0 )
26956
26957 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_OFFSET )
26958 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_ADDRESS ), (r) )
26959 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW_ADDRESS ), (v) )
26960
26961 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
26962 typedef struct
26963 {
26964         /* KEY_VALUE */
26965         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26966 }
26967 __PACKING_ATTRIBUTE_STRUCT_END__
26968 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW ;
26969 #else
26970 typedef struct
26971 {
26972         /* KEY_VALUE */
26973         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
26974 }
26975 __PACKING_ATTRIBUTE_STRUCT_END__
26976 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW ;
26977 #endif
26978
26979 /*****************************************************************************************/
26980 /* DBG_KEY2_HIGH                                                                         */
26981 /* Search Key2 high part [63:32]    The read of Search Key is used for debug needs. We c */
26982 /* an actually print out all generated key (according to key configs + parser results).  */
26983 /* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
26984 /* H                                                                                     */
26985 /*****************************************************************************************/
26986
26987 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_RSV_RSV_VALUE                     ( 0x0 )
26988 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
26989 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
26990 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
26991
26992
26993 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_OFFSET ( 0x000002B4 )
26994
26995 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_OFFSET )
26996 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_ADDRESS ), (r) )
26997 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH_ADDRESS ), (v) )
26998
26999 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27000 typedef struct
27001 {
27002         /* RSV */
27003         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27004
27005         /* KEY_VALUE */
27006         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27007 }
27008 __PACKING_ATTRIBUTE_STRUCT_END__
27009 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH ;
27010 #else
27011 typedef struct
27012 {
27013         /* KEY_VALUE */
27014         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27015
27016         /* RSV */
27017         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27018 }
27019 __PACKING_ATTRIBUTE_STRUCT_END__
27020 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH ;
27021 #endif
27022
27023 /*****************************************************************************************/
27024 /* DBG_KEY3_LOW                                                                          */
27025 /* Search Key3 low part [31:0]    The read of Search Key is used for debug needs. We can */
27026 /*  actually print out all generated key (according to key configs + parser results). Ke */
27027 /* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
27028 /*****************************************************************************************/
27029
27030 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
27031 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
27032
27033
27034 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_OFFSET ( 0x000002B8 )
27035
27036 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_OFFSET )
27037 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_ADDRESS ), (r) )
27038 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW_ADDRESS ), (v) )
27039
27040 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27041 typedef struct
27042 {
27043         /* KEY_VALUE */
27044         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27045 }
27046 __PACKING_ATTRIBUTE_STRUCT_END__
27047 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW ;
27048 #else
27049 typedef struct
27050 {
27051         /* KEY_VALUE */
27052         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27053 }
27054 __PACKING_ATTRIBUTE_STRUCT_END__
27055 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW ;
27056 #endif
27057
27058 /*****************************************************************************************/
27059 /* DBG_KEY3_HIGH                                                                         */
27060 /* Search Key3 high part [63:32]    The read of Search Key is used for debug needs. We c */
27061 /* an actually print out all generated key (according to key configs + parser results).  */
27062 /* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
27063 /* H                                                                                     */
27064 /*****************************************************************************************/
27065
27066 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_RSV_RSV_VALUE                     ( 0x0 )
27067 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
27068 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
27069 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
27070
27071
27072 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_OFFSET ( 0x000002BC )
27073
27074 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_OFFSET )
27075 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_ADDRESS ), (r) )
27076 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH_ADDRESS ), (v) )
27077
27078 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27079 typedef struct
27080 {
27081         /* RSV */
27082         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27083
27084         /* KEY_VALUE */
27085         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27086 }
27087 __PACKING_ATTRIBUTE_STRUCT_END__
27088 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH ;
27089 #else
27090 typedef struct
27091 {
27092         /* KEY_VALUE */
27093         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27094
27095         /* RSV */
27096         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27097 }
27098 __PACKING_ATTRIBUTE_STRUCT_END__
27099 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH ;
27100 #endif
27101
27102 /*****************************************************************************************/
27103 /* DBG_KEY4_LOW                                                                          */
27104 /* Search Key4 low part [31:0]    The read of Search Key is used for debug needs. We can */
27105 /*  actually print out all generated key (according to key configs + parser results). Ke */
27106 /* y of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIGH  */
27107 /*****************************************************************************************/
27108
27109 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_KEY_VALUE_VALUE_VALUE             ( 0x0 )
27110 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
27111
27112
27113 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_OFFSET ( 0x000002C0 )
27114
27115 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_ADDRESS      ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_OFFSET )
27116 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_READ( r )    READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_ADDRESS ), (r) )
27117 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_WRITE( v )   WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW_ADDRESS ), (v) )
27118
27119 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27120 typedef struct
27121 {
27122         /* KEY_VALUE */
27123         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27124 }
27125 __PACKING_ATTRIBUTE_STRUCT_END__
27126 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW ;
27127 #else
27128 typedef struct
27129 {
27130         /* KEY_VALUE */
27131         uint32_t key_value      : 32 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27132 }
27133 __PACKING_ATTRIBUTE_STRUCT_END__
27134 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW ;
27135 #endif
27136
27137 /*****************************************************************************************/
27138 /* DBG_KEY4_HIGH                                                                         */
27139 /* Search Key4 high part [63:32]    The read of Search Key is used for debug needs. We c */
27140 /* an actually print out all generated key (according to key configs + parser results).  */
27141 /* Key of appropriate search is located under two registers: DBG_KEYxx_LOW/DBG_KEYxx_HIG */
27142 /* H                                                                                     */
27143 /*****************************************************************************************/
27144
27145 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_RSV_RSV_VALUE                     ( 0x0 )
27146 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_RSV_RSV_VALUE_RESET_VALUE         ( 0x0 )
27147 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_KEY_VALUE_VALUE_VALUE             ( 0x0 )
27148 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_KEY_VALUE_VALUE_VALUE_RESET_VALUE ( 0x0 )
27149
27150
27151 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_OFFSET ( 0x000002C4 )
27152
27153 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_OFFSET )
27154 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_ADDRESS ), (r) )
27155 #define IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH_ADDRESS ), (v) )
27156
27157 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27158 typedef struct
27159 {
27160         /* RSV */
27161         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27162
27163         /* KEY_VALUE */
27164         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27165 }
27166 __PACKING_ATTRIBUTE_STRUCT_END__
27167 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH ;
27168 #else
27169 typedef struct
27170 {
27171         /* KEY_VALUE */
27172         uint32_t key_value      : 28 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27173
27174         /* RSV */
27175         uint32_t rsv            : 4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27176 }
27177 __PACKING_ATTRIBUTE_STRUCT_END__
27178 IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH ;
27179 #endif
27180
27181 /*****************************************************************************************/
27182 /* DBG_IQ_STAT                                                                           */
27183 /* Status debug register for Ingress Queue    Ingress Queue status is used for debug nee */
27184 /* ds. We can actually print out several status, like Main IQ FIFO statuses, local RAM o */
27185 /* ccupancy status, each ingress queue status                                            */
27186 /*****************************************************************************************/
27187
27188 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV2_RSV_VALUE                                 ( 0x0 )
27189 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV2_RSV_VALUE_RESET_VALUE                     ( 0x0 )
27190 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27191 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27192 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27193 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27194 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27195 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27196 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27197 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27198 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27199 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27200 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27201 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27202 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27203 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27204 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27205 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27206 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27207 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27208 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27209 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27210 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27211 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_FULL_NON_FULL_VALUE                   ( 0x0 )
27212 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_FULL_NON_FULL_VALUE_RESET_VALUE       ( 0x0 )
27213 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_FULL_FULL_VALUE                       ( 0x1 )
27214 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27215 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27216 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ7_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27217 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27218 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27219 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ6_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27220 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27221 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27222 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ5_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27223 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27224 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27225 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ4_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27226 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27227 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27228 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ3_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27229 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27230 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27231 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ2_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27232 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27233 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27234 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ1_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27235 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_EMPTY_NON_EMPTY_VALUE                 ( 0x0 )
27236 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_EMPTY_EMPTY_VALUE                     ( 0x1 )
27237 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ0_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE         ( 0x1 )
27238 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_FULL_NOT_FULL_VALUE                    ( 0x0 )
27239 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE        ( 0x0 )
27240 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_FULL_FULL_VALUE                        ( 0x1 )
27241 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_EMPTY_NON_EMPTY_VALUE                  ( 0x0 )
27242 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_EMPTY_EMPTY_VALUE                      ( 0x1 )
27243 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_IQ_FIFO_EMPTY_EMPTY_VALUE_RESET_VALUE          ( 0x1 )
27244 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV_RSV_VALUE                                  ( 0x0 )
27245 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_RSV_RSV_VALUE_RESET_VALUE                      ( 0x0 )
27246 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM4_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
27247 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM4_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
27248 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM4_STTS_OCCUPIED_VALUE                 ( 0x1 )
27249 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM3_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
27250 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM3_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
27251 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM3_STTS_OCCUPIED_VALUE                 ( 0x1 )
27252 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM2_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
27253 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM2_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
27254 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM2_STTS_OCCUPIED_VALUE                 ( 0x1 )
27255 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM1_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
27256 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM1_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
27257 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM1_STTS_OCCUPIED_VALUE                 ( 0x1 )
27258 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM0_STTS_NON_OCCUPIED_VALUE             ( 0x0 )
27259 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM0_STTS_NON_OCCUPIED_VALUE_RESET_VALUE ( 0x0 )
27260 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_LOCAL_RAM0_STTS_OCCUPIED_VALUE                 ( 0x1 )
27261
27262
27263 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_OFFSET ( 0x000002C8 )
27264
27265 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_ADDRESS       ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_OFFSET )
27266 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_READ( r )     READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_ADDRESS ), (r) )
27267 #define IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_WRITE( v )    WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT_ADDRESS ), (v) )
27268
27269 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27270 typedef struct
27271 {
27272         /* RSV2 */
27273         uint32_t rsv2                   : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27274
27275         /* IQ7_FIFO_FULL */
27276         uint32_t iq7_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27277
27278         /* IQ6_FIFO_FULL */
27279         uint32_t iq6_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27280
27281         /* IQ5_FIFO_FULL */
27282         uint32_t iq5_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27283
27284         /* IQ4_FIFO_FULL */
27285         uint32_t iq4_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27286
27287         /* IQ3_FIFO_FULL */
27288         uint32_t iq3_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27289
27290         /* IQ2_FIFO_FULL */
27291         uint32_t iq2_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27292
27293         /* IQ1_FIFO_FULL */
27294         uint32_t iq1_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27295
27296         /* IQ0_FIFO_FULL */
27297         uint32_t iq0_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27298
27299         /* IQ7_FIFO_EMPTY */
27300         uint32_t iq7_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27301
27302         /* IQ6_FIFO_EMPTY */
27303         uint32_t iq6_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27304
27305         /* IQ5_FIFO_EMPTY */
27306         uint32_t iq5_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27307
27308         /* IQ4_FIFO_EMPTY */
27309         uint32_t iq4_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27310
27311         /* IQ3_FIFO_EMPTY */
27312         uint32_t iq3_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27313
27314         /* IQ2_FIFO_EMPTY */
27315         uint32_t iq2_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27316
27317         /* IQ1_FIFO_EMPTY */
27318         uint32_t iq1_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27319
27320         /* IQ0_FIFO_EMPTY */
27321         uint32_t iq0_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27322
27323         /* IQ_FIFO_FULL */
27324         uint32_t iq_fifo_full           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27325
27326         /* IQ_FIFO_EMPTY */
27327         uint32_t iq_fifo_empty          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27328
27329         /* RSV */
27330         uint32_t rsv                    : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27331
27332         /* Local_ram4_stts */
27333         uint32_t local_ram4_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27334
27335         /* Local_ram3_stts */
27336         uint32_t local_ram3_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27337
27338         /* Local_ram2_stts */
27339         uint32_t local_ram2_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27340
27341         /* Local_ram1_stts */
27342         uint32_t local_ram1_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27343
27344         /* Local_ram0_stts */
27345         uint32_t local_ram0_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27346 }
27347 __PACKING_ATTRIBUTE_STRUCT_END__
27348 IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT ;
27349 #else
27350 typedef struct
27351 {
27352         /* Local_ram0_stts */
27353         uint32_t local_ram0_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27354
27355         /* Local_ram1_stts */
27356         uint32_t local_ram1_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27357
27358         /* Local_ram2_stts */
27359         uint32_t local_ram2_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27360
27361         /* Local_ram3_stts */
27362         uint32_t local_ram3_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27363
27364         /* Local_ram4_stts */
27365         uint32_t local_ram4_stts        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27366
27367         /* RSV */
27368         uint32_t rsv                    : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27369
27370         /* IQ_FIFO_EMPTY */
27371         uint32_t iq_fifo_empty          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27372
27373         /* IQ_FIFO_FULL */
27374         uint32_t iq_fifo_full           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27375
27376         /* IQ0_FIFO_EMPTY */
27377         uint32_t iq0_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27378
27379         /* IQ1_FIFO_EMPTY */
27380         uint32_t iq1_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27381
27382         /* IQ2_FIFO_EMPTY */
27383         uint32_t iq2_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27384
27385         /* IQ3_FIFO_EMPTY */
27386         uint32_t iq3_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27387
27388         /* IQ4_FIFO_EMPTY */
27389         uint32_t iq4_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27390
27391         /* IQ5_FIFO_EMPTY */
27392         uint32_t iq5_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27393
27394         /* IQ6_FIFO_EMPTY */
27395         uint32_t iq6_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27396
27397         /* IQ7_FIFO_EMPTY */
27398         uint32_t iq7_fifo_empty         : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27399
27400         /* IQ0_FIFO_FULL */
27401         uint32_t iq0_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27402
27403         /* IQ1_FIFO_FULL */
27404         uint32_t iq1_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27405
27406         /* IQ2_FIFO_FULL */
27407         uint32_t iq2_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27408
27409         /* IQ3_FIFO_FULL */
27410         uint32_t iq3_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27411
27412         /* IQ4_FIFO_FULL */
27413         uint32_t iq4_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27414
27415         /* IQ5_FIFO_FULL */
27416         uint32_t iq5_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27417
27418         /* IQ6_FIFO_FULL */
27419         uint32_t iq6_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27420
27421         /* IQ7_FIFO_FULL */
27422         uint32_t iq7_fifo_full          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27423
27424         /* RSV2 */
27425         uint32_t rsv2                   : 8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27426 }
27427 __PACKING_ATTRIBUTE_STRUCT_END__
27428 IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT ;
27429 #endif
27430
27431 /*****************************************************************************************/
27432 /* DBG_RBOUT_SEL                                                                         */
27433 /* Debug Runner Buffer output selection                                                  */
27434 /*****************************************************************************************/
27435
27436 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_RSV_RSV_VALUE                                  ( 0x0 )
27437 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_RSV_RSV_VALUE_RESET_VALUE                      ( 0x0 )
27438 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_SHRTPKT_OUT_DISABLE_VALUE                  ( 0x0 )
27439 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_SHRTPKT_OUT_DISABLE_VALUE_RESET_VALUE      ( 0x0 )
27440 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_SHRTPKT_OUT_ENABLE_VALUE                   ( 0x1 )
27441 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_BAC_BBHCLASS_OUT_DISABLE_VALUE             ( 0x0 )
27442 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_BAC_BBHCLASS_OUT_DISABLE_VALUE_RESET_VALUE ( 0x0 )
27443 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_BAC_BBHCLASS_OUT_ENABLE_VALUE              ( 0x1 )
27444 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY4_OUT_DISABLE_VALUE                     ( 0x0 )
27445 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY4_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
27446 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY4_OUT_ENABLE_VALUE                      ( 0x1 )
27447 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY3_OUT_DISABLE_VALUE                     ( 0x0 )
27448 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY3_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
27449 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY3_OUT_ENABLE_VALUE                      ( 0x1 )
27450 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY2_OUT_DISABLE_VALUE                     ( 0x0 )
27451 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY2_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
27452 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY2_OUT_ENABLE_VALUE                      ( 0x1 )
27453 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY1_OUT_DISABLE_VALUE                     ( 0x0 )
27454 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY1_OUT_DISABLE_VALUE_RESET_VALUE         ( 0x0 )
27455 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_DBG_KEY1_OUT_ENABLE_VALUE                      ( 0x1 )
27456
27457
27458 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_OFFSET ( 0x000002CC )
27459
27460 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_ADDRESS     ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_OFFSET )
27461 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_READ( r )   READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_ADDRESS ), (r) )
27462 #define IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_WRITE( v )  WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL_ADDRESS ), (v) )
27463
27464 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27465 typedef struct
27466 {
27467         /* RSV */
27468         uint32_t rsv                    : 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27469
27470         /* DBG_SHRTPKT_OUT */
27471         uint32_t dbg_shrtpkt_out        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27472
27473         /* DBG_BAC_ORGCLASS_OUT */
27474         uint32_t dbg_bac_bbhclass_out   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27475
27476         /* DBG_KEY4_OUT */
27477         uint32_t dbg_key4_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27478
27479         /* DBG_KEY3_OUT */
27480         uint32_t dbg_key3_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27481
27482         /* DBG_KEY2_OUT */
27483         uint32_t dbg_key2_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27484
27485         /* DBG_KEY1_OUT */
27486         uint32_t dbg_key1_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27487 }
27488 __PACKING_ATTRIBUTE_STRUCT_END__
27489 IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL ;
27490 #else
27491 typedef struct
27492 {
27493         /* DBG_KEY1_OUT */
27494         uint32_t dbg_key1_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27495
27496         /* DBG_KEY2_OUT */
27497         uint32_t dbg_key2_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27498
27499         /* DBG_KEY3_OUT */
27500         uint32_t dbg_key3_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27501
27502         /* DBG_KEY4_OUT */
27503         uint32_t dbg_key4_out           : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27504
27505         /* DBG_BAC_ORGCLASS_OUT */
27506         uint32_t dbg_bac_bbhclass_out   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27507
27508         /* DBG_SHRTPKT_OUT */
27509         uint32_t dbg_shrtpkt_out        : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27510
27511         /* RSV */
27512         uint32_t rsv                    : 26 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27513 }
27514 __PACKING_ATTRIBUTE_STRUCT_END__
27515 IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL ;
27516 #endif
27517
27518 /*****************************************************************************************/
27519 /* DBG_CRITICAL_STAT                                                                     */
27520 /* Status/alarm register, which includes indicators of system failures: like stuck in lo */
27521 /* ok-up procedure, egress FIFO full, etc.                                               */
27522 /*****************************************************************************************/
27523
27524 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_RSV_RSV_VALUE                                    ( 0x0 )
27525 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_RSV_RSV_VALUE_RESET_VALUE                        ( 0x0 )
27526 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE              ( 0x0 )
27527 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE  ( 0x0 )
27528 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_PKT_CMD_FIFO_FULL_FULL_VALUE                  ( 0x1 )
27529 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_MSGTX_FIFO_FULL_NOT_FULL_VALUE                ( 0x0 )
27530 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_MSGTX_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE    ( 0x0 )
27531 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_MSGTX_FIFO_FULL_FULL_VALUE                    ( 0x1 )
27532 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_DATATX_FIFO_FULL_NOT_FULL_VALUE               ( 0x0 )
27533 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_DATATX_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE   ( 0x0 )
27534 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_EQ_DATATX_FIFO_FULL_FULL_VALUE                   ( 0x1 )
27535 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LUT_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE             ( 0x0 )
27536 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LUT_PKT_CMD_FIFO_FULL_NOT_FULL_VALUE_RESET_VALUE ( 0x0 )
27537 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LUT_PKT_CMD_FIFO_FULL_FULL_VALUE                 ( 0x1 )
27538 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP4_STUCK_N_STUCK_VALUE                        ( 0x0 )
27539 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP4_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
27540 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP4_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
27541 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP3_STUCK_N_STUCK_VALUE                        ( 0x0 )
27542 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP3_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
27543 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP3_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
27544 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP2_STUCK_N_STUCK_VALUE                        ( 0x0 )
27545 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP2_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
27546 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP2_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
27547 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP1_STUCK_N_STUCK_VALUE                        ( 0x0 )
27548 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP1_STUCK_N_NOT_STUCK_VALUE                    ( 0x1 )
27549 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_LKUP1_STUCK_N_NOT_STUCK_VALUE_RESET_VALUE        ( 0x1 )
27550
27551
27552 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_OFFSET ( 0x000002D0 )
27553
27554 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_ADDRESS         ( IH_REGS_GENERAL_CONFIGURATION_ADDRESS + IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_OFFSET )
27555 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_READ( r )       READ_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_ADDRESS ), (r) )
27556 #define IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_WRITE( v )      WRITE_32( ( IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT_ADDRESS ), (v) )
27557
27558 #ifndef _BYTE_ORDER_LITTLE_ENDIAN_
27559 typedef struct
27560 {
27561         /* RSV */
27562         uint32_t rsv                    : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27563
27564         /* EQ_PKT_CMD_FIFO_FULL */
27565         uint32_t eq_pkt_cmd_fifo_full   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27566
27567         /* EQ_MSGTX_FIFO_FULL */
27568         uint32_t eq_msgtx_fifo_full     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27569
27570         /* EQ_DATATX_FIFO_FULL */
27571         uint32_t eq_datatx_fifo_full    : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27572
27573         /* LUT_PKT_CMD_FIFO_FULL */
27574         uint32_t lut_pkt_cmd_fifo_full  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27575
27576         /* LKUP4_STUCK_N */
27577         uint32_t lkup4_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27578
27579         /* LKUP3_STUCK_N */
27580         uint32_t lkup3_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27581
27582         /* LKUP2_STUCK_N */
27583         uint32_t lkup2_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27584
27585         /* LKUP1_STUCK_N */
27586         uint32_t lkup1_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27587 }
27588 __PACKING_ATTRIBUTE_STRUCT_END__
27589 IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT ;
27590 #else
27591 typedef struct
27592 {
27593         /* LKUP1_STUCK_N */
27594         uint32_t lkup1_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27595
27596         /* LKUP2_STUCK_N */
27597         uint32_t lkup2_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27598
27599         /* LKUP3_STUCK_N */
27600         uint32_t lkup3_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27601
27602         /* LKUP4_STUCK_N */
27603         uint32_t lkup4_stuck_n          : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27604
27605         /* LUT_PKT_CMD_FIFO_FULL */
27606         uint32_t lut_pkt_cmd_fifo_full  : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27607
27608         /* EQ_DATATX_FIFO_FULL */
27609         uint32_t eq_datatx_fifo_full    : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27610
27611         /* EQ_MSGTX_FIFO_FULL */
27612         uint32_t eq_msgtx_fifo_full     : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27613
27614         /* EQ_PKT_CMD_FIFO_FULL */
27615         uint32_t eq_pkt_cmd_fifo_full   : 1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27616
27617         /* RSV */
27618         uint32_t rsv                    : 24 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27619 }
27620 __PACKING_ATTRIBUTE_STRUCT_END__
27621 IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT ;
27622 #endif
27623
27624 typedef struct
27625 {
27626         /* LKUP_TBL0_LUT_CFG */
27627         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CFG lkup_tbl0_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27628
27629         /* LKUP_TBL1_LUT_CFG */
27630         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CFG lkup_tbl1_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27631
27632         /* LKUP_TBL2_LUT_CFG */
27633         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CFG lkup_tbl2_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27634
27635         /* LKUP_TBL3_LUT_CFG */
27636         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CFG lkup_tbl3_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27637
27638         /* LKUP_TBL4_LUT_CFG */
27639         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CFG lkup_tbl4_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27640
27641         /* LKUP_TBL5_LUT_CFG */
27642         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CFG lkup_tbl5_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27643
27644         /* LKUP_TBL6_LUT_CFG */
27645         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CFG lkup_tbl6_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27646
27647         /* LKUP_TBL7_LUT_CFG */
27648         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CFG lkup_tbl7_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27649
27650         /* LKUP_TBL8_LUT_CFG */
27651         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CFG lkup_tbl8_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27652
27653         /* LKUP_TBL9_LUT_CFG */
27654         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CFG lkup_tbl9_lut_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27655
27656         /* LKUP_TBL0_CAM_CFG */
27657         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CFG lkup_tbl0_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27658
27659         /* LKUP_TBL1_CAM_CFG */
27660         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CFG lkup_tbl1_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27661
27662         /* LKUP_TBL2_CAM_CFG */
27663         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CFG lkup_tbl2_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27664
27665         /* LKUP_TBL3_CAM_CFG */
27666         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CFG lkup_tbl3_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27667
27668         /* LKUP_TBL4_CAM_CFG */
27669         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CFG lkup_tbl4_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27670
27671         /* LKUP_TBL5_CAM_CFG */
27672         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CFG lkup_tbl5_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27673
27674         /* LKUP_TBL6_CAM_CFG */
27675         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CFG lkup_tbl6_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27676
27677         /* LKUP_TBL7_CAM_CFG */
27678         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CFG lkup_tbl7_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27679
27680         /* LKUP_TBL8_CAM_CFG */
27681         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CFG lkup_tbl8_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27682
27683         /* LKUP_TBL9_CAM_CFG */
27684         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CFG lkup_tbl9_cam_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27685
27686         /* LKUP_TBL0_LUT_CNXT_CFG */
27687         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_LUT_CNXT_CFG lkup_tbl0_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27688
27689         /* LKUP_TBL1_LUT_CNXT_CFG */
27690         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_LUT_CNXT_CFG lkup_tbl1_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27691
27692         /* LKUP_TBL2_LUT_CNXT_CFG */
27693         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_LUT_CNXT_CFG lkup_tbl2_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27694
27695         /* LKUP_TBL3_LUT_CNXT_CFG */
27696         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_LUT_CNXT_CFG lkup_tbl3_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27697
27698         /* LKUP_TBL4_LUT_CNXT_CFG */
27699         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_LUT_CNXT_CFG lkup_tbl4_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27700
27701         /* LKUP_TBL5_LUT_CNXT_CFG */
27702         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_LUT_CNXT_CFG lkup_tbl5_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27703
27704         /* LKUP_TBL6_LUT_CNXT_CFG */
27705         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_LUT_CNXT_CFG lkup_tbl6_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27706
27707         /* LKUP_TBL7_LUT_CNXT_CFG */
27708         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_LUT_CNXT_CFG lkup_tbl7_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27709
27710         /* LKUP_TBL8_LUT_CNXT_CFG */
27711         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_LUT_CNXT_CFG lkup_tbl8_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27712
27713         /* LKUP_TBL9_LUT_CNXT_CFG */
27714         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_LUT_CNXT_CFG lkup_tbl9_lut_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27715
27716         /* Reserved */
27717         uint8_t reserved1 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27718
27719         /* LKUP_TBL0_CAM_CNXT_CFG */
27720         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_CAM_CNXT_CFG lkup_tbl0_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27721
27722         /* LKUP_TBL1_CAM_CNXT_CFG */
27723         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_CAM_CNXT_CFG lkup_tbl1_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27724
27725         /* LKUP_TBL2_CAM_CNXT_CFG */
27726         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_CAM_CNXT_CFG lkup_tbl2_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27727
27728         /* LKUP_TBL3_CAM_CNXT_CFG */
27729         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_CAM_CNXT_CFG lkup_tbl3_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27730
27731         /* LKUP_TBL4_CAM_CNXT_CFG */
27732         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_CAM_CNXT_CFG lkup_tbl4_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27733
27734         /* LKUP_TBL5_CAM_CNXT_CFG */
27735         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_CAM_CNXT_CFG lkup_tbl5_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27736
27737         /* LKUP_TBL6_CAM_CNXT_CFG */
27738         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_CAM_CNXT_CFG lkup_tbl6_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27739
27740         /* LKUP_TBL7_CAM_CNXT_CFG */
27741         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_CAM_CNXT_CFG lkup_tbl7_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27742
27743         /* LKUP_TBL8_CAM_CNXT_CFG */
27744         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_CAM_CNXT_CFG lkup_tbl8_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27745
27746         /* Reserved */
27747         uint8_t reserved2 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27748
27749         /* LKUP_TBL9_CAM_CNXT_CFG */
27750         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_CAM_CNXT_CFG lkup_tbl9_cam_cnxt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27751
27752         /* LKUP_TBL0_KEY_CFG */
27753         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_CFG lkup_tbl0_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27754
27755         /* LKUP_TBL0_KEY_P0_MASKL */
27756         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKL lkup_tbl0_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27757
27758         /* LKUP_TBL0_KEY_P0_MASKH */
27759         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P0_MASKH lkup_tbl0_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27760
27761         /* LKUP_TBL0_KEY_P1_MASKL */
27762         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKL lkup_tbl0_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27763
27764         /* LKUP_TBL0_KEY_P1_MASKH */
27765         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_KEY_P1_MASKH lkup_tbl0_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27766
27767         /* LKUP_TBL1_KEY_CFG */
27768         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_CFG lkup_tbl1_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27769
27770         /* LKUP_TBL1_KEY_P0_MASKL */
27771         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKL lkup_tbl1_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27772
27773         /* LKUP_TBL1_KEY_P0_MASKH */
27774         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P0_MASKH lkup_tbl1_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27775
27776         /* LKUP_TBL1_KEY_P1_MASKL */
27777         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKL lkup_tbl1_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27778
27779         /* LKUP_TBL1_KEY_P1_MASKH */
27780         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_KEY_P1_MASKH lkup_tbl1_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27781
27782         /* LKUP_TBL2_KEY_CFG */
27783         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_CFG lkup_tbl2_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27784
27785         /* LKUP_TBL2_KEY_P0_MASKL */
27786         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKL lkup_tbl2_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27787
27788         /* LKUP_TBL2_KEY_P0_MASKH */
27789         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P0_MASKH lkup_tbl2_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27790
27791         /* LKUP_TBL2_KEY_P1_MASKL */
27792         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKL lkup_tbl2_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27793
27794         /* LKUP_TBL2_KEY_P1_MASKH */
27795         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_KEY_P1_MASKH lkup_tbl2_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27796
27797         /* LKUP_TBL3_KEY_CFG */
27798         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_CFG lkup_tbl3_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27799
27800         /* LKUP_TBL3_KEY_P0_MASKL */
27801         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKL lkup_tbl3_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27802
27803         /* LKUP_TBL3_KEY_P0_MASKH */
27804         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P0_MASKH lkup_tbl3_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27805
27806         /* LKUP_TBL3_KEY_P1_MASKL */
27807         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKL lkup_tbl3_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27808
27809         /* LKUP_TBL3_KEY_P1_MASKH */
27810         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_KEY_P1_MASKH lkup_tbl3_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27811
27812         /* LKUP_TBL4_KEY_CFG */
27813         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_CFG lkup_tbl4_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27814
27815         /* LKUP_TBL4_KEY_P0_MASKL */
27816         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKL lkup_tbl4_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27817
27818         /* LKUP_TBL4_KEY_P0_MASKH */
27819         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P0_MASKH lkup_tbl4_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27820
27821         /* LKUP_TBL4_KEY_P1_MASKL */
27822         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKL lkup_tbl4_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27823
27824         /* LKUP_TBL4_KEY_P1_MASKH */
27825         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_KEY_P1_MASKH lkup_tbl4_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27826
27827         /* LKUP_TBL5_KEY_CFG */
27828         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_CFG lkup_tbl5_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27829
27830         /* LKUP_TBL5_KEY_P0_MASKL */
27831         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKL lkup_tbl5_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27832
27833         /* LKUP_TBL5_KEY_P0_MASKH */
27834         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P0_MASKH lkup_tbl5_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27835
27836         /* LKUP_TBL5_KEY_P1_MASKL */
27837         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKL lkup_tbl5_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27838
27839         /* LKUP_TBL5_KEY_P1_MASKH */
27840         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_KEY_P1_MASKH lkup_tbl5_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27841
27842         /* LKUP_TBL6_KEY_CFG */
27843         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_CFG lkup_tbl6_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27844
27845         /* LKUP_TBL6_KEY_P0_MASKL */
27846         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKL lkup_tbl6_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27847
27848         /* LKUP_TBL6_KEY_P0_MASKH */
27849         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P0_MASKH lkup_tbl6_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27850
27851         /* LKUP_TBL6_KEY_P1_MASKL */
27852         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKL lkup_tbl6_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27853
27854         /* LKUP_TBL6_KEY_P1_MASKH */
27855         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_KEY_P1_MASKH lkup_tbl6_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27856
27857         /* LKUP_TBL7_KEY_CFG */
27858         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_CFG lkup_tbl7_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27859
27860         /* LKUP_TBL7_KEY_P0_MASKL */
27861         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKL lkup_tbl7_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27862
27863         /* LKUP_TBL7_KEY_P0_MASKH */
27864         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P0_MASKH lkup_tbl7_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27865
27866         /* LKUP_TBL7_KEY_P1_MASKL */
27867         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKL lkup_tbl7_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27868
27869         /* Reserved */
27870         uint8_t reserved3 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27871
27872         /* LKUP_TBL7_KEY_P1_MASKH */
27873         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_KEY_P1_MASKH lkup_tbl7_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27874
27875         /* LKUP_TBL8_KEY_CFG */
27876         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_CFG lkup_tbl8_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27877
27878         /* LKUP_TBL8_KEY_P0_MASKL */
27879         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKL lkup_tbl8_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27880
27881         /* LKUP_TBL8_KEY_P0_MASKH */
27882         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P0_MASKH lkup_tbl8_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27883
27884         /* LKUP_TBL8_KEY_P1_MASKL */
27885         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKL lkup_tbl8_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27886
27887         /* LKUP_TBL8_KEY_P1_MASKH */
27888         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_KEY_P1_MASKH lkup_tbl8_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27889
27890         /* LKUP_TBL9_KEY_CFG */
27891         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_CFG lkup_tbl9_key_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27892
27893         /* LKUP_TBL9_KEY_P0_MASKL */
27894         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKL lkup_tbl9_key_p0_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27895
27896         /* LKUP_TBL9_KEY_P0_MASKH */
27897         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P0_MASKH lkup_tbl9_key_p0_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27898
27899         /* LKUP_TBL9_KEY_P1_MASKL */
27900         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKL lkup_tbl9_key_p1_maskl __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27901
27902         /* LKUP_TBL9_KEY_P1_MASKH */
27903         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_KEY_P1_MASKH lkup_tbl9_key_p1_maskh __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27904
27905         /* LKUP_TBL0_GL_MASK */
27906         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL0_GL_MASK lkup_tbl0_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27907
27908         /* LKUP_TBL1_GL_MASK */
27909         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL1_GL_MASK lkup_tbl1_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27910
27911         /* LKUP_TBL2_GL_MASK */
27912         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL2_GL_MASK lkup_tbl2_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27913
27914         /* LKUP_TBL3_GL_MASK */
27915         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL3_GL_MASK lkup_tbl3_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27916
27917         /* LKUP_TBL4_GL_MASK */
27918         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL4_GL_MASK lkup_tbl4_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27919
27920         /* LKUP_TBL5_GL_MASK */
27921         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL5_GL_MASK lkup_tbl5_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27922
27923         /* LKUP_TBL6_GL_MASK */
27924         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL6_GL_MASK lkup_tbl6_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27925
27926         /* LKUP_TBL7_GL_MASK */
27927         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL7_GL_MASK lkup_tbl7_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27928
27929         /* LKUP_TBL8_GL_MASK */
27930         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL8_GL_MASK lkup_tbl8_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27931
27932         /* LKUP_TBL9_GL_MASK */
27933         IH_REGS_LOOKUP_CONFIGURATION_LKUP_TBL9_GL_MASK lkup_tbl9_gl_mask __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27934 }
27935  __PACKING_ATTRIBUTE_STRUCT_END__
27936 IH_REGS_LOOKUP_CONFIGURATION ;
27937
27938 typedef struct
27939 {
27940         /* DA_FILT0_VAL_L */
27941         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_VAL_L da_filt0_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27942
27943         /* DA_FILT0_MASK_L */
27944         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_MASK_L da_filt0_mask_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27945
27946         /* DA_FILT0_CFG_H */
27947         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT0_CFG_H da_filt0_cfg_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27948
27949         /* PARSER_CFG */
27950         IH_REGS_PARSER_CORE_CONFIGURATION_PARSER_CFG parser_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27951
27952         /* QTAG_Ethertype */
27953         IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_ETHTYPE qtag_ethtype __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27954
27955         /* QTAG_Nesting */
27956         IH_REGS_PARSER_CORE_CONFIGURATION_QTAG_NEST qtag_nest __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27957
27958         /* Snap_organization_code */
27959         IH_REGS_PARSER_CORE_CONFIGURATION_SNAP_ORG_CODE snap_org_code __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27960
27961         /* User_Ethertype_configurtion_0_1 */
27962         IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_0_1 user_ethtype_0_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27963
27964         /* User_Ethertype_configurtion_2_3 */
27965         IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_2_3 user_ethtype_2_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27966
27967         /* User_Ethertype_Configuration */
27968         IH_REGS_PARSER_CORE_CONFIGURATION_USER_ETHTYPE_CONFIG user_ethtype_config __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27969
27970         /* VID_Configuration_0_1 */
27971         IH_REGS_PARSER_CORE_CONFIGURATION_VID_0_1 vid_0_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27972
27973         /* VID_Configuration_2_3 */
27974         IH_REGS_PARSER_CORE_CONFIGURATION_VID_2_3 vid_2_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27975
27976         /* VID_Configuration_4_5 */
27977         IH_REGS_PARSER_CORE_CONFIGURATION_VID_4_5 vid_4_5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27978
27979         /* VID_Configuration_6_7 */
27980         IH_REGS_PARSER_CORE_CONFIGURATION_VID_6_7 vid_6_7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27981
27982         /* VID_Configuration_8_9 */
27983         IH_REGS_PARSER_CORE_CONFIGURATION_VID_8_9 vid_8_9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27984
27985         /* VID_Configuration_10_11 */
27986         IH_REGS_PARSER_CORE_CONFIGURATION_VID_10_11 vid_10_11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27987
27988         /* User_defined_IP_Protocl */
27989         IH_REGS_PARSER_CORE_CONFIGURATION_USER_IP_PROT user_ip_prot __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27990
27991         /* PPP_IP_Protocol_Code */
27992         IH_REGS_PARSER_CORE_CONFIGURATION_PPP_IP_PROT_CODE ppp_ip_prot_code __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27993
27994         /* IP_FILTER0_CFG */
27995         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_CFG ip_filter0_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27996
27997         /* IP_FILTER1_CFG */
27998         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_CFG ip_filter1_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
27999
28000         /* IP_FILTER2_CFG */
28001         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_CFG ip_filter2_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28002
28003         /* IP_FILTER3_CFG */
28004         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_CFG ip_filter3_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28005
28006         /* DA_FILT1_VAL_L */
28007         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_VAL_L da_filt1_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28008
28009         /* DA_FILT1_MASK_L */
28010         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_MASK_L da_filt1_mask_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28011
28012         /* DA_FILT1_CFG_H */
28013         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT1_CFG_H da_filt1_cfg_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28014
28015         /* DA_FILT2_VAL_L */
28016         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_L da_filt2_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28017
28018         /* DA_FILT2_VAL_H */
28019         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT2_VAL_H da_filt2_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28020
28021         /* DA_FILT3_VAL_L */
28022         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_L da_filt3_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28023
28024         /* DA_FILT3_VAL_H */
28025         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT3_VAL_H da_filt3_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28026
28027         /* DA_FILT4_VAL_L */
28028         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_L da_filt4_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28029
28030         /* DA_FILT4_VAL_H */
28031         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT4_VAL_H da_filt4_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28032
28033         /* DA_FILT5_VAL_L */
28034         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_L da_filt5_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28035
28036         /* DA_FILT5_VAL_H */
28037         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT5_VAL_H da_filt5_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28038
28039         /* DA_FILT_VALID_CFG */
28040         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT_VALID_CFG da_filt_valid_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28041
28042         /* IP_FILTER0_MASK_CFG */
28043         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER0_MASK_CFG ip_filter0_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28044
28045         /* IP_FILTER1_MASK_CFG */
28046         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER1_MASK_CFG ip_filter1_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28047
28048         /* IP_FILTER2_MASK_CFG */
28049         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER2_MASK_CFG ip_filter2_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28050
28051         /* IP_FILTER3_MASK_CFG */
28052         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTER3_MASK_CFG ip_filter3_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28053
28054         /* IP_FILTERS_CFG */
28055         IH_REGS_PARSER_CORE_CONFIGURATION_IP_FILTERS_CFG ip_filters_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28056
28057         /* GRE_PROTOCOL_CFG */
28058         IH_REGS_PARSER_CORE_CONFIGURATION_GRE_PROTOCOL_CFG gre_protocol_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28059
28060         /* Reserved */
28061         uint8_t reserved1 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28062
28063         /* DSCP2TCI_TBL0_R0 */
28064         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R0 dscp2tci_tbl0_r0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28065
28066         /* DSCP2TCI_TBL0_R1 */
28067         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R1 dscp2tci_tbl0_r1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28068
28069         /* DSCP2TCI_TBL0_R2 */
28070         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R2 dscp2tci_tbl0_r2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28071
28072         /* DSCP2TCI_TBL0_R3 */
28073         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R3 dscp2tci_tbl0_r3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28074
28075         /* DSCP2TCI_TBL0_R4 */
28076         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R4 dscp2tci_tbl0_r4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28077
28078         /* DSCP2TCI_TBL0_R5 */
28079         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R5 dscp2tci_tbl0_r5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28080
28081         /* DSCP2TCI_TBL0_R6 */
28082         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R6 dscp2tci_tbl0_r6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28083
28084         /* DSCP2TCI_TBL0_R7 */
28085         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL0_R7 dscp2tci_tbl0_r7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28086
28087         /* DSCP2TCI_TBL1_R0 */
28088         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R0 dscp2tci_tbl1_r0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28089
28090         /* DSCP2TCI_TBL1_R1 */
28091         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R1 dscp2tci_tbl1_r1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28092
28093         /* DSCP2TCI_TBL1_R2 */
28094         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R2 dscp2tci_tbl1_r2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28095
28096         /* DSCP2TCI_TBL1_R3 */
28097         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R3 dscp2tci_tbl1_r3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28098
28099         /* DSCP2TCI_TBL1_R4 */
28100         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R4 dscp2tci_tbl1_r4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28101
28102         /* DSCP2TCI_TBL1_R5 */
28103         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R5 dscp2tci_tbl1_r5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28104
28105         /* DSCP2TCI_TBL1_R6 */
28106         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R6 dscp2tci_tbl1_r6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28107
28108         /* DSCP2TCI_TBL1_R7 */
28109         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP2TCI_TBL1_R7 dscp2tci_tbl1_r7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28110
28111         /* DEFAULT_TCI_TBL0 */
28112         IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL0 default_tci_tbl0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28113
28114         /* DEFAULT_TCI_TBL1 */
28115         IH_REGS_PARSER_CORE_CONFIGURATION_DEFAULT_TCI_TBL1 default_tci_tbl1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28116
28117         /* DSCP_TBL_VALID_CFG */
28118         IH_REGS_PARSER_CORE_CONFIGURATION_DSCP_TBL_VALID_CFG dscp_tbl_valid_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28119
28120         /* DA_FILT6_VAL_L */
28121         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_L da_filt6_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28122
28123         /* DA_FILT6_VAL_H */
28124         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT6_VAL_H da_filt6_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28125
28126         /* DA_FILT7_VAL_L */
28127         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_L da_filt7_val_l __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28128
28129         /* DA_FILT7_VAL_H */
28130         IH_REGS_PARSER_CORE_CONFIGURATION_DA_FILT7_VAL_H da_filt7_val_h __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28131
28132         /* IPV6_HDR_EXT_FLTR_MASK_CFG */
28133         IH_REGS_PARSER_CORE_CONFIGURATION_IPV6_HDR_EXT_FLTR_MASK_CFG ipv6_hdr_ext_fltr_mask_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28134
28135         /* ENG */
28136         IH_REGS_PARSER_CORE_CONFIGURATION_ENG eng __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28137 }
28138  __PACKING_ATTRIBUTE_STRUCT_END__
28139 IH_REGS_PARSER_CORE_CONFIGURATION ;
28140
28141 typedef struct
28142 {
28143         /* SP2IQ_MAP_CFG */
28144         IH_REGS_GENERAL_CONFIGURATION_SP2IQ_MAP_CFG sp2iq_map_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28145
28146         /* IQ_BASE_CFG */
28147         IH_REGS_GENERAL_CONFIGURATION_IQ_BASE_CFG iq_base_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28148
28149         /* IQ_SIZE_CFG */
28150         IH_REGS_GENERAL_CONFIGURATION_IQ_SIZE_CFG iq_size_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28151
28152         /* IQL_PRIOR_CFG */
28153         IH_REGS_GENERAL_CONFIGURATION_IQL_PRIOR_CFG iql_prior_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28154
28155         /* IQH_PRIOR_CFG */
28156         IH_REGS_GENERAL_CONFIGURATION_IQH_PRIOR_CFG iqh_prior_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28157
28158         /* PHL_OFFSET_CFG */
28159         IH_REGS_GENERAL_CONFIGURATION_PHL_OFFSET_CFG phl_offset_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28160
28161         /* PHH_OFFSET_CFG */
28162         IH_REGS_GENERAL_CONFIGURATION_PHH_OFFSET_CFG phh_offset_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28163
28164         /* Reserved */
28165         uint8_t reserved1 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28166
28167         /* IQ_WEIGHT_CFG */
28168         IH_REGS_GENERAL_CONFIGURATION_IQ_WEIGHT_CFG iq_weight_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28169
28170         /* IQL_CNGS_THRS_CFG */
28171         IH_REGS_GENERAL_CONFIGURATION_IQL_CNGS_THRS_CFG iql_cngs_thrs_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28172
28173         /* IQH_CNGS_THRS_CFG */
28174         IH_REGS_GENERAL_CONFIGURATION_IQH_CNGS_THRS_CFG iqh_cngs_thrs_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28175
28176         /* Reserved */
28177         uint8_t reserved2 [ 4 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28178
28179         /* RNRA_RB_BASE */
28180         IH_REGS_GENERAL_CONFIGURATION_RNRA_RB_BASE rnra_rb_base __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28181
28182         /* RNRB_RB_BASE */
28183         IH_REGS_GENERAL_CONFIGURATION_RNRB_RB_BASE rnrb_rb_base __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28184
28185         /* RNRA_IHRSP_ADDR */
28186         IH_REGS_GENERAL_CONFIGURATION_RNRA_IHRSP_ADDR rnra_ihrsp_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28187
28188         /* RNRB_IHRSP_ADDR */
28189         IH_REGS_GENERAL_CONFIGURATION_RNRB_IHRSP_ADDR rnrb_ihrsp_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28190
28191         /* RNRA_CNGS_RPT_ADDR */
28192         IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_RPT_ADDR rnra_cngs_rpt_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28193
28194         /* RNRB_CNGS_RPT_ADDR */
28195         IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_RPT_ADDR rnrb_cngs_rpt_addr __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28196
28197         /* RNR_CNGS_RPT_CFG */
28198         IH_REGS_GENERAL_CONFIGURATION_RNR_CNGS_RPT_CFG rnr_cngs_rpt_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28199
28200         /* RADDR0_CFG */
28201         IH_REGS_GENERAL_CONFIGURATION_RADDR0_CFG raddr0_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28202
28203         /* RADDR1_CFG */
28204         IH_REGS_GENERAL_CONFIGURATION_RADDR1_CFG raddr1_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28205
28206         /* RBPM_BAT_CFG */
28207         IH_REGS_GENERAL_CONFIGURATION_RBPM_BAT_CFG rbpm_bat_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28208
28209         /* RBPM_BAC_STAT */
28210         IH_REGS_GENERAL_CONFIGURATION_RBPM_BAC_STAT rbpm_bac_stat __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28211
28212         /* TRGT_MTRX_ETH0_SP_CFG */
28213         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH0_SP_CFG trgt_mtrx_eth0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28214
28215         /* TRGT_MTRX_ETH1_SP_CFG */
28216         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH1_SP_CFG trgt_mtrx_eth1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28217
28218         /* TRGT_MTRX_ETH2_SP_CFG */
28219         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH2_SP_CFG trgt_mtrx_eth2_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28220
28221         /* TRGT_MTRX_ETH3_SP_CFG */
28222         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH3_SP_CFG trgt_mtrx_eth3_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28223
28224         /* TRGT_MTRX_ETH4_SP_CFG */
28225         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_ETH4_SP_CFG trgt_mtrx_eth4_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28226
28227         /* TRGT_MTRX_GPON_SP_CFG */
28228         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_GPON_SP_CFG trgt_mtrx_gpon_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28229
28230         /* IH_MISC_CFG */
28231         IH_REGS_GENERAL_CONFIGURATION_IH_MISC_CFG ih_misc_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28232
28233         /* IH_CLASS_KEY0 */
28234         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY0 ih_class_key0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28235
28236         /* IH_CLASS_KEY1 */
28237         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY1 ih_class_key1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28238
28239         /* IH_CLASS_KEY2 */
28240         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY2 ih_class_key2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28241
28242         /* IH_CLASS_KEY3 */
28243         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY3 ih_class_key3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28244
28245         /* IH_CLASS_KEY4 */
28246         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY4 ih_class_key4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28247
28248         /* IH_CLASS_KEY5 */
28249         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY5 ih_class_key5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28250
28251         /* IH_CLASS_KEY6 */
28252         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY6 ih_class_key6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28253
28254         /* IH_CLASS_KEY7 */
28255         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY7 ih_class_key7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28256
28257         /* IH_CLASS_KEY8 */
28258         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY8 ih_class_key8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28259
28260         /* IH_CLASS_KEY9 */
28261         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY9 ih_class_key9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28262
28263         /* Reserved */
28264         uint8_t reserved3 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28265
28266         /* IH_CLASS_KEY10 */
28267         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY10 ih_class_key10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28268
28269         /* IH_CLASS_KEY11 */
28270         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY11 ih_class_key11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28271
28272         /* IH_CLASS_KEY12 */
28273         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY12 ih_class_key12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28274
28275         /* IH_CLASS_KEY13 */
28276         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY13 ih_class_key13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28277
28278         /* IH_CLASS_KEY14 */
28279         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY14 ih_class_key14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28280
28281         /* IH_CLASS_KEY15 */
28282         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_KEY15 ih_class_key15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28283
28284         /* IH_CLASS_MASK0 */
28285         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK0 ih_class_mask0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28286
28287         /* IH_CLASS_MASK1 */
28288         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK1 ih_class_mask1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28289
28290         /* IH_CLASS_MASK2 */
28291         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK2 ih_class_mask2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28292
28293         /* IH_CLASS_MASK3 */
28294         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK3 ih_class_mask3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28295
28296         /* IH_CLASS_MASK4 */
28297         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK4 ih_class_mask4 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28298
28299         /* IH_CLASS_MASK5 */
28300         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK5 ih_class_mask5 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28301
28302         /* IH_CLASS_MASK6 */
28303         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK6 ih_class_mask6 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28304
28305         /* IH_CLASS_MASK7 */
28306         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK7 ih_class_mask7 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28307
28308         /* IH_CLASS_MASK8 */
28309         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK8 ih_class_mask8 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28310
28311         /* IH_CLASS_MASK9 */
28312         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK9 ih_class_mask9 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28313
28314         /* IH_CLASS_MASK10 */
28315         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK10 ih_class_mask10 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28316
28317         /* IH_CLASS_MASK11 */
28318         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK11 ih_class_mask11 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28319
28320         /* IH_CLASS_MASK12 */
28321         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK12 ih_class_mask12 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28322
28323         /* IH_CLASS_MASK13 */
28324         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK13 ih_class_mask13 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28325
28326         /* IH_CLASS_MASK14 */
28327         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK14 ih_class_mask14 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28328
28329         /* IH_CLASS_MASK15 */
28330         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS_MASK15 ih_class_mask15 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28331
28332         /* IH_CLASS0_GENERAL_CFG */
28333         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_GENERAL_CFG ih_class0_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28334
28335         /* IH_CLASS1_GENERAL_CFG */
28336         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_GENERAL_CFG ih_class1_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28337
28338         /* IH_CLASS2_GENERAL_CFG */
28339         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_GENERAL_CFG ih_class2_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28340
28341         /* IH_CLASS3_GENERAL_CFG */
28342         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_GENERAL_CFG ih_class3_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28343
28344         /* IH_CLASS4_GENERAL_CFG */
28345         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_GENERAL_CFG ih_class4_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28346
28347         /* IH_CLASS5_GENERAL_CFG */
28348         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_GENERAL_CFG ih_class5_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28349
28350         /* IH_CLASS6_GENERAL_CFG */
28351         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_GENERAL_CFG ih_class6_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28352
28353         /* IH_CLASS7_GENERAL_CFG */
28354         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_GENERAL_CFG ih_class7_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28355
28356         /* IH_CLASS8_GENERAL_CFG */
28357         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_GENERAL_CFG ih_class8_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28358
28359         /* IH_CLASS9_GENERAL_CFG */
28360         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_GENERAL_CFG ih_class9_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28361
28362         /* IH_CLASS10_GENERAL_CFG */
28363         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_GENERAL_CFG ih_class10_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28364
28365         /* IH_CLASS11_GENERAL_CFG */
28366         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_GENERAL_CFG ih_class11_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28367
28368         /* IH_CLASS12_GENERAL_CFG */
28369         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_GENERAL_CFG ih_class12_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28370
28371         /* IH_CLASS13_GENERAL_CFG */
28372         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_GENERAL_CFG ih_class13_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28373
28374         /* IH_CLASS14_GENERAL_CFG */
28375         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_GENERAL_CFG ih_class14_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28376
28377         /* IH_CLASS15_GENERAL_CFG */
28378         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_GENERAL_CFG ih_class15_general_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28379
28380         /* IH_CLASS0_SEARCH_CFG */
28381         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS0_SEARCH_CFG ih_class0_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28382
28383         /* IH_CLASS1_SEARCH_CFG */
28384         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS1_SEARCH_CFG ih_class1_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28385
28386         /* Reserved */
28387         uint8_t reserved4 [ 96 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28388
28389         /* IH_CLASS2_SEARCH_CFG */
28390         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS2_SEARCH_CFG ih_class2_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28391
28392         /* IH_CLASS3_SEARCH_CFG */
28393         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS3_SEARCH_CFG ih_class3_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28394
28395         /* IH_CLASS4_SEARCH_CFG */
28396         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS4_SEARCH_CFG ih_class4_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28397
28398         /* IH_CLASS5_SEARCH_CFG */
28399         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS5_SEARCH_CFG ih_class5_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28400
28401         /* IH_CLASS6_SEARCH_CFG */
28402         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS6_SEARCH_CFG ih_class6_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28403
28404         /* IH_CLASS7_SEARCH_CFG */
28405         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS7_SEARCH_CFG ih_class7_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28406
28407         /* IH_CLASS8_SEARCH_CFG */
28408         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS8_SEARCH_CFG ih_class8_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28409
28410         /* IH_CLASS9_SEARCH_CFG */
28411         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS9_SEARCH_CFG ih_class9_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28412
28413         /* IH_CLASS10_SEARCH_CFG */
28414         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS10_SEARCH_CFG ih_class10_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28415
28416         /* IH_CLASS11_SEARCH_CFG */
28417         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS11_SEARCH_CFG ih_class11_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28418
28419         /* IH_CLASS12_SEARCH_CFG */
28420         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS12_SEARCH_CFG ih_class12_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28421
28422         /* IH_CLASS13_SEARCH_CFG */
28423         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS13_SEARCH_CFG ih_class13_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28424
28425         /* IH_CLASS14_SEARCH_CFG */
28426         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS14_SEARCH_CFG ih_class14_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28427
28428         /* IH_CLASS15_SEARCH_CFG */
28429         IH_REGS_GENERAL_CONFIGURATION_IH_CLASS15_SEARCH_CFG ih_class15_search_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28430
28431         /* RNRA_CNGS_TRSH_CFG */
28432         IH_REGS_GENERAL_CONFIGURATION_RNRA_CNGS_TRSH_CFG rnra_cngs_trsh_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28433
28434         /* RNRB_CNGS_TRSH_CFG */
28435         IH_REGS_GENERAL_CONFIGURATION_RNRB_CNGS_TRSH_CFG rnrb_cngs_trsh_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28436
28437         /* WAN_PER_PORT_CFG */
28438         IH_REGS_GENERAL_CONFIGURATION_WAN_PER_PORT_CFG wan_per_port_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28439
28440         /* PARSE_LAYER_PER_PORT_CFG */
28441         IH_REGS_GENERAL_CONFIGURATION_PARSE_LAYER_PER_PORT_CFG parse_layer_per_port_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28442
28443         /* PROP_SIZE_PER_PORT_CFG0 */
28444         IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG0 prop_size_per_port_cfg0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28445
28446         /* PROP_SIZE_PER_PORT_CFG1 */
28447         IH_REGS_GENERAL_CONFIGURATION_PROP_SIZE_PER_PORT_CFG1 prop_size_per_port_cfg1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28448
28449         /* IH_CLSF_MAPL_CFG */
28450         IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPL_CFG ih_clsf_mapl_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28451
28452         /* IH_CLSF_MAPH_CFG */
28453         IH_REGS_GENERAL_CONFIGURATION_IH_CLSF_MAPH_CFG ih_clsf_maph_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28454
28455         /* TRGT_MTRX_PCIE0_SP_CFG */
28456         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE0_SP_CFG trgt_mtrx_pcie0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28457
28458         /* TRGT_MTRX_PCIE1_SP_CFG */
28459         IH_REGS_GENERAL_CONFIGURATION_TRGT_MTRX_PCIE1_SP_CFG trgt_mtrx_pcie1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28460
28461         /* FW_EN_MTRX_ETH0_SP_CFG */
28462         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH0_SP_CFG fw_en_mtrx_eth0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28463
28464         /* FW_EN_MTRX_ETH1_SP_CFG */
28465         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH1_SP_CFG fw_en_mtrx_eth1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28466
28467         /* FW_EN_MTRX_ETH2_SP_CFG */
28468         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH2_SP_CFG fw_en_mtrx_eth2_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28469
28470         /* FW_EN_MTRX_ETH3_SP_CFG */
28471         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH3_SP_CFG fw_en_mtrx_eth3_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28472
28473         /* FW_EN_MTRX_ETH4_SP_CFG */
28474         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_ETH4_SP_CFG fw_en_mtrx_eth4_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28475
28476         /* FW_EN_MTRX_GPON_SP_CFG */
28477         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_GPON_SP_CFG fw_en_mtrx_gpon_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28478
28479         /* FW_EN_MTRX_PCIE0_SP_CFG */
28480         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE0_SP_CFG fw_en_mtrx_pcie0_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28481
28482         /* FW_EN_MTRX_PCIE1_SP_CFG */
28483         IH_REGS_GENERAL_CONFIGURATION_FW_EN_MTRX_PCIE1_SP_CFG fw_en_mtrx_pcie1_sp_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28484
28485         /* PH_MEM_RD_RQST_CFG */
28486         IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_RQST_CFG ph_mem_rd_rqst_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28487
28488         /* PH_MEM_RD_DATA_LOW */
28489         IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_LOW ph_mem_rd_data_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28490
28491         /* PH_MEM_RD_DATA_HIGH */
28492         IH_REGS_GENERAL_CONFIGURATION_PH_MEM_RD_DATA_HIGH ph_mem_rd_data_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28493
28494         /* SN_REG_0 */
28495         IH_REGS_GENERAL_CONFIGURATION_SN_REG_0 sn_reg_0 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28496
28497         /* SN_REG_1 */
28498         IH_REGS_GENERAL_CONFIGURATION_SN_REG_1 sn_reg_1 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28499
28500         /* SN_REG_2 */
28501         IH_REGS_GENERAL_CONFIGURATION_SN_REG_2 sn_reg_2 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28502
28503         /* SN_REG_3 */
28504         IH_REGS_GENERAL_CONFIGURATION_SN_REG_3 sn_reg_3 __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28505
28506         /* LOCAL_MEM_RD_RQST_CFG */
28507         IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_RQST_CFG local_mem_rd_rqst_cfg __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28508
28509         /* LOCAL_MEM_RD_DATA_LOW */
28510         IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_LOW local_mem_rd_data_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28511
28512         /* LOCAL_MEM_RD_DATA_HIGH */
28513         IH_REGS_GENERAL_CONFIGURATION_LOCAL_MEM_RD_DATA_HIGH local_mem_rd_data_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28514
28515         /* DBG_KEY1_LOW */
28516         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_LOW dbg_key1_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28517
28518         /* DBG_KEY1_HIGH */
28519         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY1_HIGH dbg_key1_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28520
28521         /* DBG_KEY2_LOW */
28522         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_LOW dbg_key2_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28523
28524         /* DBG_KEY2_HIGH */
28525         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY2_HIGH dbg_key2_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28526
28527         /* DBG_KEY3_LOW */
28528         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_LOW dbg_key3_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28529
28530         /* DBG_KEY3_HIGH */
28531         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY3_HIGH dbg_key3_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28532
28533         /* DBG_KEY4_LOW */
28534         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_LOW dbg_key4_low __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28535
28536         /* DBG_KEY4_HIGH */
28537         IH_REGS_GENERAL_CONFIGURATION_DBG_KEY4_HIGH dbg_key4_high __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28538
28539         /* DBG_IQ_STAT */
28540         IH_REGS_GENERAL_CONFIGURATION_DBG_IQ_STAT dbg_iq_stat __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28541
28542         /* DBG_RBOUT_SEL */
28543         IH_REGS_GENERAL_CONFIGURATION_DBG_RBOUT_SEL dbg_rbout_sel __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28544
28545         /* DBG_CRITICAL_STAT */
28546         IH_REGS_GENERAL_CONFIGURATION_DBG_CRITICAL_STAT dbg_critical_stat __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28547 }
28548  __PACKING_ATTRIBUTE_STRUCT_END__
28549 IH_REGS_GENERAL_CONFIGURATION ;
28550
28551 typedef struct
28552 {
28553         /* lookup_configuration function */
28554         IH_REGS_LOOKUP_CONFIGURATION lookup_configuration __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28555
28556         /* Reserved */
28557         uint8_t reserved0 [ 624 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28558
28559         /* parser_core_configuration function */
28560         IH_REGS_PARSER_CORE_CONFIGURATION parser_core_configuration __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28561
28562         /* Reserved */
28563         uint8_t reserved1 [ 764 ] __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28564
28565         /* general_configuration function */
28566         IH_REGS_GENERAL_CONFIGURATION general_configuration __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28567 }
28568  __PACKING_ATTRIBUTE_STRUCT_END__
28569 IH_REGS ;
28570
28571 typedef struct
28572 {
28573         /* REGS */
28574         IH_REGS regs __PACKING_ATTRIBUTE_FIELD_LEVEL__ ;
28575 }
28576 __PACKING_ATTRIBUTE_STRUCT_END__
28577 IH_FOR_ALL ;
28578 #endif /* IH_H_INCLUDED */
28579