2 * UniPhier SG (SoC Glue) block registers
4 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #define ARCH_SG_REGS_H
13 #define SG_CTRL_BASE 0x5f800000
14 #define SG_DBG_BASE 0x5f900000
17 #define SG_REVISION (SG_CTRL_BASE | 0x0000)
18 #define SG_REVISION_TYPE_SHIFT 16
19 #define SG_REVISION_TYPE_MASK (0xff << SG_REVISION_TYPE_SHIFT)
20 #define SG_REVISION_MODEL_SHIFT 8
21 #define SG_REVISION_MODEL_MASK (0x3 << SG_REVISION_MODEL_SHIFT)
22 #define SG_REVISION_REV_SHIFT 0
23 #define SG_REVISION_REV_MASK (0x1f << SG_REVISION_REV_SHIFT)
25 /* Memory Configuration */
26 #define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
28 #define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
29 #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
30 #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
31 #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
32 #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
33 #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
34 #define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
35 #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
36 #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
38 #define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
39 #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
40 #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
41 #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
42 #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
43 #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
44 #define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
45 #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
46 #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
48 #define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
49 #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
50 #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
51 #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
52 #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
53 #define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16))
54 #define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
55 #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
56 #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
57 /* PH1-LD6b, ProXstream2, PH1-LD20 only */
58 #define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
60 #define SG_MEMCONF_SPARSEMEM (0x1 << 4)
62 #define SG_ETPHYPSHUT (SG_CTRL_BASE | 0x554)
63 #define SG_ETPHYCNT (SG_CTRL_BASE | 0x550)
66 #define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
68 /* PH1-Pro4, PH1-Pro5 */
69 #define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
72 #define SG_IECTRL (SG_CTRL_BASE | 0x1d00)
75 #define SG_PINMON0 (SG_DBG_BASE | 0x0100)
77 #define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
78 #define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
79 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
80 #define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
82 #define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
83 #define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
84 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
85 #define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
86 #define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
88 #define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
89 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
90 #define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
91 #define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
95 .macro sg_set_pinsel
, pin
, muxval
, mux_bits
, reg_stride
, ra
, rd
96 ldr
\ra
, =(SG_PINCTRL_BASE
+ \pin
* \mux_bits
/ 32 * \reg_stride
)
98 and \rd
, \rd
, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
99 orr
\rd
, \rd
, #(\muxval << (\pin * \mux_bits % 32))
105 #include <linux/types.h>
106 #include <linux/io.h>
108 static inline void sg_set_pinsel(unsigned pin
, unsigned muxval
,
109 unsigned mux_bits
, unsigned reg_stride
)
111 unsigned shift
= pin
* mux_bits
% 32;
112 unsigned long reg
= SG_PINCTRL_BASE
+ pin
* mux_bits
/ 32 * reg_stride
;
113 u32 mask
= (1U << mux_bits
) - 1;
117 tmp
&= ~(mask
<< shift
);
118 tmp
|= (mask
& muxval
) << shift
;
122 static inline void sg_set_iectrl(unsigned pin
)
124 unsigned bit
= pin
% 32;
125 unsigned long reg
= SG_IECTRL
+ pin
/ 32 * 4;
133 static inline void sg_set_iectrl_range(unsigned min
, unsigned max
)
137 for (i
= min
; i
<= max
; i
++)
141 #endif /* __ASSEMBLY__ */
143 #endif /* ARCH_SG_REGS_H */