1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
9 #ifndef CONFIG_CLK_MPC83XX
14 #include <asm/processor.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 /* ----------------------------------------------------------------- */
36 mult_t core_csb_ratio
;
40 static corecnf_t corecnf_tab
[] = {
41 {_byp
, _byp
}, /* 0x00 */
42 {_byp
, _byp
}, /* 0x01 */
43 {_byp
, _byp
}, /* 0x02 */
44 {_byp
, _byp
}, /* 0x03 */
45 {_byp
, _byp
}, /* 0x04 */
46 {_byp
, _byp
}, /* 0x05 */
47 {_byp
, _byp
}, /* 0x06 */
48 {_byp
, _byp
}, /* 0x07 */
49 {_1x
, _x2
}, /* 0x08 */
50 {_1x
, _x4
}, /* 0x09 */
51 {_1x
, _x8
}, /* 0x0A */
52 {_1x
, _x8
}, /* 0x0B */
53 {_1_5x
, _x2
}, /* 0x0C */
54 {_1_5x
, _x4
}, /* 0x0D */
55 {_1_5x
, _x8
}, /* 0x0E */
56 {_1_5x
, _x8
}, /* 0x0F */
57 {_2x
, _x2
}, /* 0x10 */
58 {_2x
, _x4
}, /* 0x11 */
59 {_2x
, _x8
}, /* 0x12 */
60 {_2x
, _x8
}, /* 0x13 */
61 {_2_5x
, _x2
}, /* 0x14 */
62 {_2_5x
, _x4
}, /* 0x15 */
63 {_2_5x
, _x8
}, /* 0x16 */
64 {_2_5x
, _x8
}, /* 0x17 */
65 {_3x
, _x2
}, /* 0x18 */
66 {_3x
, _x4
}, /* 0x19 */
67 {_3x
, _x8
}, /* 0x1A */
68 {_3x
, _x8
}, /* 0x1B */
71 /* ----------------------------------------------------------------- */
78 volatile immap_t
*im
= (immap_t
*) CONFIG_SYS_IMMR
;
83 u32 corecnf_tab_index
;
88 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
89 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
93 #elif defined(CONFIG_MPC8309)
101 #if !defined(CONFIG_MPC832x)
104 #if defined(CONFIG_MPC8315)
107 #if defined(CONFIG_FSL_ESDHC)
110 #if !defined(CONFIG_MPC8309)
116 #if defined(CONFIG_MPC8360)
119 #if defined(CONFIG_QE)
125 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
126 defined(CONFIG_MPC837x)
130 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
134 if ((im
->sysconf
.immrbar
& IMMRBAR_BASE_ADDR
) != (u32
) im
)
137 clkin_div
= ((im
->clk
.spmr
& SPMR_CKID
) >> SPMR_CKID_SHIFT
);
139 if (im
->reset
.rcwh
& HRCWH_PCI_HOST
) {
140 #if defined(CONFIG_83XX_CLKIN)
141 pci_sync_in
= CONFIG_83XX_CLKIN
/ (1 + clkin_div
);
143 pci_sync_in
= 0xDEADBEEF;
146 #if defined(CONFIG_83XX_PCICLK)
147 pci_sync_in
= CONFIG_83XX_PCICLK
;
149 pci_sync_in
= 0xDEADBEEF;
153 spmf
= (im
->clk
.spmr
& SPMR_SPMF
) >> SPMR_SPMF_SHIFT
;
154 csb_clk
= pci_sync_in
* (1 + clkin_div
) * spmf
;
158 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
159 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
160 switch ((sccr
& SCCR_TSEC1CM
) >> SCCR_TSEC1CM_SHIFT
) {
168 tsec1_clk
= csb_clk
/ 2;
171 tsec1_clk
= csb_clk
/ 3;
174 /* unknown SCCR_TSEC1CM value */
179 #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
180 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
181 switch ((sccr
& SCCR_USBDRCM
) >> SCCR_USBDRCM_SHIFT
) {
189 usbdr_clk
= csb_clk
/ 2;
192 usbdr_clk
= csb_clk
/ 3;
195 /* unknown SCCR_USBDRCM value */
200 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
201 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
202 switch ((sccr
& SCCR_TSEC2CM
) >> SCCR_TSEC2CM_SHIFT
) {
210 tsec2_clk
= csb_clk
/ 2;
213 tsec2_clk
= csb_clk
/ 3;
216 /* unknown SCCR_TSEC2CM value */
219 #elif defined(CONFIG_MPC8313)
220 tsec2_clk
= tsec1_clk
;
222 if (!(sccr
& SCCR_TSEC1ON
))
224 if (!(sccr
& SCCR_TSEC2ON
))
228 #if defined(CONFIG_MPC834x)
229 switch ((sccr
& SCCR_USBMPHCM
) >> SCCR_USBMPHCM_SHIFT
) {
234 usbmph_clk
= csb_clk
;
237 usbmph_clk
= csb_clk
/ 2;
240 usbmph_clk
= csb_clk
/ 3;
243 /* unknown SCCR_USBMPHCM value */
247 if (usbmph_clk
!= 0 && usbdr_clk
!= 0 && usbmph_clk
!= usbdr_clk
) {
248 /* if USB MPH clock is not disabled and
249 * USB DR clock is not disabled then
250 * USB MPH & USB DR must have the same rate
255 #if !defined(CONFIG_MPC8309)
256 switch ((sccr
& SCCR_ENCCM
) >> SCCR_ENCCM_SHIFT
) {
264 enc_clk
= csb_clk
/ 2;
267 enc_clk
= csb_clk
/ 3;
270 /* unknown SCCR_ENCCM value */
275 #if defined(CONFIG_FSL_ESDHC)
276 switch ((sccr
& SCCR_SDHCCM
) >> SCCR_SDHCCM_SHIFT
) {
284 sdhc_clk
= csb_clk
/ 2;
287 sdhc_clk
= csb_clk
/ 3;
290 /* unknown SCCR_SDHCCM value */
294 #if defined(CONFIG_MPC8315)
295 switch ((sccr
& SCCR_TDMCM
) >> SCCR_TDMCM_SHIFT
) {
303 tdm_clk
= csb_clk
/ 2;
306 tdm_clk
= csb_clk
/ 3;
309 /* unknown SCCR_TDMCM value */
314 #if defined(CONFIG_MPC834x)
315 i2c1_clk
= tsec2_clk
;
316 #elif defined(CONFIG_MPC8360)
318 #elif defined(CONFIG_MPC832x)
320 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
322 #elif defined(CONFIG_FSL_ESDHC)
324 #elif defined(CONFIG_MPC837x)
326 #elif defined(CONFIG_MPC8309)
329 #if !defined(CONFIG_MPC832x)
330 i2c2_clk
= csb_clk
; /* i2c-2 clk is equal to csb clk */
333 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
334 defined(CONFIG_MPC837x)
335 switch ((sccr
& SCCR_PCIEXP1CM
) >> SCCR_PCIEXP1CM_SHIFT
) {
340 pciexp1_clk
= csb_clk
;
343 pciexp1_clk
= csb_clk
/ 2;
346 pciexp1_clk
= csb_clk
/ 3;
349 /* unknown SCCR_PCIEXP1CM value */
353 switch ((sccr
& SCCR_PCIEXP2CM
) >> SCCR_PCIEXP2CM_SHIFT
) {
358 pciexp2_clk
= csb_clk
;
361 pciexp2_clk
= csb_clk
/ 2;
364 pciexp2_clk
= csb_clk
/ 3;
367 /* unknown SCCR_PCIEXP2CM value */
372 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
373 switch ((sccr
& SCCR_SATA1CM
) >> SCCR_SATA1CM_SHIFT
) {
381 sata_clk
= csb_clk
/ 2;
384 sata_clk
= csb_clk
/ 3;
387 /* unknown SCCR_SATA1CM value */
393 (1 + ((im
->clk
.spmr
& SPMR_LBIUCM
) >> SPMR_LBIUCM_SHIFT
));
394 lcrr
= (im
->im_lbc
.lcrr
& LCRR_CLKDIV
) >> LCRR_CLKDIV_SHIFT
;
399 lclk_clk
= lbiu_clk
/ lcrr
;
407 (1 + ((im
->clk
.spmr
& SPMR_DDRCM
) >> SPMR_DDRCM_SHIFT
));
408 corepll
= (im
->clk
.spmr
& SPMR_COREPLL
) >> SPMR_COREPLL_SHIFT
;
410 #if defined(CONFIG_MPC8360)
411 mem_sec_clk
= csb_clk
* (1 +
412 ((im
->clk
.spmr
& SPMR_LBIUCM
) >> SPMR_LBIUCM_SHIFT
));
415 corecnf_tab_index
= ((corepll
& 0x1F) << 2) | ((corepll
& 0x60) >> 5);
416 if (corecnf_tab_index
> (ARRAY_SIZE(corecnf_tab
))) {
417 /* corecnf_tab_index is too high, possibly wrong value */
420 switch (corecnf_tab
[corecnf_tab_index
].core_csb_ratio
) {
427 core_clk
= (3 * csb_clk
) / 2;
430 core_clk
= 2 * csb_clk
;
433 core_clk
= (5 * csb_clk
) / 2;
436 core_clk
= 3 * csb_clk
;
439 /* unknown core to csb ratio */
443 #if defined(CONFIG_QE)
444 qepmf
= (im
->clk
.spmr
& SPMR_CEPMF
) >> SPMR_CEPMF_SHIFT
;
445 qepdf
= (im
->clk
.spmr
& SPMR_CEPDF
) >> SPMR_CEPDF_SHIFT
;
446 qe_clk
= (pci_sync_in
* qepmf
) / (1 + qepdf
);
447 brg_clk
= qe_clk
/ 2;
450 gd
->arch
.csb_clk
= csb_clk
;
451 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
452 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
453 gd
->arch
.tsec1_clk
= tsec1_clk
;
454 gd
->arch
.tsec2_clk
= tsec2_clk
;
455 gd
->arch
.usbdr_clk
= usbdr_clk
;
456 #elif defined(CONFIG_MPC8309)
457 gd
->arch
.usbdr_clk
= usbdr_clk
;
459 #if defined(CONFIG_MPC834x)
460 gd
->arch
.usbmph_clk
= usbmph_clk
;
462 #if defined(CONFIG_MPC8315)
463 gd
->arch
.tdm_clk
= tdm_clk
;
465 #if defined(CONFIG_FSL_ESDHC)
466 gd
->arch
.sdhc_clk
= sdhc_clk
;
468 gd
->arch
.core_clk
= core_clk
;
469 gd
->arch
.i2c1_clk
= i2c1_clk
;
470 #if !defined(CONFIG_MPC832x)
471 gd
->arch
.i2c2_clk
= i2c2_clk
;
473 #if !defined(CONFIG_MPC8309)
474 gd
->arch
.enc_clk
= enc_clk
;
476 gd
->arch
.lbiu_clk
= lbiu_clk
;
477 gd
->arch
.lclk_clk
= lclk_clk
;
478 gd
->mem_clk
= mem_clk
;
479 #if defined(CONFIG_MPC8360)
480 gd
->arch
.mem_sec_clk
= mem_sec_clk
;
482 #if defined(CONFIG_QE)
483 gd
->arch
.qe_clk
= qe_clk
;
484 gd
->arch
.brg_clk
= brg_clk
;
486 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
487 defined(CONFIG_MPC837x)
488 gd
->arch
.pciexp1_clk
= pciexp1_clk
;
489 gd
->arch
.pciexp2_clk
= pciexp2_clk
;
491 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
492 gd
->arch
.sata_clk
= sata_clk
;
494 gd
->pci_clk
= pci_sync_in
;
495 gd
->cpu_clk
= gd
->arch
.core_clk
;
496 gd
->bus_clk
= gd
->arch
.csb_clk
;
501 /********************************************
503 * return system bus freq in Hz
504 *********************************************/
505 ulong
get_bus_freq(ulong dummy
)
507 return gd
->arch
.csb_clk
;
510 /********************************************
512 * return ddr bus freq in Hz
513 *********************************************/
514 ulong
get_ddr_freq(ulong dummy
)
519 static int do_clocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
523 printf("Clock configuration:\n");
524 printf(" Core: %-4s MHz\n",
525 strmhz(buf
, gd
->arch
.core_clk
));
526 printf(" Coherent System Bus: %-4s MHz\n",
527 strmhz(buf
, gd
->arch
.csb_clk
));
528 #if defined(CONFIG_QE)
529 printf(" QE: %-4s MHz\n",
530 strmhz(buf
, gd
->arch
.qe_clk
));
531 printf(" BRG: %-4s MHz\n",
532 strmhz(buf
, gd
->arch
.brg_clk
));
534 printf(" Local Bus Controller:%-4s MHz\n",
535 strmhz(buf
, gd
->arch
.lbiu_clk
));
536 printf(" Local Bus: %-4s MHz\n",
537 strmhz(buf
, gd
->arch
.lclk_clk
));
538 printf(" DDR: %-4s MHz\n", strmhz(buf
, gd
->mem_clk
));
539 #if defined(CONFIG_MPC8360)
540 printf(" DDR Secondary: %-4s MHz\n",
541 strmhz(buf
, gd
->arch
.mem_sec_clk
));
543 #if !defined(CONFIG_MPC8309)
544 printf(" SEC: %-4s MHz\n",
545 strmhz(buf
, gd
->arch
.enc_clk
));
547 printf(" I2C1: %-4s MHz\n",
548 strmhz(buf
, gd
->arch
.i2c1_clk
));
549 #if !defined(CONFIG_MPC832x)
550 printf(" I2C2: %-4s MHz\n",
551 strmhz(buf
, gd
->arch
.i2c2_clk
));
553 #if defined(CONFIG_MPC8315)
554 printf(" TDM: %-4s MHz\n",
555 strmhz(buf
, gd
->arch
.tdm_clk
));
557 #if defined(CONFIG_FSL_ESDHC)
558 printf(" SDHC: %-4s MHz\n",
559 strmhz(buf
, gd
->arch
.sdhc_clk
));
561 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
562 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
563 printf(" TSEC1: %-4s MHz\n",
564 strmhz(buf
, gd
->arch
.tsec1_clk
));
565 printf(" TSEC2: %-4s MHz\n",
566 strmhz(buf
, gd
->arch
.tsec2_clk
));
567 printf(" USB DR: %-4s MHz\n",
568 strmhz(buf
, gd
->arch
.usbdr_clk
));
569 #elif defined(CONFIG_MPC8309)
570 printf(" USB DR: %-4s MHz\n",
571 strmhz(buf
, gd
->arch
.usbdr_clk
));
573 #if defined(CONFIG_MPC834x)
574 printf(" USB MPH: %-4s MHz\n",
575 strmhz(buf
, gd
->arch
.usbmph_clk
));
577 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
578 defined(CONFIG_MPC837x)
579 printf(" PCIEXP1: %-4s MHz\n",
580 strmhz(buf
, gd
->arch
.pciexp1_clk
));
581 printf(" PCIEXP2: %-4s MHz\n",
582 strmhz(buf
, gd
->arch
.pciexp2_clk
));
584 #if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
585 printf(" SATA: %-4s MHz\n",
586 strmhz(buf
, gd
->arch
.sata_clk
));
591 U_BOOT_CMD(clocks
, 1, 0, do_clocks
,
592 "print clock configuration",