bl1/aarch64/bl1_context_mgmt.c

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8
   9 #include <arch_helpers.h>
  10 #include <context.h>
  11 #include <common/debug.h>
  12 #include <lib/el3_runtime/context_mgmt.h>
  13 #include <plat/common/platform.h>
  14
  15 #include "../bl1_private.h"
  16
  17 /*
  18  * Following array will be used for context management.
  19  * There are 2 instances, for the Secure and Non-Secure contexts.
  20  */
  21 static cpu_context_t bl1_cpu_context[2];
  22
  23 /* Following contains the cpu context pointers. */
  24 static void *bl1_cpu_context_ptr[2];
  25
  26
  27 void *cm_get_context(uint32_t security_state)
  28 {
  29         assert(sec_state_is_valid(security_state));
  30         return bl1_cpu_context_ptr[security_state];
  31 }
  32
  33 void cm_set_context(void *context, uint32_t security_state)
  34 {
  35         assert(sec_state_is_valid(security_state));
  36         bl1_cpu_context_ptr[security_state] = context;
  37 }
  38
  39 /*******************************************************************************
  40  * This function prepares the context for Secure/Normal world images.
  41  * Normal world images are transitioned to EL2(if supported) else EL1.
  42  ******************************************************************************/
  43 void bl1_prepare_next_image(unsigned int image_id)
  44 {
  45         unsigned int security_state;
  46         image_desc_t *image_desc;
  47         entry_point_info_t *next_bl_ep;
  48
  49 #if CTX_INCLUDE_AARCH32_REGS
  50         /*
  51          * Ensure that the build flag to save AArch32 system registers in CPU
  52          * context is not set for AArch64-only platforms.
  53          */
  54         if (el_implemented(1) == EL_IMPL_A64ONLY) {
  55                 ERROR("EL1 supports AArch64-only. Please set build flag "
  56                                 "CTX_INCLUDE_AARCH32_REGS = 0\n");
  57                 panic();
  58         }
  59 #endif
  60
  61         /* Get the image descriptor. */
  62         image_desc = bl1_plat_get_image_desc(image_id);
  63         assert(image_desc);
  64
  65         /* Get the entry point info. */
  66         next_bl_ep = &image_desc->ep_info;
  67
  68         /* Get the image security state. */
  69         security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
  70
  71         /* Setup the Secure/Non-Secure context if not done already. */
  72         if (!cm_get_context(security_state))
  73                 cm_set_context(&bl1_cpu_context[security_state], security_state);
  74
  75         /* Prepare the SPSR for the next BL image. */
  76         if (security_state == SECURE) {
  77                 next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
  78                                    DISABLE_ALL_EXCEPTIONS);
  79         } else {
  80                 /* Use EL2 if supported; else use EL1. */
  81                 if (el_implemented(2) != EL_IMPL_NONE) {
  82                         next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
  83                                 DISABLE_ALL_EXCEPTIONS);
  84                 } else {
  85                         next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
  86                            DISABLE_ALL_EXCEPTIONS);
  87                 }
  88         }
  89
  90         /* Allow platform to make change */
  91         bl1_plat_set_ep_info(image_id, next_bl_ep);
  92
  93         /* Prepare the context for the next BL image. */
  94         cm_init_my_context(next_bl_ep);
  95         cm_prepare_el3_exit(security_state);
  96
  97         /* Indicate that image is in execution state. */
  98         image_desc->state = IMAGE_STATE_EXECUTED;
  99
 100         print_entry_point_info(next_bl_ep);
 101 }