bl1/bl1.ld.S

   1 /*
   2  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8 #include <xlat_tables_defs.h>
   9
  10 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
  11 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
  12 ENTRY(bl1_entrypoint)
  13
  14 MEMORY {
  15     ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
  16     RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
  17 }
  18
  19 SECTIONS
  20 {
  21     . = BL1_RO_BASE;
  22     ASSERT(. == ALIGN(PAGE_SIZE),
  23            "BL1_RO_BASE address is not aligned on a page boundary.")
  24
  25 #if SEPARATE_CODE_AND_RODATA
  26     .text . : {
  27         __TEXT_START__ = .;
  28         *bl1_entrypoint.o(.text*)
  29         *(.text*)
  30         *(.vectors)
  31         . = NEXT(PAGE_SIZE);
  32         __TEXT_END__ = .;
  33      } >ROM
  34
  35     .rodata . : {
  36         __RODATA_START__ = .;
  37         *(.rodata*)
  38
  39         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  40         . = ALIGN(8);
  41         __PARSER_LIB_DESCS_START__ = .;
  42         KEEP(*(.img_parser_lib_descs))
  43         __PARSER_LIB_DESCS_END__ = .;
  44
  45         /*
  46          * Ensure 8-byte alignment for cpu_ops so that its fields are also
  47          * aligned. Also ensure cpu_ops inclusion.
  48          */
  49         . = ALIGN(8);
  50         __CPU_OPS_START__ = .;
  51         KEEP(*(cpu_ops))
  52         __CPU_OPS_END__ = .;
  53
  54         /*
  55          * No need to pad out the .rodata section to a page boundary. Next is
  56          * the .data section, which can mapped in ROM with the same memory
  57          * attributes as the .rodata section.
  58          */
  59         __RODATA_END__ = .;
  60     } >ROM
  61 #else
  62     ro . : {
  63         __RO_START__ = .;
  64         *bl1_entrypoint.o(.text*)
  65         *(.text*)
  66         *(.rodata*)
  67
  68         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  69         . = ALIGN(8);
  70         __PARSER_LIB_DESCS_START__ = .;
  71         KEEP(*(.img_parser_lib_descs))
  72         __PARSER_LIB_DESCS_END__ = .;
  73
  74         /*
  75          * Ensure 8-byte alignment for cpu_ops so that its fields are also
  76          * aligned. Also ensure cpu_ops inclusion.
  77          */
  78         . = ALIGN(8);
  79         __CPU_OPS_START__ = .;
  80         KEEP(*(cpu_ops))
  81         __CPU_OPS_END__ = .;
  82
  83         *(.vectors)
  84         __RO_END__ = .;
  85     } >ROM
  86 #endif
  87
  88     ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
  89            "cpu_ops not defined for this platform.")
  90
  91     . = BL1_RW_BASE;
  92     ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
  93            "BL1_RW_BASE address is not aligned on a page boundary.")
  94
  95     /*
  96      * The .data section gets copied from ROM to RAM at runtime.
  97      * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
  98      * aligned regions in it.
  99      * Its VMA must be page-aligned as it marks the first read/write page.
 100      *
 101      * It must be placed at a lower address than the stacks if the stack
 102      * protector is enabled. Alternatively, the .data.stack_protector_canary
 103      * section can be placed independently of the main .data section.
 104      */
 105     .data . : ALIGN(16) {
 106         __DATA_RAM_START__ = .;
 107         *(.data*)
 108         __DATA_RAM_END__ = .;
 109     } >RAM AT>ROM
 110
 111     stacks . (NOLOAD) : {
 112         __STACKS_START__ = .;
 113         *(tzfw_normal_stacks)
 114         __STACKS_END__ = .;
 115     } >RAM
 116
 117     /*
 118      * The .bss section gets initialised to 0 at runtime.
 119      * Its base address should be 16-byte aligned for better performance of the
 120      * zero-initialization code.
 121      */
 122     .bss : ALIGN(16) {
 123         __BSS_START__ = .;
 124         *(.bss*)
 125         *(COMMON)
 126         __BSS_END__ = .;
 127     } >RAM
 128
 129     /*
 130      * The xlat_table section is for full, aligned page tables (4K).
 131      * Removing them from .bss avoids forcing 4K alignment on
 132      * the .bss section. The tables are initialized to zero by the translation
 133      * tables library.
 134      */
 135     xlat_table (NOLOAD) : {
 136         *(xlat_table)
 137     } >RAM
 138
 139 #if USE_COHERENT_MEM
 140     /*
 141      * The base address of the coherent memory section must be page-aligned (4K)
 142      * to guarantee that the coherent data are stored on their own pages and
 143      * are not mixed with normal data.  This is required to set up the correct
 144      * memory attributes for the coherent data page tables.
 145      */
 146     coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
 147         __COHERENT_RAM_START__ = .;
 148         *(tzfw_coherent_mem)
 149         __COHERENT_RAM_END_UNALIGNED__ = .;
 150         /*
 151          * Memory page(s) mapped to this section will be marked
 152          * as device memory.  No other unexpected data must creep in.
 153          * Ensure the rest of the current memory page is unused.
 154          */
 155         . = NEXT(PAGE_SIZE);
 156         __COHERENT_RAM_END__ = .;
 157     } >RAM
 158 #endif
 159
 160     __BL1_RAM_START__ = ADDR(.data);
 161     __BL1_RAM_END__ = .;
 162
 163     __DATA_ROM_START__ = LOADADDR(.data);
 164     __DATA_SIZE__ = SIZEOF(.data);
 165
 166     /*
 167      * The .data section is the last PROGBITS section so its end marks the end
 168      * of BL1's actual content in Trusted ROM.
 169      */
 170     __BL1_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
 171     ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
 172            "BL1's ROM content has exceeded its limit.")
 173
 174     __BSS_SIZE__ = SIZEOF(.bss);
 175
 176 #if USE_COHERENT_MEM
 177     __COHERENT_RAM_UNALIGNED_SIZE__ =
 178         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
 179 #endif
 180
 181     ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
 182 }