bl1/bl1_main.c

   1 /*
   2  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8
   9 #include <platform_def.h>
  10
  11 #include <arch.h>
  12 #include <arch_helpers.h>
  13 #include <bl1/bl1.h>
  14 #include <common/bl_common.h>
  15 #include <common/debug.h>
  16 #include <drivers/auth/auth_mod.h>
  17 #include <drivers/console.h>
  18 #include <lib/cpus/errata_report.h>
  19 #include <lib/utils.h>
  20 #include <plat/common/platform.h>
  21 #include <smccc_helpers.h>
  22 #include <tools_share/uuid.h>
  23
  24 #include "bl1_private.h"
  25
  26 /* BL1 Service UUID */
  27 DEFINE_SVC_UUID2(bl1_svc_uid,
  28         0xd46739fd, 0xcb72, 0x9a4d, 0xb5, 0x75,
  29         0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
  30
  31 static void bl1_load_bl2(void);
  32
  33 /*******************************************************************************
  34  * Helper utility to calculate the BL2 memory layout taking into consideration
  35  * the BL1 RW data assuming that it is at the top of the memory layout.
  36  ******************************************************************************/
  37 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
  38                         meminfo_t *bl2_mem_layout)
  39 {
  40         assert(bl1_mem_layout != NULL);
  41         assert(bl2_mem_layout != NULL);
  42
  43         /*
  44          * Remove BL1 RW data from the scope of memory visible to BL2.
  45          * This is assuming BL1 RW data is at the top of bl1_mem_layout.
  46          */
  47         assert(BL1_RW_BASE > bl1_mem_layout->total_base);
  48         bl2_mem_layout->total_base = bl1_mem_layout->total_base;
  49         bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
  50
  51         flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
  52 }
  53
  54 /*******************************************************************************
  55  * Function to perform late architectural and platform specific initialization.
  56  * It also queries the platform to load and run next BL image. Only called
  57  * by the primary cpu after a cold boot.
  58  ******************************************************************************/
  59 void bl1_main(void)
  60 {
  61         unsigned int image_id;
  62
  63         /* Announce our arrival */
  64         NOTICE(FIRMWARE_WELCOME_STR);
  65         NOTICE("BL1: %s\n", version_string);
  66         NOTICE("BL1: %s\n", build_message);
  67
  68         INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
  69                                         (void *)BL1_RAM_LIMIT);
  70
  71         print_errata_status();
  72
  73 #if ENABLE_ASSERTIONS
  74         u_register_t val;
  75         /*
  76          * Ensure that MMU/Caches and coherency are turned on
  77          */
  78 #ifdef AARCH32
  79         val = read_sctlr();
  80 #else
  81         val = read_sctlr_el3();
  82 #endif
  83         assert(val & SCTLR_M_BIT);
  84         assert(val & SCTLR_C_BIT);
  85         assert(val & SCTLR_I_BIT);
  86         /*
  87          * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
  88          * provided platform value
  89          */
  90         val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
  91         /*
  92          * If CWG is zero, then no CWG information is available but we can
  93          * at least check the platform value is less than the architectural
  94          * maximum.
  95          */
  96         if (val != 0)
  97                 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
  98         else
  99                 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
 100 #endif /* ENABLE_ASSERTIONS */
 101
 102         /* Perform remaining generic architectural setup from EL3 */
 103         bl1_arch_setup();
 104
 105 #if TRUSTED_BOARD_BOOT
 106         /* Initialize authentication module */
 107         auth_mod_init();
 108 #endif /* TRUSTED_BOARD_BOOT */
 109
 110         /* Perform platform setup in BL1. */
 111         bl1_platform_setup();
 112
 113         /* Get the image id of next image to load and run. */
 114         image_id = bl1_plat_get_next_image_id();
 115
 116         /*
 117          * We currently interpret any image id other than
 118          * BL2_IMAGE_ID as the start of firmware update.
 119          */
 120         if (image_id == BL2_IMAGE_ID)
 121                 bl1_load_bl2();
 122         else
 123                 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
 124
 125         bl1_prepare_next_image(image_id);
 126
 127         console_flush();
 128 }
 129
 130 /*******************************************************************************
 131  * This function locates and loads the BL2 raw binary image in the trusted SRAM.
 132  * Called by the primary cpu after a cold boot.
 133  * TODO: Add support for alternative image load mechanism e.g using virtio/elf
 134  * loader etc.
 135  ******************************************************************************/
 136 static void bl1_load_bl2(void)
 137 {
 138         image_desc_t *image_desc;
 139         image_info_t *image_info;
 140         int err;
 141
 142         /* Get the image descriptor */
 143         image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
 144         assert(image_desc);
 145
 146         /* Get the image info */
 147         image_info = &image_desc->image_info;
 148         INFO("BL1: Loading BL2\n");
 149
 150         err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
 151         if (err) {
 152                 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
 153                 plat_error_handler(err);
 154         }
 155
 156         err = load_auth_image(BL2_IMAGE_ID, image_info);
 157         if (err) {
 158                 ERROR("Failed to load BL2 firmware.\n");
 159                 plat_error_handler(err);
 160         }
 161
 162         /* Allow platform to handle image information. */
 163         err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
 164         if (err) {
 165                 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
 166                 plat_error_handler(err);
 167         }
 168
 169         NOTICE("BL1: Booting BL2\n");
 170 }
 171
 172 /*******************************************************************************
 173  * Function called just before handing over to the next BL to inform the user
 174  * about the boot progress. In debug mode, also print details about the BL
 175  * image's execution context.
 176  ******************************************************************************/
 177 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
 178 {
 179 #ifdef AARCH32
 180         NOTICE("BL1: Booting BL32\n");
 181 #else
 182         NOTICE("BL1: Booting BL31\n");
 183 #endif /* AARCH32 */
 184         print_entry_point_info(bl_ep_info);
 185 }
 186
 187 #if SPIN_ON_BL1_EXIT
 188 void print_debug_loop_message(void)
 189 {
 190         NOTICE("BL1: Debug loop, spinning forever\n");
 191         NOTICE("BL1: Please connect the debugger to continue\n");
 192 }
 193 #endif
 194
 195 /*******************************************************************************
 196  * Top level handler for servicing BL1 SMCs.
 197  ******************************************************************************/
 198 register_t bl1_smc_handler(unsigned int smc_fid,
 199         register_t x1,
 200         register_t x2,
 201         register_t x3,
 202         register_t x4,
 203         void *cookie,
 204         void *handle,
 205         unsigned int flags)
 206 {
 207
 208 #if TRUSTED_BOARD_BOOT
 209         /*
 210          * Dispatch FWU calls to FWU SMC handler and return its return
 211          * value
 212          */
 213         if (is_fwu_fid(smc_fid)) {
 214                 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
 215                         handle, flags);
 216         }
 217 #endif
 218
 219         switch (smc_fid) {
 220         case BL1_SMC_CALL_COUNT:
 221                 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
 222
 223         case BL1_SMC_UID:
 224                 SMC_UUID_RET(handle, bl1_svc_uid);
 225
 226         case BL1_SMC_VERSION:
 227                 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
 228
 229         default:
 230                 break;
 231         }
 232
 233         WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
 234         SMC_RET1(handle, SMC_UNK);
 235 }
 236
 237 /*******************************************************************************
 238  * BL1 SMC wrapper.  This function is only used in AArch32 mode to ensure ABI
 239  * compliance when invoking bl1_smc_handler.
 240  ******************************************************************************/
 241 register_t bl1_smc_wrapper(uint32_t smc_fid,
 242         void *cookie,
 243         void *handle,
 244         unsigned int flags)
 245 {
 246         register_t x1, x2, x3, x4;
 247
 248         assert(handle);
 249
 250         get_smc_params_from_ctx(handle, x1, x2, x3, x4);
 251         return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
 252 }