2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
8 #include <asm_macros.S>
10 #include <el3_common_macros.S>
14 .globl bl2_run_next_image
18 /* Save arguments x0-x3 from previous Boot loader */
24 el3_entrypoint_common \
26 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
27 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
30 _exception_vectors=bl2_vector_table
33 * Restore parameters of boot rom
40 bl bl2_el3_early_platform_setup
41 bl bl2_el3_plat_arch_setup
43 /* ---------------------------------------------
44 * Jump to main function.
45 * ---------------------------------------------
49 /* ---------------------------------------------
50 * Should never reach this point.
51 * ---------------------------------------------
53 no_ret plat_panic_handler
55 endfunc bl2_entrypoint
57 func bl2_run_next_image
61 * MMU needs to be disabled because both BL2 and BL32 execute
62 * in PL1, and therefore share the same address space.
63 * BL32 will initialize the address space according to its
66 bl disable_mmu_icache_secure
71 bl bl2_el3_plat_prepare_exit
74 * Extract PC and SPSR based on struct `entry_point_info_t`
75 * and load it in LR and SPSR registers respectively.
77 ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
78 ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
81 /* Some BL32 stages expect lr_svc to provide the BL33 entry address */
83 ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
86 add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
87 ldm r8, {r0, r1, r2, r3}
89 endfunc bl2_run_next_image