2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
8 #include <asm_macros.S>
9 #include <common/bl_common.h>
17 /*---------------------------------------------
18 * Save arguments x0 - x3 from BL1 for future
20 * ---------------------------------------------
27 /* ---------------------------------------------
28 * Set the exception vector to something sane.
29 * ---------------------------------------------
31 adr x0, early_exceptions
35 /* ---------------------------------------------
36 * Enable the SError interrupt now that the
37 * exception vectors have been setup.
38 * ---------------------------------------------
40 msr daifclr, #DAIF_ABT_BIT
42 /* ---------------------------------------------
43 * Enable the instruction cache, stack pointer
44 * and data access alignment checks and disable
46 * ---------------------------------------------
48 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
51 bic x0, x0, #SCTLR_DSSBS_BIT
55 /* ---------------------------------------------
56 * Invalidate the RW memory used by the BL2
57 * image. This includes the data and NOBITS
58 * sections. This is done to safeguard against
59 * possible corruption of this memory by dirty
60 * cache lines in a system cache as a result of
61 * use by an earlier boot loader stage.
62 * ---------------------------------------------
69 /* ---------------------------------------------
70 * Zero out NOBITS sections. There are 2 of them:
72 * - the coherent memory section.
73 * ---------------------------------------------
75 adrp x0, __BSS_START__
76 add x0, x0, :lo12:__BSS_START__
78 add x1, x1, :lo12:__BSS_END__
83 adrp x0, __COHERENT_RAM_START__
84 add x0, x0, :lo12:__COHERENT_RAM_START__
85 adrp x1, __COHERENT_RAM_END_UNALIGNED__
86 add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
91 /* --------------------------------------------
92 * Allocate a stack whose memory will be marked
93 * as Normal-IS-WBWA when the MMU is enabled.
94 * There is no risk of reading stale stack
95 * memory after enabling the MMU as only the
96 * primary cpu is running at the moment.
97 * --------------------------------------------
101 /* ---------------------------------------------
102 * Initialize the stack protector canary before
103 * any C code is called.
104 * ---------------------------------------------
106 #if STACK_PROTECTOR_ENABLED
107 bl update_stack_protector_canary
110 /* ---------------------------------------------
112 * ---------------------------------------------
120 /* ---------------------------------------------
121 * Enable pointer authentication
122 * ---------------------------------------------
126 orr x0, x0, #SCTLR_EnIA_BIT
128 /* ---------------------------------------------
129 * Enable PAC branch type compatibility
130 * ---------------------------------------------
132 bic x0, x0, #(SCTLR_BT0_BIT | SCTLR_BT1_BIT)
133 #endif /* ENABLE_BTI */
136 #endif /* ENABLE_PAUTH */
138 /* ---------------------------------------------
139 * Jump to main function.
140 * ---------------------------------------------
144 /* ---------------------------------------------
145 * Should never reach this point.
146 * ---------------------------------------------
148 no_ret plat_panic_handler
150 endfunc bl2_entrypoint