bl2/aarch64/bl2_entrypoint.S

   1 /*
   2  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <asm_macros.S>
   9 #include <common/bl_common.h>
  10
  11
  12         .globl  bl2_entrypoint
  13
  14
  15
  16 func bl2_entrypoint
  17         /*---------------------------------------------
  18          * Save arguments x0 - x3 from BL1 for future
  19          * use.
  20          * ---------------------------------------------
  21          */
  22         mov     x20, x0
  23         mov     x21, x1
  24         mov     x22, x2
  25         mov     x23, x3
  26
  27         /* ---------------------------------------------
  28          * Set the exception vector to something sane.
  29          * ---------------------------------------------
  30          */
  31         adr     x0, early_exceptions
  32         msr     vbar_el1, x0
  33         isb
  34
  35         /* ---------------------------------------------
  36          * Enable the SError interrupt now that the
  37          * exception vectors have been setup.
  38          * ---------------------------------------------
  39          */
  40         msr     daifclr, #DAIF_ABT_BIT
  41
  42         /* ---------------------------------------------
  43          * Enable the instruction cache, stack pointer
  44          * and data access alignment checks
  45          * ---------------------------------------------
  46          */
  47         mov     x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
  48         mrs     x0, sctlr_el1
  49         orr     x0, x0, x1
  50         msr     sctlr_el1, x0
  51         isb
  52
  53         /* ---------------------------------------------
  54          * Invalidate the RW memory used by the BL2
  55          * image. This includes the data and NOBITS
  56          * sections. This is done to safeguard against
  57          * possible corruption of this memory by dirty
  58          * cache lines in a system cache as a result of
  59          * use by an earlier boot loader stage.
  60          * ---------------------------------------------
  61          */
  62         adr     x0, __RW_START__
  63         adr     x1, __RW_END__
  64         sub     x1, x1, x0
  65         bl      inv_dcache_range
  66
  67         /* ---------------------------------------------
  68          * Zero out NOBITS sections. There are 2 of them:
  69          *   - the .bss section;
  70          *   - the coherent memory section.
  71          * ---------------------------------------------
  72          */
  73         adrp    x0, __BSS_START__
  74         add     x0, x0, :lo12:__BSS_START__
  75         adrp    x1, __BSS_END__
  76         add     x1, x1, :lo12:__BSS_END__
  77         sub     x1, x1, x0
  78         bl      zeromem
  79
  80 #if USE_COHERENT_MEM
  81         adrp    x0, __COHERENT_RAM_START__
  82         add     x0, x0, :lo12:__COHERENT_RAM_START__
  83         adrp    x1, __COHERENT_RAM_END_UNALIGNED__
  84         add     x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
  85         sub     x1, x1, x0
  86         bl      zeromem
  87 #endif
  88
  89         /* --------------------------------------------
  90          * Allocate a stack whose memory will be marked
  91          * as Normal-IS-WBWA when the MMU is enabled.
  92          * There is no risk of reading stale stack
  93          * memory after enabling the MMU as only the
  94          * primary cpu is running at the moment.
  95          * --------------------------------------------
  96          */
  97         bl      plat_set_my_stack
  98
  99         /* ---------------------------------------------
 100          * Initialize the stack protector canary before
 101          * any C code is called.
 102          * ---------------------------------------------
 103          */
 104 #if STACK_PROTECTOR_ENABLED
 105         bl      update_stack_protector_canary
 106 #endif
 107
 108         /* ---------------------------------------------
 109          * Perform early platform setup & platform
 110          * specific early arch. setup e.g. mmu setup
 111          * ---------------------------------------------
 112          */
 113         mov     x0, x20
 114         mov     x1, x21
 115         mov     x2, x22
 116         mov     x3, x23
 117         bl      bl2_early_platform_setup2
 118
 119         bl      bl2_plat_arch_setup
 120
 121         /* ---------------------------------------------
 122          * Jump to main function.
 123          * ---------------------------------------------
 124          */
 125         bl      bl2_main
 126
 127         /* ---------------------------------------------
 128          * Should never reach this point.
 129          * ---------------------------------------------
 130          */
 131         no_ret  plat_panic_handler
 132
 133 endfunc bl2_entrypoint