2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
7 #include <platform_def.h>
8 #include <xlat_tables_defs.h>
10 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
17 RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
19 RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
28 ASSERT(. == ALIGN(PAGE_SIZE),
29 "BL2_RO_BASE address is not aligned on a page boundary.")
32 ASSERT(. == ALIGN(PAGE_SIZE),
33 "BL2_BASE address is not aligned on a page boundary.")
36 #if SEPARATE_CODE_AND_RODATA
39 __TEXT_RESIDENT_START__ = .;
40 *bl2_el3_entrypoint.o(.text*)
42 __TEXT_RESIDENT_END__ = .;
57 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
59 __PARSER_LIB_DESCS_START__ = .;
60 KEEP(*(.img_parser_lib_descs))
61 __PARSER_LIB_DESCS_END__ = .;
64 * Ensure 8-byte alignment for cpu_ops so that its fields are also
65 * aligned. Also ensure cpu_ops inclusion.
68 __CPU_OPS_START__ = .;
80 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
81 "Resident part of BL2 has exceeded its limit.")
85 __TEXT_RESIDENT_START__ = .;
86 *bl2_el3_entrypoint.o(.text*)
88 __TEXT_RESIDENT_END__ = .;
93 * Ensure 8-byte alignment for cpu_ops so that its fields are also
94 * aligned. Also ensure cpu_ops inclusion.
97 __CPU_OPS_START__ = .;
101 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
103 __PARSER_LIB_DESCS_START__ = .;
104 KEEP(*(.img_parser_lib_descs))
105 __PARSER_LIB_DESCS_END__ = .;
108 __RO_END_UNALIGNED__ = .;
110 * Memory page(s) mapped to this section will be marked as
111 * read-only, executable. No RW data from the next section must
112 * creep in. Ensure the rest of the current memory page is unused.
114 . = ALIGN(PAGE_SIZE);
124 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
125 "cpu_ops not defined for this platform.")
129 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
130 "BL2_RW_BASE address is not aligned on a page boundary.")
134 * Define a linker symbol to mark start of the RW memory area for this
140 * .data must be placed at a lower address than the stacks if the stack
141 * protector is enabled. Alternatively, the .data.stack_protector_canary
142 * section can be placed independently of the main .data section.
145 __DATA_RAM_START__ = .;
147 __DATA_RAM_END__ = .;
155 __STACKS_START__ = .;
156 *(tzfw_normal_stacks)
161 * The .bss section gets initialised to 0 at runtime.
162 * Its base address should be 16-byte aligned for better performance of the
163 * zero-initialization code.
167 *(SORT_BY_ALIGNMENT(.bss*))
173 * The xlat_table section is for full, aligned page tables (4K).
174 * Removing them from .bss avoids forcing 4K alignment on
175 * the .bss section. The tables are initialized to zero by the translation
178 xlat_table (NOLOAD) : {
184 * The base address of the coherent memory section must be page-aligned (4K)
185 * to guarantee that the coherent data are stored on their own pages and
186 * are not mixed with normal data. This is required to set up the correct
187 * memory attributes for the coherent data page tables.
189 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
190 __COHERENT_RAM_START__ = .;
192 __COHERENT_RAM_END_UNALIGNED__ = .;
194 * Memory page(s) mapped to this section will be marked
195 * as device memory. No other unexpected data must creep in.
196 * Ensure the rest of the current memory page is unused.
198 . = ALIGN(PAGE_SIZE);
199 __COHERENT_RAM_END__ = .;
204 * Define a linker symbol to mark end of the RW memory area for this
211 __BL2_RAM_START__ = ADDR(.data);
214 __DATA_ROM_START__ = LOADADDR(.data);
215 __DATA_SIZE__ = SIZEOF(.data);
218 * The .data section is the last PROGBITS section so its end marks the end
219 * of BL2's RO content in XIP memory..
221 __BL2_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
222 ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
223 "BL2's RO content has exceeded its limit.")
225 __BSS_SIZE__ = SIZEOF(.bss);
229 __COHERENT_RAM_UNALIGNED_SIZE__ =
230 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
234 ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
236 ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")