bl2/bl2_el3.ld.S

   1 /*
   2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8
   9 #include <lib/xlat_tables/xlat_tables_defs.h>
  10
  11 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
  12 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
  13 ENTRY(bl2_entrypoint)
  14
  15 MEMORY {
  16 #if BL2_IN_XIP_MEM
  17     ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
  18     RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
  19 #else
  20     RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
  21 #endif
  22 }
  23
  24
  25 SECTIONS
  26 {
  27 #if BL2_IN_XIP_MEM
  28     . = BL2_RO_BASE;
  29     ASSERT(. == ALIGN(PAGE_SIZE),
  30            "BL2_RO_BASE address is not aligned on a page boundary.")
  31 #else
  32     . = BL2_BASE;
  33     ASSERT(. == ALIGN(PAGE_SIZE),
  34            "BL2_BASE address is not aligned on a page boundary.")
  35 #endif
  36
  37 #if SEPARATE_CODE_AND_RODATA
  38     .text . : {
  39         __TEXT_START__ = .;
  40         __TEXT_RESIDENT_START__ = .;
  41         *bl2_el3_entrypoint.o(.text*)
  42         *(.text.asm.*)
  43         __TEXT_RESIDENT_END__ = .;
  44         *(.text*)
  45         *(.vectors)
  46         . = ALIGN(PAGE_SIZE);
  47         __TEXT_END__ = .;
  48 #if BL2_IN_XIP_MEM
  49      } >ROM
  50 #else
  51      } >RAM
  52 #endif
  53
  54     .rodata . : {
  55         __RODATA_START__ = .;
  56         *(.rodata*)
  57
  58         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  59         . = ALIGN(8);
  60         __PARSER_LIB_DESCS_START__ = .;
  61         KEEP(*(.img_parser_lib_descs))
  62         __PARSER_LIB_DESCS_END__ = .;
  63
  64         /*
  65          * Ensure 8-byte alignment for cpu_ops so that its fields are also
  66          * aligned. Also ensure cpu_ops inclusion.
  67          */
  68         . = ALIGN(8);
  69         __CPU_OPS_START__ = .;
  70         KEEP(*(cpu_ops))
  71         __CPU_OPS_END__ = .;
  72
  73         . = ALIGN(PAGE_SIZE);
  74         __RODATA_END__ = .;
  75 #if BL2_IN_XIP_MEM
  76     } >ROM
  77 #else
  78     } >RAM
  79 #endif
  80
  81     ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
  82           "Resident part of BL2 has exceeded its limit.")
  83 #else
  84     ro . : {
  85         __RO_START__ = .;
  86         __TEXT_RESIDENT_START__ = .;
  87         *bl2_el3_entrypoint.o(.text*)
  88         *(.text.asm.*)
  89         __TEXT_RESIDENT_END__ = .;
  90         *(.text*)
  91         *(.rodata*)
  92
  93         /*
  94          * Ensure 8-byte alignment for cpu_ops so that its fields are also
  95          * aligned. Also ensure cpu_ops inclusion.
  96          */
  97         . = ALIGN(8);
  98         __CPU_OPS_START__ = .;
  99         KEEP(*(cpu_ops))
 100         __CPU_OPS_END__ = .;
 101
 102         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
 103         . = ALIGN(8);
 104         __PARSER_LIB_DESCS_START__ = .;
 105         KEEP(*(.img_parser_lib_descs))
 106         __PARSER_LIB_DESCS_END__ = .;
 107
 108         *(.vectors)
 109         __RO_END_UNALIGNED__ = .;
 110         /*
 111          * Memory page(s) mapped to this section will be marked as
 112          * read-only, executable.  No RW data from the next section must
 113          * creep in.  Ensure the rest of the current memory page is unused.
 114          */
 115         . = ALIGN(PAGE_SIZE);
 116
 117         __RO_END__ = .;
 118 #if BL2_IN_XIP_MEM
 119     } >ROM
 120 #else
 121     } >RAM
 122 #endif
 123 #endif
 124
 125     ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
 126           "cpu_ops not defined for this platform.")
 127
 128 #if BL2_IN_XIP_MEM
 129     . = BL2_RW_BASE;
 130     ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
 131            "BL2_RW_BASE address is not aligned on a page boundary.")
 132 #endif
 133
 134     /*
 135      * Define a linker symbol to mark start of the RW memory area for this
 136      * image.
 137      */
 138     __RW_START__ = . ;
 139
 140     /*
 141      * .data must be placed at a lower address than the stacks if the stack
 142      * protector is enabled. Alternatively, the .data.stack_protector_canary
 143      * section can be placed independently of the main .data section.
 144      */
 145     .data . : {
 146         __DATA_RAM_START__ = .;
 147         *(.data*)
 148         __DATA_RAM_END__ = .;
 149 #if BL2_IN_XIP_MEM
 150     } >RAM AT>ROM
 151 #else
 152     } >RAM
 153 #endif
 154
 155     stacks (NOLOAD) : {
 156         __STACKS_START__ = .;
 157         *(tzfw_normal_stacks)
 158         __STACKS_END__ = .;
 159     } >RAM
 160
 161     /*
 162      * The .bss section gets initialised to 0 at runtime.
 163      * Its base address should be 16-byte aligned for better performance of the
 164      * zero-initialization code.
 165      */
 166     .bss : ALIGN(16) {
 167         __BSS_START__ = .;
 168         *(SORT_BY_ALIGNMENT(.bss*))
 169         *(COMMON)
 170         __BSS_END__ = .;
 171     } >RAM
 172
 173     /*
 174      * The xlat_table section is for full, aligned page tables (4K).
 175      * Removing them from .bss avoids forcing 4K alignment on
 176      * the .bss section. The tables are initialized to zero by the translation
 177      * tables library.
 178      */
 179     xlat_table (NOLOAD) : {
 180         *(xlat_table)
 181     } >RAM
 182
 183 #if USE_COHERENT_MEM
 184     /*
 185      * The base address of the coherent memory section must be page-aligned (4K)
 186      * to guarantee that the coherent data are stored on their own pages and
 187      * are not mixed with normal data.  This is required to set up the correct
 188      * memory attributes for the coherent data page tables.
 189      */
 190     coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
 191         __COHERENT_RAM_START__ = .;
 192         *(tzfw_coherent_mem)
 193         __COHERENT_RAM_END_UNALIGNED__ = .;
 194         /*
 195          * Memory page(s) mapped to this section will be marked
 196          * as device memory.  No other unexpected data must creep in.
 197          * Ensure the rest of the current memory page is unused.
 198          */
 199         . = ALIGN(PAGE_SIZE);
 200         __COHERENT_RAM_END__ = .;
 201     } >RAM
 202 #endif
 203
 204     /*
 205      * Define a linker symbol to mark end of the RW memory area for this
 206      * image.
 207      */
 208     __RW_END__ = .;
 209     __BL2_END__ = .;
 210
 211 #if BL2_IN_XIP_MEM
 212     __BL2_RAM_START__ = ADDR(.data);
 213     __BL2_RAM_END__ = .;
 214
 215     __DATA_ROM_START__ = LOADADDR(.data);
 216     __DATA_SIZE__ = SIZEOF(.data);
 217
 218     /*
 219      * The .data section is the last PROGBITS section so its end marks the end
 220      * of BL2's RO content in XIP memory..
 221      */
 222     __BL2_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
 223     ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
 224            "BL2's RO content has exceeded its limit.")
 225 #endif
 226     __BSS_SIZE__ = SIZEOF(.bss);
 227
 228
 229 #if USE_COHERENT_MEM
 230     __COHERENT_RAM_UNALIGNED_SIZE__ =
 231         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
 232 #endif
 233
 234 #if BL2_IN_XIP_MEM
 235     ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
 236 #else
 237     ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
 238 #endif
 239 }