bl31/bl31.ld.S

   1 /*
   2  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8 #include <xlat_tables_defs.h>
   9
  10 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
  11 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
  12 ENTRY(bl31_entrypoint)
  13
  14
  15 MEMORY {
  16     RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
  17 }
  18
  19 #ifdef PLAT_EXTRA_LD_SCRIPT
  20 #include <plat.ld.S>
  21 #endif
  22
  23 SECTIONS
  24 {
  25     . = BL31_BASE;
  26     ASSERT(. == ALIGN(PAGE_SIZE),
  27            "BL31_BASE address is not aligned on a page boundary.")
  28
  29 #if SEPARATE_CODE_AND_RODATA
  30     .text . : {
  31         __TEXT_START__ = .;
  32         *bl31_entrypoint.o(.text*)
  33         *(.text*)
  34         *(.vectors)
  35         . = ALIGN(PAGE_SIZE);
  36         __TEXT_END__ = .;
  37     } >RAM
  38
  39     .rodata . : {
  40         __RODATA_START__ = .;
  41         *(.rodata*)
  42
  43         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  44         . = ALIGN(8);
  45         __RT_SVC_DESCS_START__ = .;
  46         KEEP(*(rt_svc_descs))
  47         __RT_SVC_DESCS_END__ = .;
  48
  49 #if ENABLE_PMF
  50         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  51         . = ALIGN(8);
  52         __PMF_SVC_DESCS_START__ = .;
  53         KEEP(*(pmf_svc_descs))
  54         __PMF_SVC_DESCS_END__ = .;
  55 #endif /* ENABLE_PMF */
  56
  57         /*
  58          * Ensure 8-byte alignment for cpu_ops so that its fields are also
  59          * aligned. Also ensure cpu_ops inclusion.
  60          */
  61         . = ALIGN(8);
  62         __CPU_OPS_START__ = .;
  63         KEEP(*(cpu_ops))
  64         __CPU_OPS_END__ = .;
  65
  66         /* Place pubsub sections for events */
  67         . = ALIGN(8);
  68 #include <pubsub_events.h>
  69
  70         . = ALIGN(PAGE_SIZE);
  71         __RODATA_END__ = .;
  72     } >RAM
  73 #else
  74     ro . : {
  75         __RO_START__ = .;
  76         *bl31_entrypoint.o(.text*)
  77         *(.text*)
  78         *(.rodata*)
  79
  80         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  81         . = ALIGN(8);
  82         __RT_SVC_DESCS_START__ = .;
  83         KEEP(*(rt_svc_descs))
  84         __RT_SVC_DESCS_END__ = .;
  85
  86 #if ENABLE_PMF
  87         /* Ensure 8-byte alignment for descriptors and ensure inclusion */
  88         . = ALIGN(8);
  89         __PMF_SVC_DESCS_START__ = .;
  90         KEEP(*(pmf_svc_descs))
  91         __PMF_SVC_DESCS_END__ = .;
  92 #endif /* ENABLE_PMF */
  93
  94         /*
  95          * Ensure 8-byte alignment for cpu_ops so that its fields are also
  96          * aligned. Also ensure cpu_ops inclusion.
  97          */
  98         . = ALIGN(8);
  99         __CPU_OPS_START__ = .;
 100         KEEP(*(cpu_ops))
 101         __CPU_OPS_END__ = .;
 102
 103         /* Place pubsub sections for events */
 104         . = ALIGN(8);
 105 #include <pubsub_events.h>
 106
 107         *(.vectors)
 108         __RO_END_UNALIGNED__ = .;
 109         /*
 110          * Memory page(s) mapped to this section will be marked as read-only,
 111          * executable.  No RW data from the next section must creep in.
 112          * Ensure the rest of the current memory page is unused.
 113          */
 114         . = ALIGN(PAGE_SIZE);
 115         __RO_END__ = .;
 116     } >RAM
 117 #endif
 118
 119     ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
 120            "cpu_ops not defined for this platform.")
 121
 122 #if ENABLE_SPM
 123     /*
 124      * Exception vectors of the SPM shim layer. They must be aligned to a 2K
 125      * address, but we need to place them in a separate page so that we can set
 126      * individual permissions to them, so the actual alignment needed is 4K.
 127      *
 128      * There's no need to include this into the RO section of BL31 because it
 129      * doesn't need to be accessed by BL31.
 130      */
 131     spm_shim_exceptions : ALIGN(PAGE_SIZE) {
 132         __SPM_SHIM_EXCEPTIONS_START__ = .;
 133         *(.spm_shim_exceptions)
 134         . = ALIGN(PAGE_SIZE);
 135         __SPM_SHIM_EXCEPTIONS_END__ = .;
 136     } >RAM
 137 #endif
 138
 139     /*
 140      * Define a linker symbol to mark start of the RW memory area for this
 141      * image.
 142      */
 143     __RW_START__ = . ;
 144
 145     /*
 146      * .data must be placed at a lower address than the stacks if the stack
 147      * protector is enabled. Alternatively, the .data.stack_protector_canary
 148      * section can be placed independently of the main .data section.
 149      */
 150    .data . : {
 151         __DATA_START__ = .;
 152         *(.data*)
 153         __DATA_END__ = .;
 154     } >RAM
 155
 156 #ifdef BL31_PROGBITS_LIMIT
 157     ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
 158 #endif
 159
 160     stacks (NOLOAD) : {
 161         __STACKS_START__ = .;
 162         *(tzfw_normal_stacks)
 163         __STACKS_END__ = .;
 164     } >RAM
 165
 166     /*
 167      * The .bss section gets initialised to 0 at runtime.
 168      * Its base address should be 16-byte aligned for better performance of the
 169      * zero-initialization code.
 170      */
 171     .bss (NOLOAD) : ALIGN(16) {
 172         __BSS_START__ = .;
 173         *(.bss*)
 174         *(COMMON)
 175 #if !USE_COHERENT_MEM
 176         /*
 177          * Bakery locks are stored in normal .bss memory
 178          *
 179          * Each lock's data is spread across multiple cache lines, one per CPU,
 180          * but multiple locks can share the same cache line.
 181          * The compiler will allocate enough memory for one CPU's bakery locks,
 182          * the remaining cache lines are allocated by the linker script
 183          */
 184         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 185         __BAKERY_LOCK_START__ = .;
 186         *(bakery_lock)
 187         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 188         __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
 189         . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
 190         __BAKERY_LOCK_END__ = .;
 191 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
 192     ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
 193         "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
 194 #endif
 195 #endif
 196
 197 #if ENABLE_PMF
 198         /*
 199          * Time-stamps are stored in normal .bss memory
 200          *
 201          * The compiler will allocate enough memory for one CPU's time-stamps,
 202          * the remaining memory for other CPU's is allocated by the
 203          * linker script
 204          */
 205         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 206         __PMF_TIMESTAMP_START__ = .;
 207         KEEP(*(pmf_timestamp_array))
 208         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 209         __PMF_PERCPU_TIMESTAMP_END__ = .;
 210         __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
 211         . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
 212         __PMF_TIMESTAMP_END__ = .;
 213 #endif /* ENABLE_PMF */
 214         __BSS_END__ = .;
 215     } >RAM
 216
 217     /*
 218      * The xlat_table section is for full, aligned page tables (4K).
 219      * Removing them from .bss avoids forcing 4K alignment on
 220      * the .bss section. The tables are initialized to zero by the translation
 221      * tables library.
 222      */
 223     xlat_table (NOLOAD) : {
 224         *(xlat_table)
 225     } >RAM
 226
 227 #if USE_COHERENT_MEM
 228     /*
 229      * The base address of the coherent memory section must be page-aligned (4K)
 230      * to guarantee that the coherent data are stored on their own pages and
 231      * are not mixed with normal data.  This is required to set up the correct
 232      * memory attributes for the coherent data page tables.
 233      */
 234     coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
 235         __COHERENT_RAM_START__ = .;
 236         /*
 237          * Bakery locks are stored in coherent memory
 238          *
 239          * Each lock's data is contiguous and fully allocated by the compiler
 240          */
 241         *(bakery_lock)
 242         *(tzfw_coherent_mem)
 243         __COHERENT_RAM_END_UNALIGNED__ = .;
 244         /*
 245          * Memory page(s) mapped to this section will be marked
 246          * as device memory.  No other unexpected data must creep in.
 247          * Ensure the rest of the current memory page is unused.
 248          */
 249         . = ALIGN(PAGE_SIZE);
 250         __COHERENT_RAM_END__ = .;
 251     } >RAM
 252 #endif
 253
 254     /*
 255      * Define a linker symbol to mark end of the RW memory area for this
 256      * image.
 257      */
 258     __RW_END__ = .;
 259     __BL31_END__ = .;
 260
 261     __BSS_SIZE__ = SIZEOF(.bss);
 262 #if USE_COHERENT_MEM
 263     __COHERENT_RAM_UNALIGNED_SIZE__ =
 264         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
 265 #endif
 266
 267     ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
 268 }