bl32/sp_min/sp_min.ld.S

   1 /*
   2  * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <platform_def.h>
   8 #include <xlat_tables_defs.h>
   9
  10 OUTPUT_FORMAT(elf32-littlearm)
  11 OUTPUT_ARCH(arm)
  12 ENTRY(sp_min_vector_table)
  13
  14 MEMORY {
  15     RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE
  16 }
  17
  18
  19 SECTIONS
  20 {
  21     . = BL32_BASE;
  22    ASSERT(. == ALIGN(PAGE_SIZE),
  23           "BL32_BASE address is not aligned on a page boundary.")
  24
  25 #if SEPARATE_CODE_AND_RODATA
  26     .text . : {
  27         __TEXT_START__ = .;
  28         *entrypoint.o(.text*)
  29         *(.text*)
  30         *(.vectors)
  31         . = NEXT(PAGE_SIZE);
  32         __TEXT_END__ = .;
  33     } >RAM
  34
  35     .rodata . : {
  36         __RODATA_START__ = .;
  37         *(.rodata*)
  38
  39         /* Ensure 4-byte alignment for descriptors and ensure inclusion */
  40         . = ALIGN(4);
  41         __RT_SVC_DESCS_START__ = .;
  42         KEEP(*(rt_svc_descs))
  43         __RT_SVC_DESCS_END__ = .;
  44
  45         /*
  46          * Ensure 4-byte alignment for cpu_ops so that its fields are also
  47          * aligned. Also ensure cpu_ops inclusion.
  48          */
  49         . = ALIGN(4);
  50         __CPU_OPS_START__ = .;
  51         KEEP(*(cpu_ops))
  52         __CPU_OPS_END__ = .;
  53
  54         /* Place pubsub sections for events */
  55         . = ALIGN(8);
  56 #include <pubsub_events.h>
  57
  58         . = NEXT(PAGE_SIZE);
  59         __RODATA_END__ = .;
  60     } >RAM
  61 #else
  62     ro . : {
  63         __RO_START__ = .;
  64         *entrypoint.o(.text*)
  65         *(.text*)
  66         *(.rodata*)
  67
  68         /* Ensure 4-byte alignment for descriptors and ensure inclusion */
  69         . = ALIGN(4);
  70         __RT_SVC_DESCS_START__ = .;
  71         KEEP(*(rt_svc_descs))
  72         __RT_SVC_DESCS_END__ = .;
  73
  74         /*
  75          * Ensure 4-byte alignment for cpu_ops so that its fields are also
  76          * aligned. Also ensure cpu_ops inclusion.
  77          */
  78         . = ALIGN(4);
  79         __CPU_OPS_START__ = .;
  80         KEEP(*(cpu_ops))
  81         __CPU_OPS_END__ = .;
  82
  83         /* Place pubsub sections for events */
  84         . = ALIGN(8);
  85 #include <pubsub_events.h>
  86
  87         *(.vectors)
  88         __RO_END_UNALIGNED__ = .;
  89
  90         /*
  91          * Memory page(s) mapped to this section will be marked as
  92          * read-only, executable.  No RW data from the next section must
  93          * creep in.  Ensure the rest of the current memory block is unused.
  94          */
  95         . = NEXT(PAGE_SIZE);
  96         __RO_END__ = .;
  97     } >RAM
  98 #endif
  99
 100     ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
 101            "cpu_ops not defined for this platform.")
 102     /*
 103      * Define a linker symbol to mark start of the RW memory area for this
 104      * image.
 105      */
 106     __RW_START__ = . ;
 107
 108     .data . : {
 109         __DATA_START__ = .;
 110         *(.data*)
 111         __DATA_END__ = .;
 112     } >RAM
 113
 114     stacks (NOLOAD) : {
 115         __STACKS_START__ = .;
 116         *(tzfw_normal_stacks)
 117         __STACKS_END__ = .;
 118     } >RAM
 119
 120     /*
 121      * The .bss section gets initialised to 0 at runtime.
 122      * Its base address should be 8-byte aligned for better performance of the
 123      * zero-initialization code.
 124      */
 125     .bss (NOLOAD) : ALIGN(8) {
 126         __BSS_START__ = .;
 127         *(.bss*)
 128         *(COMMON)
 129 #if !USE_COHERENT_MEM
 130         /*
 131          * Bakery locks are stored in normal .bss memory
 132          *
 133          * Each lock's data is spread across multiple cache lines, one per CPU,
 134          * but multiple locks can share the same cache line.
 135          * The compiler will allocate enough memory for one CPU's bakery locks,
 136          * the remaining cache lines are allocated by the linker script
 137          */
 138         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 139         __BAKERY_LOCK_START__ = .;
 140         *(bakery_lock)
 141         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 142         __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
 143         . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
 144         __BAKERY_LOCK_END__ = .;
 145 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
 146     ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
 147         "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
 148 #endif
 149 #endif
 150
 151 #if ENABLE_PMF
 152         /*
 153          * Time-stamps are stored in normal .bss memory
 154          *
 155          * The compiler will allocate enough memory for one CPU's time-stamps,
 156          * the remaining memory for other CPU's is allocated by the
 157          * linker script
 158          */
 159         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 160         __PMF_TIMESTAMP_START__ = .;
 161         KEEP(*(pmf_timestamp_array))
 162         . = ALIGN(CACHE_WRITEBACK_GRANULE);
 163         __PMF_PERCPU_TIMESTAMP_END__ = .;
 164         __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
 165         . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
 166         __PMF_TIMESTAMP_END__ = .;
 167 #endif /* ENABLE_PMF */
 168
 169         __BSS_END__ = .;
 170     } >RAM
 171
 172     /*
 173      * The xlat_table section is for full, aligned page tables (4K).
 174      * Removing them from .bss avoids forcing 4K alignment on
 175      * the .bss section and eliminates the unecessary zero init
 176      */
 177     xlat_table (NOLOAD) : {
 178         *(xlat_table)
 179     } >RAM
 180
 181      __BSS_SIZE__ = SIZEOF(.bss);
 182
 183 #if USE_COHERENT_MEM
 184     /*
 185      * The base address of the coherent memory section must be page-aligned (4K)
 186      * to guarantee that the coherent data are stored on their own pages and
 187      * are not mixed with normal data.  This is required to set up the correct
 188      * memory attributes for the coherent data page tables.
 189      */
 190     coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
 191         __COHERENT_RAM_START__ = .;
 192         /*
 193          * Bakery locks are stored in coherent memory
 194          *
 195          * Each lock's data is contiguous and fully allocated by the compiler
 196          */
 197         *(bakery_lock)
 198         *(tzfw_coherent_mem)
 199         __COHERENT_RAM_END_UNALIGNED__ = .;
 200         /*
 201          * Memory page(s) mapped to this section will be marked
 202          * as device memory.  No other unexpected data must creep in.
 203          * Ensure the rest of the current memory page is unused.
 204          */
 205         . = NEXT(PAGE_SIZE);
 206         __COHERENT_RAM_END__ = .;
 207     } >RAM
 208
 209     __COHERENT_RAM_UNALIGNED_SIZE__ =
 210         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
 211 #endif
 212
 213     /*
 214      * Define a linker symbol to mark end of the RW memory area for this
 215      * image.
 216      */
 217     __RW_END__ = .;
 218
 219    __BL32_END__ = .;
 220 }