bl32/tsp/tsp.ld.S

   1 /*
   2  * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <lib/xlat_tables/xlat_tables_defs.h>
   8 #include <platform_def.h>
   9
  10 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
  11 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
  12 ENTRY(tsp_entrypoint)
  13
  14
  15 MEMORY {
  16     RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
  17 }
  18
  19
  20 SECTIONS
  21 {
  22     . = BL32_BASE;
  23     ASSERT(. == ALIGN(PAGE_SIZE),
  24            "BL32_BASE address is not aligned on a page boundary.")
  25
  26 #if SEPARATE_CODE_AND_RODATA
  27     .text . : {
  28         __TEXT_START__ = .;
  29         *tsp_entrypoint.o(.text*)
  30         *(.text*)
  31         *(.vectors)
  32         . = ALIGN(PAGE_SIZE);
  33         __TEXT_END__ = .;
  34     } >RAM
  35
  36     .rodata . : {
  37         __RODATA_START__ = .;
  38         *(.rodata*)
  39         . = ALIGN(PAGE_SIZE);
  40         __RODATA_END__ = .;
  41     } >RAM
  42 #else
  43     ro . : {
  44         __RO_START__ = .;
  45         *tsp_entrypoint.o(.text*)
  46         *(.text*)
  47         *(.rodata*)
  48         *(.vectors)
  49         __RO_END_UNALIGNED__ = .;
  50         /*
  51          * Memory page(s) mapped to this section will be marked as
  52          * read-only, executable.  No RW data from the next section must
  53          * creep in.  Ensure the rest of the current memory page is unused.
  54          */
  55         . = ALIGN(PAGE_SIZE);
  56         __RO_END__ = .;
  57     } >RAM
  58 #endif
  59
  60     /*
  61      * Define a linker symbol to mark start of the RW memory area for this
  62      * image.
  63      */
  64     __RW_START__ = . ;
  65
  66     .data . : {
  67         __DATA_START__ = .;
  68         *(.data*)
  69         __DATA_END__ = .;
  70     } >RAM
  71
  72 #ifdef TSP_PROGBITS_LIMIT
  73     ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
  74 #endif
  75
  76     stacks (NOLOAD) : {
  77         __STACKS_START__ = .;
  78         *(tzfw_normal_stacks)
  79         __STACKS_END__ = .;
  80     } >RAM
  81
  82     /*
  83      * The .bss section gets initialised to 0 at runtime.
  84      * Its base address should be 16-byte aligned for better performance of the
  85      * zero-initialization code.
  86      */
  87     .bss : ALIGN(16) {
  88         __BSS_START__ = .;
  89         *(SORT_BY_ALIGNMENT(.bss*))
  90         *(COMMON)
  91         __BSS_END__ = .;
  92     } >RAM
  93
  94     /*
  95      * The xlat_table section is for full, aligned page tables (4K).
  96      * Removing them from .bss avoids forcing 4K alignment on
  97      * the .bss section. The tables are initialized to zero by the translation
  98      * tables library.
  99      */
 100     xlat_table (NOLOAD) : {
 101         *(xlat_table)
 102     } >RAM
 103
 104 #if USE_COHERENT_MEM
 105     /*
 106      * The base address of the coherent memory section must be page-aligned (4K)
 107      * to guarantee that the coherent data are stored on their own pages and
 108      * are not mixed with normal data.  This is required to set up the correct
 109      * memory attributes for the coherent data page tables.
 110      */
 111     coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
 112         __COHERENT_RAM_START__ = .;
 113         *(tzfw_coherent_mem)
 114         __COHERENT_RAM_END_UNALIGNED__ = .;
 115         /*
 116          * Memory page(s) mapped to this section will be marked
 117          * as device memory.  No other unexpected data must creep in.
 118          * Ensure the rest of the current memory page is unused.
 119          */
 120         . = ALIGN(PAGE_SIZE);
 121         __COHERENT_RAM_END__ = .;
 122     } >RAM
 123 #endif
 124
 125     /*
 126      * Define a linker symbol to mark the end of the RW memory area for this
 127      * image.
 128      */
 129     __RW_END__ = .;
 130     __BL32_END__ = .;
 131
 132     __BSS_SIZE__ = SIZEOF(.bss);
 133 #if USE_COHERENT_MEM
 134     __COHERENT_RAM_UNALIGNED_SIZE__ =
 135         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
 136 #endif
 137
 138     ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
 139 }