1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
11 #include <environment.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <dm/uclass.h>
19 #include <fdt_support.h>
22 #ifdef CONFIG_ATSHA204A
23 # include <atsha204a-i2c.h>
26 #ifdef CONFIG_WDT_ORION
30 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
31 #include <../serdes/a38x/high_speed_env_spec.h>
33 DECLARE_GLOBAL_DATA_PTR
;
35 #define OMNIA_I2C_EEPROM_DM_NAME "i2c@11000->i2cmux@70->i2c@0"
36 #define OMNIA_I2C_EEPROM 0x54
37 #define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0
38 #define OMNIA_I2C_EEPROM_ADDRLEN 2
39 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
41 #define OMNIA_I2C_MCU_DM_NAME "i2c@11000->i2cmux@70->i2c@0"
42 #define OMNIA_I2C_MCU_ADDR_STATUS 0x1
43 #define OMNIA_I2C_MCU_SATA 0x20
44 #define OMNIA_I2C_MCU_CARDDET 0x10
45 #define OMNIA_I2C_MCU 0x2a
46 #define OMNIA_I2C_MCU_WDT_ADDR 0x0b
48 #define OMNIA_ATSHA204_OTP_VERSION 0
49 #define OMNIA_ATSHA204_OTP_SERIAL 1
50 #define OMNIA_ATSHA204_OTP_MAC0 3
51 #define OMNIA_ATSHA204_OTP_MAC1 4
53 #define MVTWSI_ARMADA_DEBUG_REG 0x8c
56 * Those values and defines are taken from the Marvell U-Boot version
57 * "u-boot-2013.01-2014_T3.0"
59 #define OMNIA_GPP_OUT_ENA_LOW \
60 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
61 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
62 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
63 #define OMNIA_GPP_OUT_ENA_MID \
64 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
65 BIT(16) | BIT(17) | BIT(18)))
67 #define OMNIA_GPP_OUT_VAL_LOW 0x0
68 #define OMNIA_GPP_OUT_VAL_MID 0x0
69 #define OMNIA_GPP_POL_LOW 0x0
70 #define OMNIA_GPP_POL_MID 0x0
72 static struct serdes_map board_serdes_map_pex
[] = {
73 {PEX0
, SERDES_SPEED_5_GBPS
, PEX_ROOT_COMPLEX_X1
, 0, 0},
74 {USB3_HOST0
, SERDES_SPEED_5_GBPS
, SERDES_DEFAULT_MODE
, 0, 0},
75 {PEX1
, SERDES_SPEED_5_GBPS
, PEX_ROOT_COMPLEX_X1
, 0, 0},
76 {USB3_HOST1
, SERDES_SPEED_5_GBPS
, SERDES_DEFAULT_MODE
, 0, 0},
77 {PEX2
, SERDES_SPEED_5_GBPS
, PEX_ROOT_COMPLEX_X1
, 0, 0},
78 {SGMII2
, SERDES_SPEED_1_25_GBPS
, SERDES_DEFAULT_MODE
, 0, 0}
81 static struct serdes_map board_serdes_map_sata
[] = {
82 {SATA0
, SERDES_SPEED_6_GBPS
, SERDES_DEFAULT_MODE
, 0, 0},
83 {USB3_HOST0
, SERDES_SPEED_5_GBPS
, SERDES_DEFAULT_MODE
, 0, 0},
84 {PEX1
, SERDES_SPEED_5_GBPS
, PEX_ROOT_COMPLEX_X1
, 0, 0},
85 {USB3_HOST1
, SERDES_SPEED_5_GBPS
, SERDES_DEFAULT_MODE
, 0, 0},
86 {PEX2
, SERDES_SPEED_5_GBPS
, PEX_ROOT_COMPLEX_X1
, 0, 0},
87 {SGMII2
, SERDES_SPEED_1_25_GBPS
, SERDES_DEFAULT_MODE
, 0, 0}
90 static bool omnia_detect_sata(void)
92 struct udevice
*bus
, *dev
;
96 puts("SERDES0 card detect: ");
98 if (uclass_get_device_by_name(UCLASS_I2C
, OMNIA_I2C_MCU_DM_NAME
, &bus
)) {
99 puts("Cannot find MCU bus!\n");
103 ret
= i2c_get_chip(bus
, OMNIA_I2C_MCU
, 1, &dev
);
105 puts("Cannot get MCU chip!\n");
109 for (; retry
> 0; --retry
) {
110 ret
= dm_i2c_read(dev
, OMNIA_I2C_MCU_ADDR_STATUS
, (uchar
*) &mode
, 2);
116 puts("I2C read failed! Default PEX\n");
120 if (!(mode
& OMNIA_I2C_MCU_CARDDET
)) {
125 if (mode
& OMNIA_I2C_MCU_SATA
) {
134 int hws_board_topology_load(struct serdes_map
**serdes_map_array
, u8
*count
)
136 if (omnia_detect_sata()) {
137 *serdes_map_array
= board_serdes_map_sata
;
138 *count
= ARRAY_SIZE(board_serdes_map_sata
);
140 *serdes_map_array
= board_serdes_map_pex
;
141 *count
= ARRAY_SIZE(board_serdes_map_pex
);
147 struct omnia_eeprom
{
154 static bool omnia_read_eeprom(struct omnia_eeprom
*oep
)
156 struct udevice
*bus
, *dev
;
157 int ret
, crc
, retry
= 3;
159 if (uclass_get_device_by_name(UCLASS_I2C
, OMNIA_I2C_EEPROM_DM_NAME
, &bus
)) {
160 puts("Cannot find EEPROM bus\n");
164 ret
= i2c_get_chip(bus
, OMNIA_I2C_EEPROM
, OMNIA_I2C_EEPROM_ADDRLEN
, &dev
);
166 puts("Cannot get EEPROM chip\n");
170 for (; retry
> 0; --retry
) {
171 ret
= dm_i2c_read(dev
, OMNIA_I2C_EEPROM_CONFIG_ADDR
, (uchar
*) oep
, sizeof(struct omnia_eeprom
));
175 if (oep
->magic
!= OMNIA_I2C_EEPROM_MAGIC
) {
176 puts("I2C EEPROM missing magic number!\n");
180 crc
= crc32(0, (unsigned char *) oep
,
181 sizeof(struct omnia_eeprom
) - 4);
182 if (crc
== oep
->crc
) {
185 printf("CRC of EEPROM memory config failed! "
186 "calc=0x%04x saved=0x%04x\n", crc
, oep
->crc
);
191 puts("I2C EEPROM read failed!\n");
199 * Define the DDR layout / topology here in the board file. This will
200 * be used by the DDR3 init code in the SPL U-Boot version to configure
201 * the DDR3 controller.
203 static struct mv_ddr_topology_map board_topology_map_1g
= {
205 0x1, /* active interfaces */
206 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
207 { { { {0x1, 0, 0, 0},
212 SPEED_BIN_DDR_1600K
, /* speed_bin */
213 MV_DDR_DEV_WIDTH_16BIT
, /* memory_width */
214 MV_DDR_DIE_CAP_4GBIT
, /* mem_size */
215 MV_DDR_FREQ_800
, /* frequency */
216 0, 0, /* cas_wl cas_l */
217 MV_DDR_TEMP_NORMAL
, /* temperature */
218 MV_DDR_TIM_2T
} }, /* timing */
219 BUS_MASK_32BIT
, /* Busses mask */
220 MV_DDR_CFG_DEFAULT
, /* ddr configuration data source */
221 { {0} }, /* raw spd data */
222 {0} /* timing parameters */
225 static struct mv_ddr_topology_map board_topology_map_2g
= {
227 0x1, /* active interfaces */
228 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
229 { { { {0x1, 0, 0, 0},
234 SPEED_BIN_DDR_1600K
, /* speed_bin */
235 MV_DDR_DEV_WIDTH_16BIT
, /* memory_width */
236 MV_DDR_DIE_CAP_8GBIT
, /* mem_size */
237 MV_DDR_FREQ_800
, /* frequency */
238 0, 0, /* cas_wl cas_l */
239 MV_DDR_TEMP_NORMAL
, /* temperature */
240 MV_DDR_TIM_2T
} }, /* timing */
241 BUS_MASK_32BIT
, /* Busses mask */
242 MV_DDR_CFG_DEFAULT
, /* ddr configuration data source */
243 { {0} }, /* raw spd data */
244 {0} /* timing parameters */
247 struct mv_ddr_topology_map
*mv_ddr_topology_map_get(void)
250 struct omnia_eeprom oep
;
252 /* Get the board config from EEPROM */
254 if(!omnia_read_eeprom(&oep
))
257 printf("Memory config in EEPROM: 0x%02x\n", oep
.ramsize
);
259 if (oep
.ramsize
== 0x2)
266 /* Hardcoded fallback */
268 puts("WARNING: Memory config from EEPROM read failed.\n");
269 puts("Falling back to default 1GiB map.\n");
273 /* Return the board topology as defined in the board code */
275 return &board_topology_map_1g
;
277 return &board_topology_map_2g
;
279 return &board_topology_map_1g
;
282 #ifndef CONFIG_SPL_BUILD
283 static int set_regdomain(void)
285 struct omnia_eeprom oep
;
286 char rd
[3] = {' ', ' ', 0};
288 if (omnia_read_eeprom(&oep
))
289 memcpy(rd
, &oep
.region
, 2);
291 puts("EEPROM regdomain read failed.\n");
293 printf("Regdomain set to %s\n", rd
);
294 return env_set("regdomain", rd
);
298 int board_early_init_f(void)
303 writel(0x11111111, MVEBU_MPP_BASE
+ 0x00);
304 writel(0x11111111, MVEBU_MPP_BASE
+ 0x04);
305 writel(0x11244011, MVEBU_MPP_BASE
+ 0x08);
306 writel(0x22222111, MVEBU_MPP_BASE
+ 0x0c);
307 writel(0x22200002, MVEBU_MPP_BASE
+ 0x10);
308 writel(0x30042022, MVEBU_MPP_BASE
+ 0x14);
309 writel(0x55550555, MVEBU_MPP_BASE
+ 0x18);
310 writel(0x00005550, MVEBU_MPP_BASE
+ 0x1c);
312 /* Set GPP Out value */
313 writel(OMNIA_GPP_OUT_VAL_LOW
, MVEBU_GPIO0_BASE
+ 0x00);
314 writel(OMNIA_GPP_OUT_VAL_MID
, MVEBU_GPIO1_BASE
+ 0x00);
316 /* Set GPP Polarity */
317 writel(OMNIA_GPP_POL_LOW
, MVEBU_GPIO0_BASE
+ 0x0c);
318 writel(OMNIA_GPP_POL_MID
, MVEBU_GPIO1_BASE
+ 0x0c);
320 /* Set GPP Out Enable */
321 writel(OMNIA_GPP_OUT_ENA_LOW
, MVEBU_GPIO0_BASE
+ 0x04);
322 writel(OMNIA_GPP_OUT_ENA_MID
, MVEBU_GPIO1_BASE
+ 0x04);
325 * Disable I2C debug mode blocking 0x64 I2C address.
326 * Note: that would be redundant once Turris Omnia migrates to DM_I2C,
327 * because the mvtwsi driver includes equivalent code.
329 i2c_debug_reg
= readl(MVEBU_TWSI_BASE
+ MVTWSI_ARMADA_DEBUG_REG
);
330 i2c_debug_reg
&= ~(1<<18);
331 writel(i2c_debug_reg
, MVEBU_TWSI_BASE
+ MVTWSI_ARMADA_DEBUG_REG
);
336 #ifndef CONFIG_SPL_BUILD
337 static bool disable_mcu_watchdog(void)
339 struct udevice
*bus
, *dev
;
341 uchar buf
[1] = {0x0};
343 if (uclass_get_device_by_name(UCLASS_I2C
, OMNIA_I2C_MCU_DM_NAME
, &bus
)) {
344 puts("Cannot find MCU bus! Can not disable MCU WDT.\n");
348 ret
= i2c_get_chip(bus
, OMNIA_I2C_MCU
, 1, &dev
);
350 puts("Cannot get MCU chip! Can not disable MCU WDT.\n");
354 for (; retry
> 0; --retry
)
355 if (!dm_i2c_write(dev
, OMNIA_I2C_MCU_WDT_ADDR
, (uchar
*) buf
, 1))
359 puts("I2C MCU watchdog failed to disable!\n");
369 /* adress of boot parameters */
370 gd
->bd
->bi_boot_params
= mvebu_sdram_bar(0) + 0x100;
372 #ifndef CONFIG_SPL_BUILD
373 if (disable_mcu_watchdog())
374 puts("Disabled MCU startup watchdog.\n");
382 int board_late_init(void)
384 #ifndef CONFIG_SPL_BUILD
391 #ifdef CONFIG_ATSHA204A
392 static struct udevice
*get_atsha204a_dev(void)
394 static struct udevice
*dev
= NULL
;
399 if (uclass_get_device_by_name(UCLASS_MISC
, "atsha204a@64", &dev
)) {
400 puts("Cannot find ATSHA204A on I2C bus!\n");
410 u32 version_num
, serial_num
;
413 #ifdef CONFIG_ATSHA204A
414 struct udevice
*dev
= get_atsha204a_dev();
417 err
= atsha204a_wakeup(dev
);
421 err
= atsha204a_read(dev
, ATSHA204A_ZONE_OTP
, false,
422 OMNIA_ATSHA204_OTP_VERSION
,
423 (u8
*) &version_num
);
427 err
= atsha204a_read(dev
, ATSHA204A_ZONE_OTP
, false,
428 OMNIA_ATSHA204_OTP_SERIAL
,
433 atsha204a_sleep(dev
);
440 printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
442 printf("Board: Turris Omnia SNL %08X%08X\n",
443 be32_to_cpu(version_num
), be32_to_cpu(serial_num
));
448 static void increment_mac(u8
*mac
)
452 for (i
= 5; i
>= 3; i
--) {
459 int misc_init_r(void)
461 #ifdef CONFIG_ATSHA204A
463 struct udevice
*dev
= get_atsha204a_dev();
464 u8 mac0
[4], mac1
[4], mac
[6];
469 err
= atsha204a_wakeup(dev
);
473 err
= atsha204a_read(dev
, ATSHA204A_ZONE_OTP
, false,
474 OMNIA_ATSHA204_OTP_MAC0
, mac0
);
478 err
= atsha204a_read(dev
, ATSHA204A_ZONE_OTP
, false,
479 OMNIA_ATSHA204_OTP_MAC1
, mac1
);
483 atsha204a_sleep(dev
);
492 if (is_valid_ethaddr(mac
))
493 eth_env_set_enetaddr("ethaddr", mac
);
497 if (is_valid_ethaddr(mac
))
498 eth_env_set_enetaddr("eth1addr", mac
);
502 if (is_valid_ethaddr(mac
))
503 eth_env_set_enetaddr("eth2addr", mac
);