sh: ap_sh4a_4a: Remove the board
[project/bcm63xx/u-boot.git] / board / renesas / ap325rxa / lowlevel_init.S
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
5 *
6 * board/ap325rxa/lowlevel_init.S
7 */
8
9 #include <config.h>
10 #include <asm/processor.h>
11 #include <asm/macro.h>
12
13 /*
14 * Board specific low level init code, called _very_ early in the
15 * startup sequence. Relocation to SDRAM has not happened yet, no
16 * stack is available, bss section has not been initialised, etc.
17 *
18 * (Note: As no stack is available, no subroutines can be called...).
19 */
20
21 .global lowlevel_init
22
23 .text
24 .align 2
25
26 lowlevel_init:
27 write16 DRVCRA_A, DRVCRA_D
28
29 write16 DRVCRB_A, DRVCRB_D
30
31 write16 RWTCSR_A, RWTCSR_D1
32
33 write16 RWTCNT_A, RWTCNT_D
34
35 write16 RWTCSR_A, RWTCSR_D2
36
37 write32 FRQCR_A, FRQCR_D
38
39 write32 CMNCR_A, CMNCR_D
40
41 write32 CS0BCR_A, CS0BCR_D
42
43 write32 CS4BCR_A, CS4BCR_D
44
45 write32 CS5ABCR_A, CS5ABCR_D
46
47 write32 CS5BBCR_A, CS5BBCR_D
48
49 write32 CS6ABCR_A, CS6ABCR_D
50
51 write32 CS6BBCR_A, CS6BBCR_D
52
53 write32 CS0WCR_A, CS0WCR_D
54
55 write32 CS4WCR_A, CS4WCR_D
56
57 write32 CS5AWCR_A, CS5AWCR_D
58
59 write32 CS5BWCR_A, CS5BWCR_D
60
61 write32 CS6AWCR_A, CS6AWCR_D
62
63 write32 CS6BWCR_A, CS6BWCR_D
64
65 write32 SBSC_SDCR_A, SBSC_SDCR_D1
66
67 write32 SBSC_SDWCR_A, SBSC_SDWCR_D
68
69 write32 SBSC_SDPCR_A, SBSC_SDPCR_D
70
71 write32 SBSC_RTCSR_A, SBSC_RTCSR_D
72
73 write32 SBSC_RTCNT_A, SBSC_RTCNT_D
74
75 write32 SBSC_RTCOR_A, SBSC_RTCOR_D
76
77 write8 SBSC_SDMR3_A1, SBSC_SDMR3_D
78
79 write8 SBSC_SDMR3_A2, SBSC_SDMR3_D
80
81 mov.l SLEEP_CNT, r1
82 2: tst r1, r1
83 nop
84 bf/s 2b
85 dt r1
86
87 write8 SBSC_SDMR3_A3, SBSC_SDMR3_D
88
89 write32 SBSC_SDCR_A, SBSC_SDCR_D2
90
91 write32 CCR_A, CCR_D
92
93 ! BL bit off (init = ON) (?!?)
94
95 stc sr, r0 ! BL bit off(init=ON)
96 mov.l SR_MASK_D, r1
97 and r1, r0
98 ldc r0, sr
99
100 rts
101 mov #0, r0
102
103 .align 2
104
105 DRVCRA_A: .long DRVCRA
106 DRVCRB_A: .long DRVCRB
107 DRVCRA_D: .word 0x4555
108 DRVCRB_D: .word 0x0005
109
110 RWTCSR_A: .long RWTCSR
111 RWTCNT_A: .long RWTCNT
112 FRQCR_A: .long FRQCR
113 RWTCSR_D1: .word 0xa507
114 RWTCSR_D2: .word 0xa504
115 RWTCNT_D: .word 0x5a00
116 .align 2
117 FRQCR_D: .long 0x0b04474a
118
119 SBSC_SDCR_A: .long SBSC_SDCR
120 SBSC_SDWCR_A: .long SBSC_SDWCR
121 SBSC_SDPCR_A: .long SBSC_SDPCR
122 SBSC_RTCSR_A: .long SBSC_RTCSR
123 SBSC_RTCNT_A: .long SBSC_RTCNT
124 SBSC_RTCOR_A: .long SBSC_RTCOR
125 SBSC_SDMR3_A1: .long 0xfe510000
126 SBSC_SDMR3_A2: .long 0xfe500242
127 SBSC_SDMR3_A3: .long 0xfe5c0042
128
129 SBSC_SDCR_D1: .long 0x92810112
130 SBSC_SDCR_D2: .long 0x92810912
131 SBSC_SDWCR_D: .long 0x05162482
132 SBSC_SDPCR_D: .long 0x00300087
133 SBSC_RTCSR_D: .long 0xa55a0212
134 SBSC_RTCNT_D: .long 0xa55a0000
135 SBSC_RTCOR_D: .long 0xa55a0040
136 SBSC_SDMR3_D: .long 0x00
137
138 CMNCR_A: .long CMNCR
139 CS0BCR_A: .long CS0BCR
140 CS4BCR_A: .long CS4BCR
141 CS5ABCR_A: .long CS5ABCR
142 CS5BBCR_A: .long CS5BBCR
143 CS6ABCR_A: .long CS6ABCR
144 CS6BBCR_A: .long CS6BBCR
145 CS0WCR_A: .long CS0WCR
146 CS4WCR_A: .long CS4WCR
147 CS5AWCR_A: .long CS5AWCR
148 CS5BWCR_A: .long CS5BWCR
149 CS6AWCR_A: .long CS6AWCR
150 CS6BWCR_A: .long CS6BWCR
151
152 CMNCR_D: .long 0x00000013
153 CS0BCR_D: .long 0x24920400
154 CS4BCR_D: .long 0x24920400
155 CS5ABCR_D: .long 0x24920400
156 CS5BBCR_D: .long 0x7fff0600
157 CS6ABCR_D: .long 0x24920400
158 CS6BBCR_D: .long 0x24920600
159 CS0WCR_D: .long 0x00000480
160 CS4WCR_D: .long 0x00000480
161 CS5AWCR_D: .long 0x00000380
162 CS5BWCR_D: .long 0x00000080
163 CS6AWCR_D: .long 0x00000300
164 CS6BWCR_D: .long 0x00000540
165
166 CCR_A: .long 0xff00001c
167 CCR_D: .long 0x0000090d
168
169 SLEEP_CNT: .long 0x00000800
170 SR_MASK_D: .long 0xEFFFFF0F