board/softing/vining_2000/vining_2000.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 samtec automotive software & electronics gmbh
   4  * Copyright (C) 2017-2019 softing automotive electronics gmbH
   5  *
   6  * Author: Christoph Fritz <chf.fritz@googlemail.com>
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/crm_regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/gpio.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/io.h>
  18 #include <asm/mach-imx/mxc_i2c.h>
  19 #include <linux/sizes.h>
  20 #include <common.h>
  21 #include <environment.h>
  22 #include <fsl_esdhc.h>
  23 #include <mmc.h>
  24 #include <i2c.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <power/pmic.h>
  28 #include <power/pfuze100_pmic.h>
  29 #include <usb.h>
  30 #include <usb/ehci-ci.h>
  31 #include <pwm.h>
  32 #include <wait_bit.h>
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  37         PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |   \
  38         PAD_CTL_SRE_FAST)
  39
  40 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |     \
  41         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |                \
  42         PAD_CTL_SRE_FAST)
  43
  44 #define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
  45
  46 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |                        \
  47         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |            \
  48         PAD_CTL_SRE_FAST)
  49
  50 #define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |      \
  51         PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |         \
  52         PAD_CTL_DSE_40ohm)
  53
  54 #define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |  \
  55         PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
  56
  57 #define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |     \
  58         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |  \
  59         PAD_CTL_SRE_FAST)
  60
  61 #define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |    \
  62         PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
  63
  64 #define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |     \
  65         PAD_CTL_PKE)
  66
  67 int dram_init(void)
  68 {
  69         gd->ram_size = imx_ddr_size();
  70
  71         return 0;
  72 }
  73
  74 static iomux_v3_cfg_t const uart1_pads[] = {
  75         MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  76         MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  77 };
  78
  79 static iomux_v3_cfg_t const usdhc2_pads[] = {
  80         MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
  81         MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82         MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83         MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  87 };
  88
  89 static iomux_v3_cfg_t const usdhc4_pads[] = {
  90         MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
  91         MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94         MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95         MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96         MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(USDHC_RESET_CTRL),
 101 };
 102
 103 static iomux_v3_cfg_t const fec1_pads[] = {
 104         MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
 105         MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
 106         MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 107         MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 108         MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 109         MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
 110         MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
 111         MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
 113                 MUX_MODE_SION,
 114         /* LAN8720 PHY Reset */
 115         MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
 116 };
 117
 118 static iomux_v3_cfg_t const pwm_led_pads[] = {
 119         MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
 120         MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
 121         MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
 122 };
 123
 124 static void setup_iomux_uart(void)
 125 {
 126         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 127 }
 128
 129 #define PHY_RESET IMX_GPIO_NR(5, 9)
 130
 131 int board_eth_init(bd_t *bis)
 132 {
 133         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 134         int ret;
 135         unsigned char eth1addr[6];
 136
 137         /* just to get secound mac address */
 138         imx_get_mac_from_fuse(1, eth1addr);
 139         if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
 140                 eth_env_set_enetaddr("eth1addr", eth1addr);
 141
 142         imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
 143
 144         /*
 145          * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
 146          * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
 147          * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
 148          */
 149         clrsetbits_le32(&iomuxc_regs->gpr[1],
 150                         IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
 151                         IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
 152                         IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
 153                         IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 154
 155         ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 156         if (ret)
 157                 goto eth_fail;
 158
 159         /* reset phy */
 160         gpio_direction_output(PHY_RESET, 0);
 161         mdelay(16);
 162         gpio_set_value(PHY_RESET, 1);
 163         mdelay(1);
 164
 165         ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
 166                                         IMX_FEC_BASE);
 167         if (ret)
 168                 goto eth_fail;
 169
 170         return ret;
 171
 172 eth_fail:
 173         printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
 174         gpio_set_value(PHY_RESET, 0);
 175         return ret;
 176 }
 177
 178 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 179 /* I2C1 for PMIC */
 180 static struct i2c_pads_info i2c_pad_info1 = {
 181         .scl = {
 182                 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
 183                 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
 184                 .gp = IMX_GPIO_NR(1, 0),
 185         },
 186         .sda = {
 187                 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
 188                 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
 189                 .gp = IMX_GPIO_NR(1, 1),
 190         },
 191 };
 192
 193 static struct pmic *pfuze_init(unsigned char i2cbus)
 194 {
 195         struct pmic *p;
 196         int ret;
 197         u32 reg;
 198
 199         ret = power_pfuze100_init(i2cbus);
 200         if (ret)
 201                 return NULL;
 202
 203         p = pmic_get("PFUZE100");
 204         ret = pmic_probe(p);
 205         if (ret)
 206                 return NULL;
 207
 208         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 209         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 210
 211         /* Set SW1AB stanby volage to 0.975V */
 212         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 213         reg &= ~SW1x_STBY_MASK;
 214         reg |= SW1x_0_975V;
 215         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 216
 217         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 218         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 219         reg &= ~SW1xCONF_DVSSPEED_MASK;
 220         reg |= SW1xCONF_DVSSPEED_4US;
 221         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 222
 223         /* Set SW1C standby voltage to 0.975V */
 224         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 225         reg &= ~SW1x_STBY_MASK;
 226         reg |= SW1x_0_975V;
 227         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 228
 229         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 230         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 231         reg &= ~SW1xCONF_DVSSPEED_MASK;
 232         reg |= SW1xCONF_DVSSPEED_4US;
 233         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 234
 235         return p;
 236 }
 237
 238 static int pfuze_mode_init(struct pmic *p, u32 mode)
 239 {
 240         unsigned char offset, i, switch_num;
 241         u32 id;
 242         int ret;
 243
 244         pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 245         id = id & 0xf;
 246
 247         if (id == 0) {
 248                 switch_num = 6;
 249                 offset = PFUZE100_SW1CMODE;
 250         } else if (id == 1) {
 251                 switch_num = 4;
 252                 offset = PFUZE100_SW2MODE;
 253         } else {
 254                 printf("Not supported, id=%d\n", id);
 255                 return -EINVAL;
 256         }
 257
 258         ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
 259         if (ret < 0) {
 260                 printf("Set SW1AB mode error!\n");
 261                 return ret;
 262         }
 263
 264         for (i = 0; i < switch_num - 1; i++) {
 265                 ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
 266                 if (ret < 0) {
 267                         printf("Set switch 0x%x mode error!\n",
 268                                offset + i * SWITCH_SIZE);
 269                         return ret;
 270                 }
 271         }
 272
 273         return ret;
 274 }
 275
 276 int power_init_board(void)
 277 {
 278         struct pmic *p;
 279         int ret;
 280
 281         p = pfuze_init(I2C_PMIC);
 282         if (!p)
 283                 return -ENODEV;
 284
 285         ret = pfuze_mode_init(p, APS_PFM);
 286         if (ret < 0)
 287                 return ret;
 288
 289         return 0;
 290 }
 291
 292 #ifdef CONFIG_USB_EHCI_MX6
 293 static iomux_v3_cfg_t const usb_otg_pads[] = {
 294         /* OGT1 */
 295         MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
 296         MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
 297         /* OTG2 */
 298         MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 299 };
 300
 301 static void setup_iomux_usb(void)
 302 {
 303         imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 304                                          ARRAY_SIZE(usb_otg_pads));
 305 }
 306
 307 int board_usb_phy_mode(int port)
 308 {
 309         if (port == 1)
 310                 return USB_INIT_HOST;
 311         else
 312                 return usb_phy_mode(port);
 313 }
 314 #endif
 315
 316 #ifdef CONFIG_PWM_IMX
 317 static int set_pwm_leds(void)
 318 {
 319         int ret;
 320
 321         imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
 322                                          ARRAY_SIZE(pwm_led_pads));
 323         /* enable backlight PWM 2, green LED */
 324         ret = pwm_init(1, 0, 0);
 325         if (ret)
 326                 goto error;
 327         /* duty cycle 200ns, period: 8000ns */
 328         ret = pwm_config(1, 200, 8000);
 329         if (ret)
 330                 goto error;
 331         ret = pwm_enable(1);
 332         if (ret)
 333                 goto error;
 334
 335         /* enable backlight PWM 1, blue LED */
 336         ret = pwm_init(0, 0, 0);
 337         if (ret)
 338                 goto error;
 339         /* duty cycle 200ns, period: 8000ns */
 340         ret = pwm_config(0, 200, 8000);
 341         if (ret)
 342                 goto error;
 343         ret = pwm_enable(0);
 344         if (ret)
 345                 goto error;
 346
 347         /* enable backlight PWM 6, red LED */
 348         ret = pwm_init(5, 0, 0);
 349         if (ret)
 350                 goto error;
 351         /* duty cycle 200ns, period: 8000ns */
 352         ret = pwm_config(5, 200, 8000);
 353         if (ret)
 354                 goto error;
 355         ret = pwm_enable(5);
 356
 357 error:
 358         return ret;
 359 }
 360 #else
 361 static int set_pwm_leds(void)
 362 {
 363         return 0;
 364 }
 365 #endif
 366
 367 #define ADCx_HC0        0x00
 368 #define ADCx_HS         0x08
 369 #define ADCx_HS_C0      BIT(0)
 370 #define ADCx_R0         0x0c
 371 #define ADCx_CFG        0x14
 372 #define ADCx_CFG_SWMODE 0x308
 373 #define ADCx_GC         0x18
 374 #define ADCx_GC_CAL     BIT(7)
 375
 376 static int read_adc(u32 *val)
 377 {
 378         int ret;
 379         void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
 380
 381         /* use software mode */
 382         writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
 383
 384         /* start auto calibration */
 385         setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
 386         ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
 387         if (ret)
 388                 goto adc_exit;
 389
 390         /* start conversion */
 391         writel(0, b + ADCx_HC0);
 392
 393         /* wait for conversion */
 394         ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
 395         if (ret)
 396                 goto adc_exit;
 397
 398         /* read result */
 399         *val = readl(b + ADCx_R0);
 400
 401 adc_exit:
 402         if (ret)
 403                 printf("ADC failure (ret=%i)\n", ret);
 404         unmap_physmem(b, MAP_NOCACHE);
 405         return ret;
 406 }
 407
 408 #define VAL_UPPER       2498
 409 #define VAL_LOWER       1550
 410
 411 static int set_pin_state(void)
 412 {
 413         u32 val;
 414         int ret;
 415
 416         ret = read_adc(&val);
 417         if (ret)
 418                 return ret;
 419
 420         if (val >= VAL_UPPER)
 421                 env_set("pin_state", "connected");
 422         else if (val < VAL_UPPER && val > VAL_LOWER)
 423                 env_set("pin_state", "open");
 424         else
 425                 env_set("pin_state", "button");
 426
 427         return ret;
 428 }
 429
 430 int board_late_init(void)
 431 {
 432         int ret;
 433
 434         ret = set_pwm_leds();
 435         if (ret)
 436                 return ret;
 437
 438         ret = set_pin_state();
 439
 440         return ret;
 441 }
 442
 443 int board_early_init_f(void)
 444 {
 445         setup_iomux_uart();
 446
 447         setup_iomux_usb();
 448
 449         return 0;
 450 }
 451
 452 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 453         {USDHC4_BASE_ADDR, 0, 8},
 454         {USDHC2_BASE_ADDR, 0, 4},
 455 };
 456
 457 #define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
 458
 459 int board_mmc_getcd(struct mmc *mmc)
 460 {
 461         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 462
 463         if (cfg->esdhc_base == USDHC4_BASE_ADDR)
 464                 return 1;
 465         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
 466                 return !gpio_get_value(USDHC2_CD_GPIO);
 467
 468         return -EINVAL;
 469 }
 470
 471 int board_mmc_init(bd_t *bis)
 472 {
 473         int ret;
 474
 475         /*
 476          * According to the board_mmc_init() the following map is done:
 477          * (U-Boot device node)    (Physical Port)
 478          * mmc0                    USDHC4
 479          * mmc1                    USDHC2
 480          */
 481         imx_iomux_v3_setup_multiple_pads(
 482                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 483         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 484
 485         imx_iomux_v3_setup_multiple_pads(
 486                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 487         gpio_direction_input(USDHC2_CD_GPIO);
 488         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 489
 490         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 491         if (ret) {
 492                 printf("Warning: failed to initialize USDHC4\n");
 493                 return ret;
 494         }
 495
 496         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
 497         if (ret) {
 498                 printf("Warning: failed to initialize USDHC2\n");
 499                 return ret;
 500         }
 501
 502         return 0;
 503 }
 504
 505 int board_init(void)
 506 {
 507         /* Address of boot parameters */
 508         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 509
 510 #ifdef CONFIG_SYS_I2C_MXC
 511         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 512 #endif
 513
 514         return 0;
 515 }
 516
 517 int checkboard(void)
 518 {
 519         puts("Board: VIN|ING 2000\n");
 520
 521         return 0;
 522 }