1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/arch/psu_init_gpl.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
21 #include <dwc3-uboot.h>
25 DECLARE_GLOBAL_DATA_PTR
;
27 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
28 !defined(CONFIG_SPL_BUILD)
29 static xilinx_desc zynqmppl
= XILINX_ZYNQMP_DESC
;
36 } zynqmp_devices
[] = {
128 { /* For testing purpose only */
176 int chip_id(unsigned char id
)
181 if (current_el() != 3) {
182 regs
.regs
[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID
;
191 * regs[0][31:0] = status of the operation
192 * regs[0][63:32] = CSU.IDCODE register
193 * regs[1][31:0] = CSU.version register
194 * regs[1][63:32] = CSU.IDCODE2 register
198 regs
.regs
[0] = upper_32_bits(regs
.regs
[0]);
199 regs
.regs
[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
200 ZYNQMP_CSU_IDCODE_SVD_MASK
;
201 regs
.regs
[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
205 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
206 regs
.regs
[1] &= ZYNQMP_CSU_SILICON_VER_MASK
;
210 regs
.regs
[1] = lower_32_bits(regs
.regs
[1]);
211 regs
.regs
[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT
;
215 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
220 val
= readl(ZYNQMP_CSU_IDCODE_ADDR
);
221 val
&= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK
|
222 ZYNQMP_CSU_IDCODE_SVD_MASK
;
223 val
>>= ZYNQMP_CSU_IDCODE_SVD_SHIFT
;
226 val
= readl(ZYNQMP_CSU_VER_ADDR
);
227 val
&= ZYNQMP_CSU_SILICON_VER_MASK
;
230 printf("%s, Invalid Req:0x%x\n", __func__
, id
);
237 #define ZYNQMP_VERSION_SIZE 9
238 #define ZYNQMP_PL_STATUS_BIT 9
239 #define ZYNQMP_IPDIS_VCU_BIT 8
240 #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
241 #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
242 #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
243 ~BIT(ZYNQMP_IPDIS_VCU_BIT)
244 #define MAX_VARIANTS_EV 3
246 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
247 !defined(CONFIG_SPL_BUILD)
248 static char *zynqmp_get_silicon_idcode_name(void)
252 static char name
[ZYNQMP_VERSION_SIZE
];
254 id
= chip_id(IDCODE
);
255 ver
= chip_id(IDCODE2
);
257 for (i
= 0; i
< ARRAY_SIZE(zynqmp_devices
); i
++) {
258 if (zynqmp_devices
[i
].id
== id
) {
259 if (zynqmp_devices
[i
].evexists
&&
260 !(ver
& ZYNQMP_PL_STATUS_MASK
))
262 if (zynqmp_devices
[i
].ver
== (ver
&
263 ZYNQMP_CSU_VERSION_MASK
))
268 if (i
>= ARRAY_SIZE(zynqmp_devices
))
271 strncat(name
, "zu", 2);
272 if (!zynqmp_devices
[i
].evexists
||
273 (ver
& ZYNQMP_PL_STATUS_MASK
)) {
274 strncat(name
, zynqmp_devices
[i
].name
,
275 ZYNQMP_VERSION_SIZE
- 3);
280 * Here we are means, PL not powered up and ev variant
281 * exists. So, we need to ignore VCU disable bit(8) in
282 * version and findout if its CG or EG/EV variant.
284 for (j
= 0; j
< MAX_VARIANTS_EV
; j
++, i
++) {
285 if ((zynqmp_devices
[i
].ver
& ~BIT(ZYNQMP_IPDIS_VCU_BIT
)) ==
286 (ver
& ZYNQMP_CSU_VCUDIS_VER_MASK
)) {
287 strncat(name
, zynqmp_devices
[i
].name
,
288 ZYNQMP_VERSION_SIZE
- 3);
293 if (j
>= MAX_VARIANTS_EV
)
296 if (strstr(name
, "eg") || strstr(name
, "ev")) {
297 buf
= strstr(name
, "e");
305 int board_early_init_f(void)
308 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_CLK_ZYNQMP)
311 pm_api_version
= zynqmp_pmufw_version();
312 printf("PMUFW:\tv%d.%d\n",
313 pm_api_version
>> ZYNQMP_PM_VERSION_MAJOR_SHIFT
,
314 pm_api_version
& ZYNQMP_PM_VERSION_MINOR_MASK
);
316 if (pm_api_version
< ZYNQMP_PM_VERSION
)
317 panic("PMUFW version error. Expected: v%d.%d\n",
318 ZYNQMP_PM_VERSION_MAJOR
, ZYNQMP_PM_VERSION_MINOR
);
321 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
330 printf("EL Level:\tEL%d\n", current_el());
332 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
333 !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
334 defined(CONFIG_SPL_BUILD))
335 if (current_el() != 3) {
336 zynqmppl
.name
= zynqmp_get_silicon_idcode_name();
337 printf("Chip ID:\t%s\n", zynqmppl
.name
);
339 fpga_add(fpga_xilinx
, &zynqmppl
);
346 int board_early_init_r(void)
350 if (current_el() != 3)
353 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
354 val
&= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
357 val
= readl(&crlapb_base
->timestamp_ref_ctrl
);
358 val
|= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT
;
359 writel(val
, &crlapb_base
->timestamp_ref_ctrl
);
361 /* Program freq register in System counter */
362 writel(zynqmp_get_system_timer_freq(),
363 &iou_scntr_secure
->base_frequency_id_register
);
364 /* And enable system counter */
365 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN
,
366 &iou_scntr_secure
->counter_control_register
);
371 unsigned long do_go_exec(ulong (*entry
)(int, char * const []), int argc
,
376 if (current_el() > 1) {
379 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry
,
382 printf("FAIL: current EL is not above EL1\n");
388 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
389 int dram_init_banksize(void)
393 ret
= fdtdec_setup_memory_banksize();
404 if (fdtdec_setup_mem_size_base() != 0)
410 int dram_init_banksize(void)
412 #if defined(CONFIG_NR_DRAM_BANKS)
413 gd
->bd
->bi_dram
[0].start
= CONFIG_SYS_SDRAM_BASE
;
414 gd
->bd
->bi_dram
[0].size
= get_effective_memsize();
424 gd
->ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
,
425 CONFIG_SYS_SDRAM_SIZE
);
431 void reset_cpu(ulong addr
)
435 #if defined(CONFIG_BOARD_LATE_INIT)
436 static const struct {
439 } reset_reasons
[] = {
440 { RESET_REASON_DEBUG_SYS
, "DEBUG" },
441 { RESET_REASON_SOFT
, "SOFT" },
442 { RESET_REASON_SRST
, "SRST" },
443 { RESET_REASON_PSONLY
, "PS-ONLY" },
444 { RESET_REASON_PMU
, "PMU" },
445 { RESET_REASON_INTERNAL
, "INTERNAL" },
446 { RESET_REASON_EXTERNAL
, "EXTERNAL" },
450 static int reset_reason(void)
454 const char *reason
= NULL
;
456 ret
= zynqmp_mmio_read((ulong
)&crlapb_base
->reset_reason
, ®
);
460 puts("Reset reason:\t");
462 for (i
= 0; i
< ARRAY_SIZE(reset_reasons
); i
++) {
463 if (reg
& reset_reasons
[i
].bit
) {
464 reason
= reset_reasons
[i
].name
;
465 printf("%s ", reset_reasons
[i
].name
);
472 env_set("reset_reason", reason
);
474 ret
= zynqmp_mmio_write(~0, ~0, (ulong
)&crlapb_base
->reset_reason
);
481 static int set_fdtfile(void)
483 char *compatible
, *fdtfile
;
484 const char *suffix
= ".dtb";
485 const char *vendor
= "xilinx/";
487 if (env_get("fdtfile"))
490 compatible
= (char *)fdt_getprop(gd
->fdt_blob
, 0, "compatible", NULL
);
492 debug("Compatible: %s\n", compatible
);
494 /* Discard vendor prefix */
495 strsep(&compatible
, ",");
497 fdtfile
= calloc(1, strlen(vendor
) + strlen(compatible
) +
502 sprintf(fdtfile
, "%s%s%s", vendor
, compatible
, suffix
);
504 env_set("fdtfile", fdtfile
);
511 int board_late_init(void)
518 int env_targets_len
= 0;
524 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
528 if (!(gd
->flags
& GD_FLG_ENV_DEFAULT
)) {
529 debug("Saved variables - Skipping\n");
537 ret
= zynqmp_mmio_read((ulong
)&crlapb_base
->boot_mode
, ®
);
541 if (reg
>> BOOT_MODE_ALT_SHIFT
)
542 reg
>>= BOOT_MODE_ALT_SHIFT
;
544 bootmode
= reg
& BOOT_MODES_MASK
;
551 env_set("modeboot", "usb_dfu_spl");
556 env_set("modeboot", "jtagboot");
558 case QSPI_MODE_24BIT
:
559 case QSPI_MODE_32BIT
:
562 env_set("modeboot", "qspiboot");
567 env_set("modeboot", "emmcboot");
571 if (uclass_get_device_by_name(UCLASS_MMC
,
572 "mmc@ff160000", &dev
) &&
573 uclass_get_device_by_name(UCLASS_MMC
,
574 "sdhci@ff160000", &dev
)) {
575 puts("Boot from SD0 but without SD0 enabled!\n");
578 debug("mmc0 device found at %p, seq %d\n", dev
, dev
->seq
);
582 env_set("modeboot", "sdboot");
589 if (uclass_get_device_by_name(UCLASS_MMC
,
590 "mmc@ff170000", &dev
) &&
591 uclass_get_device_by_name(UCLASS_MMC
,
592 "sdhci@ff170000", &dev
)) {
593 puts("Boot from SD1 but without SD1 enabled!\n");
596 debug("mmc1 device found at %p, seq %d\n", dev
, dev
->seq
);
600 env_set("modeboot", "sdboot");
605 env_set("modeboot", "nandboot");
609 printf("Invalid Boot Mode:0x%x\n", bootmode
);
614 bootseq_len
= snprintf(NULL
, 0, "%i", bootseq
);
615 debug("Bootseq len: %x\n", bootseq_len
);
619 * One terminating char + one byte for space between mode
620 * and default boot_targets
622 env_targets
= env_get("boot_targets");
624 env_targets_len
= strlen(env_targets
);
626 new_targets
= calloc(1, strlen(mode
) + env_targets_len
+ 2 +
632 sprintf(new_targets
, "%s%x %s", mode
, bootseq
,
633 env_targets
? env_targets
: "");
635 sprintf(new_targets
, "%s %s", mode
,
636 env_targets
? env_targets
: "");
638 env_set("boot_targets", new_targets
);
648 puts("Board: Xilinx ZynqMP\n");