doc/README.bus_vcxk

   1 SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2008-2009
   4  * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
   5  * Jens Scharsig <esw@bus-elektronik.de>
   6  */
   7
   8 U-Boot vcxk video controller driver
   9 ======================================
  10
  11 By defining CONFIG_VIDEO_VCXK this driver can be used with VC2K, VC4K and
  12 VC8K devices on following boards:
  13
  14 board           | ARCH          | Vendor
  15 -----------------------------------------------------------------------
  16 EB+CPU5282-T1   | MCF5282       | BuS Elektronik GmbH & Co. KG
  17 EB+MCF-EVB123   | MCF5282       | BuS Elektronik GmbH & Co. KG
  18 EB+CPUx9K2      | AT91RM9200    | BuS Elektronik GmbH & Co. KG
  19 ZLSA            | AT91RM9200    | Ruf Telematik AG
  20
  21 Driver configuration
  22 --------------------
  23
  24 The driver needs some defines to describe the target hardware:
  25
  26 CONFIG_SYS_VCXK_BASE
  27
  28         base address of VCxK hardware memory
  29
  30 CONFIG_SYS_VCXK_DEFAULT_LINEALIGN
  31
  32         defines the physical alignment of a pixel row
  33
  34 CONFIG_SYS_VCXK_DOUBLEBUFFERED
  35
  36         some boards that use vcxk prevent read from framebuffer memory.
  37         define this option to enable double buffering (needs 16KiB RAM)
  38
  39 CONFIG_SYS_VCXK_<xxxx>_PIN
  40
  41         defines the number of the I/O line PIN in the port
  42         valid values for <xxxx> are:
  43
  44                 ACKNOWLEDGE
  45                         describes the acknowledge line from vcxk hardware
  46
  47                 ENABLE
  48                         describes the enable line to vcxk hardware
  49
  50                 INVERT
  51                         describes the invert line to vcxk hardware
  52
  53                 RESET
  54                         describes the reset line to vcxk hardware
  55
  56                 REQUEST
  57                         describes the request line to vcxk hardware
  58
  59 CONFIG_SYS_VCXK_<xxxx>_PORT
  60
  61         defines the I/O port which is connected with the line
  62         for valid values for <xxxx> see CONFIG_SYS_VCXK_<xxxx>_PIN
  63
  64 CONFIG_SYS_VCXK_<xxxx>_DDR
  65
  66         defines the register which configures the direction
  67         for valid values for <xxxx> see CONFIG_SYS_VCXK_<xxxx>_PIN