1 STMicroelectronics STM32MP1 clock tree initialization
2 =====================================================
4 The STM32MP1 clock tree initialization is based on device tree information
5 for RCC IP node (st,stm32mp1-rcc) and on fixed-clock nodes.
7 RCC IP = st,stm32mp1-rcc
8 ========================
10 The RCC IP is both a reset and a clock controller but this documentation only
11 describes the fields added for clock tree initialization which are not present
12 in Linux binding for compatible "st,stm32mp1-rcc" defined in st,stm32mp1-rcc.txt
15 The added properties for clock tree initialization are:
18 - st,clksrc : The clock sources configuration array in a platform specific
21 For the STM32MP15x family there are 9 clock sources selector which are
22 configured in the following order:
23 MPU AXI MCU PLL12 PLL3 PLL4 RTC MCO1 MCO2
25 Clock source configuration values are defined by macros CLK_<NAME>_<SOURCE>
26 from dt-bindings/clock/stm32mp1-clksrc.h.
41 - st,clkdiv : The clock main dividers value specified in an array
42 in a platform specific order.
44 When used, it shall describe the whole clock dividers tree.
46 For the STM32MP15x family there are 11 dividers values expected.
47 They shall be configured in the following order:
48 MPU AXI MCU APB1 APB2 APB3 APB4 APB5 RTC MCO1 MCO2
50 The each divider value uses the DIV coding defined in RCC associated
51 register RCC_xxxDIVR. In most the case, it is:
58 Note that for RTC MCO1 MCO2, the coding is different:
81 - st,pll : A specific PLL configuration, including frequency.
83 PLL children nodes for PLL1 to PLL4 (see ref manual for details)
84 are listed with associated index 0 to 3 (st,pll@0 to st,pll@3).
85 PLLx is off when the associated node is absent.
87 Here are the available properties for each PLL node:
89 - cfg: The parameters for PLL configuration in the following order:
90 DIVM DIVN DIVP DIVQ DIVR Output.
92 DIVx values are defined as in RCC spec:
93 0x0: bypass (division by 1)
99 Output contains a bitfield for each output value (1:ON/0:OFF)
100 BIT(0) => output P : DIVPEN
101 BIT(1) => output Q : DIVQEN
102 BIT(2) => output R : DIVREN
103 NB: macro PQR(p,q,r) can be used to build this value
106 - frac : Fractional part of the multiplication factor
107 (optional, PLL is in integer mode when absent).
109 - csg : Clock Spreading Generator (optional) with parameters in the
110 following order: MOD_PER INC_STEP SSCG_MODE.
112 MOD_PER: Modulation Period Adjustment
113 INC_STEP: Modulation Depth Adjustment
114 SSCG_MODE: Spread spectrum clock generator mode, with associated
115 defined from stm32mp1-clksrc.h:
116 - SSCG_MODE_CENTER_SPREAD = 0
117 - SSCG_MODE_DOWN_SPREAD = 1
121 cfg = < 1 53 0 0 0 1 >;
125 cfg = < 1 43 1 0 0 PQR(0,1,1) >;
129 cfg = < 2 85 3 13 3 0 >;
130 csg = < 10 20 SSCG_MODE_CENTER_SPREAD >;
133 cfg = < 2 78 4 7 9 3 >;
136 - st,pkcs : used to configure the peripherals kernel clock selection.
138 The property is a list of peripheral kernel clock source identifiers defined
139 by macros CLK_<KERNEL-CLOCK>_<PARENT-CLOCK> as defined by header file
140 dt-bindings/clock/stm32mp1-clksrc.h.
142 st,pkcs may not list all the kernel clocks and has no ordering requirements.
155 other clocks = fixed-clock
156 ==========================
158 The clock tree is also based on 5 fixed-clock in clocks node
159 used to define the state of associated ST32MP1 oscillators:
166 At boot the clock tree initialization will
167 - enable oscillators present in device tree
168 - disable HSI oscillator if the node is absent (always activated by bootrom)
170 Optional properties :
172 a) for external oscillator: "clk-lse", "clk-hse"
174 4 optional fields are managed
175 - "st,bypass" configures the oscillator bypass mode (HSEBYP, LSEBYP)
176 - "st,digbypass" configures the bypass mode as full-swing digital
178 - "st,css" activates the clock security system (HSECSSON, LSECSSON)
179 - "st,drive" (only for LSE) contains the value of the drive for the
180 oscillator (see LSEDRV_ defined in the file
181 dt-bindings/clock/stm32mp1-clksrc.h)
188 compatible = "fixed-clock";
189 clock-frequency = <64000000>;
195 compatible = "fixed-clock";
196 clock-frequency = <32768>;
198 st,drive = <LSEDRV_LOWEST>;
202 b) for internal oscillator: "clk-hsi"
204 Internally HSI clock is fixed to 64MHz for STM32MP157 SoC.
205 In device tree, clk-hsi is the clock after HSIDIV (clk_hsi in RCC
206 doc). So this clock frequency is used to compute the expected HSI_DIV
207 for the clock tree initialization.
209 Example with HSIDIV = /1:
214 compatible = "fixed-clock";
215 clock-frequency = <64000000>;
219 Example with HSIDIV = /2
224 compatible = "fixed-clock";
225 clock-frequency = <32000000>;
229 Example of clock tree initialization
230 ====================================
238 compatible = "fixed-clock";
239 clock-frequency = <24000000>;
246 compatible = "fixed-clock";
247 clock-frequency = <64000000>;
253 compatible = "fixed-clock";
254 clock-frequency = <32768>;
260 compatible = "fixed-clock";
261 clock-frequency = <32000>;
267 compatible = "fixed-clock";
268 clock-frequency = <4000000>;
276 compatible = "st,stm32mp1-rcc", "syscon";
277 reg = <0x50000000 0x1000>;
280 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
346 /* VCO = 1300.0 MHz => P = 650 (CPU) */
348 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
353 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU),
356 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
361 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
363 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
368 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
370 cfg = < 3 98 5 7 7 PQR(1,1,1) >;