doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt

   1 Altera SOCFPGA Arria10 FPGA Manager
   2
   3 Required properties:
   4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
   5 - reg        : base address and size for memory mapped io.
   6                - The first index is for FPGA manager register access.
   7                - The second index is for writing FPGA configuration data.
   8 - resets     : Phandle and reset specifier for the device's reset.
   9 - clocks     : Clocks used by the device.
  10 - altr,bitstream : Fit image file name for both FPGA peripheral bitstream,
  11                    FPGA core bitstream and full bitstream.
  12
  13                    Full bitstream, consist of peripheral bitstream and core
  14                    bitstream.
  15
  16                    FPGA peripheral bitstream is used to initialize FPGA IOs,
  17                    PLL, IO48 and DDR. This bitstream is required to get DDR up
  18                    running.
  19
  20                    FPGA core bitstream contains FPGA design which is used to
  21                    program FPGA CRAM and ERAM.
  22
  23 Example: Bundles both peripheral bitstream and core bitstream into FIT image
  24          called fit_spl_fpga.itb. This FIT image can be created through running
  25          this command: tools/mkimage
  26                        -E -p 400
  27                        -f board/altera/arria10-socdk/fit_spl_fpga.its
  28                        fit_spl_fpga.itb
  29
  30          For details of describing structure and contents of the FIT image,
  31          please refer board/altera/arria10-socdk/fit_spl_fpga.its
  32
  33 - Examples for booting with full release or booting with early IO release, then
  34   follow by entering early user mode:
  35
  36         fpga_mgr: fpga-mgr@ffd03000 {
  37                 compatible = "altr,socfpga-a10-fpga-mgr";
  38                 reg = <0xffd03000 0x100
  39                        0xffcfe400 0x20>;
  40                 clocks = <&l4_mp_clk>;
  41                 resets = <&rst FPGAMGR_RESET>;
  42                 altr,bitstream = "fit_spl_fpga.itb";
  43         };