1 Change Log & Release Notes
2 ==========================
4 This document contains a summary of the new features, changes, fixes and known
5 issues in each release of Trusted Firmware-A.
14 - Support for ARMv8.3 pointer authentication in the normal and secure worlds
16 The use of pointer authentication in the normal world is enabled whenever
17 architectural support is available, without the need for additional build
20 Use of pointer authentication in the secure world remains an
21 experimental configuration at this time. Using both the ``ENABLE_PAUTH``
22 and ``CTX_INCLUDE_PAUTH_REGS`` build flags, pointer authentication can be
23 enabled in EL3 and S-EL1/0.
25 See the :ref:`Firmware Design` document for additional details on the use
26 of pointer authentication.
28 - Enable Data Independent Timing (DIT) in EL3, where supported
31 - Support for BL-specific build flags
33 - Support setting compiler target architecture based on ``ARM_ARCH_MINOR``
36 - New ``RECLAIM_INIT_CODE`` build flag:
38 A significant amount of the code used for the initialization of BL31 is
39 not needed again after boot time. In order to reduce the runtime memory
40 footprint, the memory used for this code can be reclaimed after
43 Certain boot-time functions were marked with the ``__init`` attribute to
44 enable this reclamation.
47 - cortex-a76: Workaround for erratum 1073348
48 - cortex-a76: Workaround for erratum 1220197
49 - cortex-a76: Workaround for erratum 1130799
51 - cortex-a75: Workaround for erratum 790748
52 - cortex-a75: Workaround for erratum 764081
54 - cortex-a73: Workaround for erratum 852427
55 - cortex-a73: Workaround for erratum 855423
57 - cortex-a57: Workaround for erratum 817169
58 - cortex-a57: Workaround for erratum 814670
60 - cortex-a55: Workaround for erratum 903758
61 - cortex-a55: Workaround for erratum 846532
62 - cortex-a55: Workaround for erratum 798797
63 - cortex-a55: Workaround for erratum 778703
64 - cortex-a55: Workaround for erratum 768277
66 - cortex-a53: Workaround for erratum 819472
67 - cortex-a53: Workaround for erratum 824069
68 - cortex-a53: Workaround for erratum 827319
70 - cortex-a17: Workaround for erratum 852423
71 - cortex-a17: Workaround for erratum 852421
73 - cortex-a15: Workaround for erratum 816470
74 - cortex-a15: Workaround for erratum 827671
77 - Exception Handling Framework documentation
79 - Library at ROM (romlib) documentation
81 - RAS framework documentation
83 - Coding Guidelines document
86 - ccn: Add API for setting and reading node registers
87 - Adds ``ccn_read_node_reg`` function
88 - Adds ``ccn_write_node_reg`` function
90 - partition: Support MBR partition entries
92 - scmi: Add ``plat_css_get_scmi_info`` function
94 Adds a new API ``plat_css_get_scmi_info`` which lets the platform
95 register a platform-specific instance of ``scmi_channel_plat_info_t`` and
96 remove the default values
98 - tzc380: Add TZC-380 TrustZone Controller driver
100 - tzc-dmc620: Add driver to manage the TrustZone Controller within the
101 DMC-620 Dynamic Memory Controller
103 - Library at ROM (romlib)
104 - Add platform-specific jump table list
106 - Allow patching of romlib functions
108 This change allows patching of functions in the romlib. This can be done by
109 adding "patch" at the end of the jump table entry for the function that
110 needs to be patched in the file jmptbl.i.
113 - Support non-LPAE-enabled MMU tables in AArch32
115 - mmio: Add ``mmio_clrsetbits_16`` function
116 - 16-bit variant of ``mmio_clrsetbits``
118 - object_pool: Add Object Pool Allocator
119 - Manages object allocation using a fixed-size static array
120 - Adds ``pool_alloc`` and ``pool_alloc_n`` functions
121 - Does not provide any functions to free allocated objects (by design)
123 - libc: Added ``strlcpy`` function
125 - libc: Import ``strrchr`` function from FreeBSD
127 - xlat_tables: Add support for ARMv8.4-TTST
129 - xlat_tables: Support mapping regions without an explicitly specified VA
132 - Added softudiv macro to support software division
134 - Memory Partitioning And Monitoring (MPAM)
135 - Enabled MPAM EL2 traps (``MPAMHCR_EL2`` and ``MPAM_EL2``)
138 - amlogic: Add support for Meson S905 (GXBB)
140 - arm/fvp_ve: Add support for FVP Versatile Express platform
142 - arm/n1sdp: Add support for Neoverse N1 System Development platform
144 - arm/rde1edge: Add support for Neoverse E1 platform
146 - arm/rdn1edge: Add support for Neoverse N1 platform
148 - arm: Add support for booting directly to Linux without an intermediate
151 - arm/juno: Enable new CPU errata workarounds for A53 and A57
153 - arm/juno: Add romlib support
155 Building a combined BL1 and ROMLIB binary file with the correct page
156 alignment is now supported on the Juno platform. When ``USE_ROMLIB`` is set
157 for Juno, it generates the combined file ``bl1_romlib.bin`` which needs to
158 be used instead of bl1.bin.
160 - intel/stratix: Add support for Intel Stratix 10 SoC FPGA platform
162 - marvell: Add support for Armada-37xx SoC platform
164 - nxp: Add support for i.MX8M and i.MX7 Warp7 platforms
166 - renesas: Add support for R-Car Gen3 platform
168 - xilinx: Add support for Versal ACAP platforms
170 - Position-Independent Executable (PIE)
172 PIE support has initially been added to BL31. The ``ENABLE_PIE`` build flag is
173 used to enable or disable this functionality as required.
175 - Secure Partition Manager
176 - New SPM implementation based on SPCI Alpha 1 draft specification
178 A new version of SPM has been implemented, based on the SPCI (Secure
179 Partition Client Interface) and SPRT (Secure Partition Runtime) draft
182 The new implementation is a prototype that is expected to undergo intensive
183 rework as the specifications change. It has basic support for multiple
184 Secure Partitions and Resource Descriptions.
186 The older version of SPM, based on MM (ARM Management Mode Interface
187 Specification), is still present in the codebase. A new build flag,
188 ``SPM_MM`` has been added to allow selection of the desired implementation.
189 This flag defaults to 1, selecting the MM-based implementation.
192 - Spectre Variant-1 mitigations (``CVE-2017-5753``)
194 - Use Speculation Store Bypass Safe (SSBS) functionality where available
196 Provides mitigation against ``CVE-2018-19440`` (Not saving x0 to x3
197 registers can leak information from one Normal World SMC client to another)
204 - Warning levels are now selectable with ``W=<1,2,3>``
206 - Removed unneeded include paths in PLAT_INCLUDES
208 - "Warnings as errors" (Werror) can be disabled using ``E=0``
210 - Support totally quiet output with ``-s`` flag
212 - Support passing options to checkpatch using ``CHECKPATCH_OPTS=<opts>``
214 - Invoke host compiler with ``HOSTCC / HOSTCCFLAGS`` instead of ``CC / CFLAGS``
216 - Make device tree pre-processing similar to U-boot/Linux by:
217 - Creating separate ``CPPFLAGS`` for DT preprocessing so that compiler
218 options specific to it can be accommodated.
219 - Replacing ``CPP`` with ``PP`` for DT pre-processing
222 - Errata report function definition is now mandatory for CPU support files
224 CPU operation files must now define a ``<name>_errata_report`` function to
225 print errata status. This is no longer a weak reference.
228 - Migrated some content from GitHub wiki to ``docs/`` directory
230 - Security advisories now have CVE links
232 - Updated copyright guidelines
235 - console: The ``MULTI_CONSOLE_API`` framework has been rewritten in C
237 - console: Ported multi-console driver to AArch32
239 - gic: Remove 'lowest priority' constants
241 Removed ``GIC_LOWEST_SEC_PRIORITY`` and ``GIC_LOWEST_NS_PRIORITY``.
242 Platforms should define these if required, or instead determine the correct
243 priority values at runtime.
245 - delay_timer: Check that the Generic Timer extension is present
247 - mmc: Increase command reply timeout to 10 milliseconds
249 - mmc: Poll eMMC device status to ensure ``EXT_CSD`` command completion
251 - mmc: Correctly check return code from ``mmc_fill_device_info``
255 - libfdt: Upgraded from 1.4.2 to 1.4.6-9
257 - mbed TLS: Upgraded from 2.12 to 2.16
259 This change incorporates fixes for security issues that should be reviewed
260 to determine if they are relevant for software implementations using
261 Trusted Firmware-A. See the `mbed TLS releases`_ page for details on
262 changes from the 2.12 to the 2.16 release.
265 - compiler-rt: Updated ``lshrdi3.c`` and ``int_lib.h`` with changes from
266 LLVM master branch (r345645)
268 - cpu: Updated macro that checks need for ``CVE-2017-5715`` mitigation
270 - libc: Made setjmp and longjmp C standard compliant
272 - libc: Allowed overriding the default libc (use ``OVERRIDE_LIBC``)
274 - libc: Moved setjmp and longjmp to the ``libc/`` directory
277 - Removed Mbed TLS dependency from plat_bl_common.c
279 - arm: Removed unused ``ARM_MAP_BL_ROMLIB`` macro
281 - arm: Removed ``ARM_BOARD_OPTIMISE_MEM`` feature and build flag
283 - arm: Moved several components into ``drivers/`` directory
285 This affects the SDS, SCP, SCPI, MHU and SCMI components
287 - arm/juno: Increased maximum BL2 image size to ``0xF000``
289 This change was required to accommodate a larger ``libfdt`` library
292 - Optimized bakery locks when hardware-assisted coherency is enabled using the
293 ``HW_ASSISTED_COHERENCY`` build flag
296 - Added support for unconditionally resuming secure world execution after
297 |SDEI| event processing completes
299 |SDEI| interrupts, although targeting EL3, occur on behalf of the non-secure
300 world, and may have higher priority than secure world
301 interrupts. Therefore they might preempt secure execution and yield
302 execution to the non-secure |SDEI| handler. Upon completion of |SDEI| event
303 handling, resume secure execution if it was preempted.
305 - Translation Tables (XLAT)
306 - Dynamically detect need for ``Common not Private (TTBRn_ELx.CnP)`` bit
308 Properly handle the case where ``ARMv8.2-TTCNP`` is implemented in a CPU
309 that does not implement all mandatory v8.2 features (and so must claim to
310 implement a lower architecture version).
317 - Incorrect check for SSBS feature detection
319 - Unintentional register clobber in AArch32 reset_handler function
322 - Dependency issue during DTB image build
324 - Incorrect variable expansion in Arm platform makefiles
326 - Building on Windows with verbose mode (``V=1``) enabled is broken
328 - AArch32 compilation flags is missing ``$(march32-directive)``
331 - bl2: ``uintptr_t is not defined`` error when ``BL2_IN_XIP_MEM`` is defined
333 - bl2: Missing prototype warning in ``bl2_arch_setup``
335 - bl31: Omission of Global Offset Table (GOT) section
337 - Code Quality Issues
338 - Multiple MISRA compliance issues
340 - Potential NULL pointer dereference (Coverity-detected)
343 - mmc: Local declaration of ``scr`` variable causes a cache issue when
344 invalidating after the read DMA transfer completes
346 - mmc: ``ACMD41`` does not send voltage information during initialization,
347 resulting in the command being treated as a query. This prevents the
348 command from initializing the controller.
350 - mmc: When checking device state using ``mmc_device_state()`` there are no
351 retries attempted in the event of an error
353 - ccn: Incorrect Region ID calculation for RN-I nodes
355 - console: ``Fix MULTI_CONSOLE_API`` when used as a crash console
357 - partition: Improper NULL checking in gpt.c
359 - partition: Compilation failure in ``VERBOSE`` mode (``V=1``)
362 - common: Incorrect check for Address Authentication support
364 - xlat: Fix XLAT_V1 / XLAT_V2 incompatibility
366 The file ``arm_xlat_tables.h`` has been renamed to ``xlat_tables_compat.h``
367 and has been moved to a common folder. This header can be used to guarantee
368 compatibility, as it includes the correct header based on
369 ``XLAT_TABLES_LIB_V2``.
371 - xlat: armclang unused-function warning on ``xlat_clean_dcache_range``
373 - xlat: Invalid ``mm_cursor`` checks in ``mmap_add`` and ``mmap_add_ctx``
375 - sdei: Missing ``context.h`` header
378 - common: Missing prototype warning for ``plat_log_get_prefix``
380 - arm: Insufficient maximum BL33 image size
382 - arm: Potential memory corruption during BL2-BL31 transition
384 On Arm platforms, the BL2 memory can be overlaid by BL31/BL32. The memory
385 descriptors describing the list of executable images are created in BL2
386 R/W memory, which could be possibly corrupted later on by BL31/BL32 due
387 to overlay. This patch creates a reserved location in SRAM for these
388 descriptors and are copied over by BL2 before handing over to next BL
391 - juno: Invalid behaviour when ``CSS_USE_SCMI_SDS_DRIVER`` is not set
393 In ``juno_pm.c`` the ``css_scmi_override_pm_ops`` function was used
394 regardless of whether the build flag was set. The original behaviour has
395 been restored in the case where the build flag is not set.
398 - fiptool: Incorrect UUID parsing of blob parameters
400 - doimage: Incorrect object rules in Makefile
407 - ``plat_crash_console_init`` function
409 - ``plat_crash_console_putc`` function
411 - ``plat_crash_console_flush`` function
413 - ``finish_console_register`` macro
415 - AArch64-specific Code
416 - helpers: ``get_afflvl_shift``
418 - helpers: ``mpidr_mask_lower_afflvls``
422 - Secure Partition Manager (SPM)
423 - Boot-info structure
429 - Build System Issues
430 - dtb: DTB creation not supported when building on a Windows host.
432 This step in the build process is skipped when running on a Windows host. A
433 known issue from the 1.6 release.
436 - arm/juno: System suspend from Linux does not function as documented in the
439 Following the instructions provided in the user guide document does not
440 result in the platform entering system suspend state as expected. A message
441 relating to the hdlcd driver failing to suspend will be emitted on the
444 - arm/juno: The firmware update use-cases do not work with motherboard
445 firmware version < v1.5.0 (the reset reason is not preserved). The Linaro
446 18.04 release has MB v1.4.9. The MB v1.5.0 is available in Linaro 18.10
449 - mediatek/mt6795: This platform does not build in this release
457 - Removal of a number of deprecated APIs
459 - A new Platform Compatibility Policy document has been created which
460 references a wiki page that maintains a listing of deprecated
461 interfaces and the release after which they will be removed.
463 - All deprecated interfaces except the MULTI_CONSOLE_API have been removed
466 - Various Arm and partner platforms have been updated to remove the use of
467 removed APIs in this release.
469 - This release is otherwise unchanged from 1.6 release
471 Issues resolved since last release
472 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
474 - No issues known at 1.6 release resolved in 2.0 release
479 - DTB creation not supported when building on a Windows host. This step in the
480 build process is skipped when running on a Windows host. Known issue from
483 - As a result of removal of deprecated interfaces the Nvidia Tegra, Marvell
484 Armada 8K and MediaTek MT6795 platforms do not build in this release.
485 Also MediaTek MT8173, NXP QorIQ LS1043A, NXP i.MX8QX, NXP i.MX8QMa,
486 Rockchip RK3328, Rockchip RK3368 and Rockchip RK3399 platforms have not been
487 confirmed to be working after the removal of the deprecated interfaces
488 although they do build.
496 - Addressing Speculation Security Vulnerabilities
498 - Implement static workaround for CVE-2018-3639 for AArch32 and AArch64
500 - Add support for dynamic mitigation for CVE-2018-3639
502 - Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
504 - Ensure |SDEI| handler executes with CVE-2018-3639 mitigation enabled
506 - Introduce RAS handling on AArch64
508 - Some RAS extensions are mandatory for Armv8.2 CPUs, with others
509 mandatory for Armv8.4 CPUs however, all extensions are also optional
510 extensions to the base Armv8.0 architecture.
512 - The Armv8 RAS Extensions introduced Standard Error Records which are a
513 set of standard registers to configure RAS node policy and allow RAS
514 Nodes to record and expose error information for error handling agents.
516 - Capabilities are provided to support RAS Node enumeration and iteration
517 along with individual interrupt registrations and fault injections
520 - Introduce handlers for Uncontainable errors, Double Faults and EL3
523 - Enable Memory Partitioning And Monitoring (MPAM) for lower EL's
525 - Memory Partitioning And Monitoring is an Armv8.4 feature that enables
526 various memory system components and resources to define partitions.
527 Software running at various ELs can then assign themselves to the
528 desired partition to control their performance aspects.
530 - When ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows
531 lower ELs to access their own MPAM registers without trapping to EL3.
532 This patch however, doesn't make use of partitioning in EL3; platform
533 initialisation code should configure and use partitions in EL3 if
536 - Introduce ROM Lib Feature
538 - Support combining several libraries into a self-called "romlib" image,
539 that may be shared across images to reduce memory footprint. The romlib
540 image is stored in ROM but is accessed through a jump-table that may be
541 stored in read-write memory, allowing for the library code to be patched.
543 - Introduce Backtrace Feature
545 - This function displays the backtrace, the current EL and security state
546 to allow a post-processing tool to choose the right binary to interpret
549 - Print backtrace in assert() and panic() to the console.
551 - Code hygiene changes and alignment with MISRA C-2012 guideline with fixes
552 addressing issues complying to the following rules:
554 - MISRA rules 4.9, 5.1, 5.3, 5.7, 8.2-8.5, 8.8, 8.13, 9.3, 10.1,
555 10.3-10.4, 10.8, 11.3, 11.6, 12.1, 14.4, 15.7, 16.1-16.7, 17.7-17.8,
556 20.7, 20.10, 20.12, 21.1, 21.15, 22.7
558 - Clean up the usage of void pointers to access symbols
560 - Increase usage of static qualifier to locally used functions and data
562 - Migrated to use of u_register_t for register read/write to better
563 match AArch32 and AArch64 type sizes
565 - Use int-ll64 for both AArch32 and AArch64 to assist in consistent
566 format strings between architectures
568 - Clean up TF-A libc by removing non arm copyrighted implementations
569 and replacing them with modified FreeBSD and SCC implementations
571 - Various changes to support Clang linker and assembler
573 - The clang assembler/preprocessor is used when Clang is selected. However,
574 the clang linker is not used because it is unable to link TF-A objects
575 due to immaturity of clang linker functionality at this time.
577 - Refactor support APIs into Libraries
579 - Evolve libfdt, mbed TLS library and standard C library sources as
580 proper libraries that TF-A may be linked against.
584 - Add CPU support for Cortex-Ares and Cortex-A76
586 - Add AMU support for Cortex-Ares
588 - Add initial CPU support for Cortex-Deimos
590 - Add initial CPU support for Cortex-Helios
592 - Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
594 - Implement Cortex-Ares erratum 1043202 workaround
596 - Implement DSU erratum 936184 workaround
598 - Check presence of fix for errata 843419 in Cortex-A53
600 - Check presence of fix for errata 835769 in Cortex-A53
602 - Translation Tables Enhancements
604 - The xlat v2 library has been refactored in order to be reused by
605 different TF components at different EL's including the addition of EL2.
606 Some refactoring to make the code more generic and less specific to TF,
607 in order to reuse the library outside of this project.
611 - General cleanups and refactoring to pave the way to multiple partitions
616 - Allow platforms to define explicit events
618 - Determine client EL from NS context's SCR_EL3
620 - Make dispatches synchronous
622 - Introduce jump primitives for BL31
624 - Mask events after CPU wakeup in |SDEI| dispatcher to conform to the
627 - Misc TF-A Core Common Code Enhancements
629 - Add support for eXecute In Place (XIP) memory in BL2
631 - Add support for the SMC Calling Convention 2.0
633 - Introduce External Abort handling on AArch64
634 External Abort routed to EL3 was reported as an unhandled exception
635 and caused a panic. This change enables Trusted Firmware-A to handle
636 External Aborts routed to EL3.
638 - Save value of ACTLR_EL1 implementation-defined register in the CPU
639 context structure rather than forcing it to 0.
641 - Introduce ARM_LINUX_KERNEL_AS_BL33 build option, which allows BL31 to
642 directly jump to a Linux kernel. This makes for a quicker and simpler
643 boot flow, which might be useful in some test environments.
645 - Add dynamic configurations for BL31, BL32 and BL33 enabling support for
646 Chain of Trust (COT).
648 - Make TF UUID RFC 4122 compliant
650 - New Platform Support
656 - Allwinner sun50i_64
658 - Allwinner sun50i_h6
666 - NXP i.MX7Solo WaRP7
670 - Socionext Synquacer SC2A11
674 - STMicroelectronics STM32MP1
676 - Misc Generic Platform Common Code Enhancements
678 - Add MMC framework that supports both eMMC and SD card devices
680 - Misc Arm Platform Common Code Enhancements
682 - Demonstrate PSCI MEM_PROTECT from el3_runtime
684 - Provide RAS support
686 - Migrate AArch64 port to the multi console driver. The old API is
687 deprecated and will eventually be removed.
689 - Move BL31 below BL2 to enable BL2 overlay resulting in changes in the
690 layout of BL images in memory to enable more efficient use of available
693 - Add cpp build processing for dtb that allows processing device tree
694 with external includes.
696 - Extend FIP io driver to support multiple FIP devices
698 - Add support for SCMI AP core configuration protocol v1.0
700 - Use SCMI AP core protocol to set the warm boot entrypoint
702 - Add support to Mbed TLS drivers for shared heap among different
703 BL images to help optimise memory usage
705 - Enable non-secure access to UART1 through a build option to support
706 a serial debug port for debugger connection
708 - Enhancements for Arm Juno Platform
710 - Add support for TrustZone Media Protection 1 (TZMP1)
712 - Enhancements for Arm FVP Platform
714 - Dynamic_config: remove the FVP dtb files
716 - Set DYNAMIC_WORKAROUND_CVE_2018_3639=1 on FVP by default
718 - Set the ability to dynamically disable Trusted Boot Board
719 authentication to be off by default with DYN_DISABLE_AUTH
721 - Add librom enhancement support in FVP
723 - Support shared Mbed TLS heap between BL1 and BL2 that allow a
724 reduction in BL2 size for FVP
726 - Enhancements for Arm SGI/SGM Platform
728 - Enable ARM_PLAT_MT flag for SGI-575
730 - Add dts files to enable support for dynamic config
734 - Support shared Mbed TLS heap for SGI and SGM between BL1 and BL2
736 - Enhancements for Non Arm Platforms
738 - Raspberry Pi Platform
746 - Rockchip rk3399 Platform
750 - Socionext Platforms
752 - Allwinner Platforms
756 - NVIDIA Tegra Platform
760 - STMicroelectronics STM32MP1 Platform
762 Issues resolved since last release
763 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
765 - No issues known at 1.5 release resolved in 1.6 release
770 - DTB creation not supported when building on a Windows host. This step in the
771 build process is skipped when running on a Windows host. Known issue from
780 - Added new firmware support to enable RAS (Reliability, Availability, and
781 Serviceability) functionality.
783 - Secure Partition Manager (SPM): A Secure Partition is a software execution
784 environment instantiated in S-EL0 that can be used to implement simple
785 management and security services. The SPM is the firmware component that
786 is responsible for managing a Secure Partition.
788 - SDEI dispatcher: Support for interrupt-based |SDEI| events and all
789 interfaces as defined by the |SDEI| specification v1.0, see
790 `SDEI Specification`_
792 - Exception Handling Framework (EHF): Framework that allows dispatching of
793 EL3 interrupts to their registered handlers which are registered based on
794 their priorities. Facilitates firmware-first error handling policy where
795 asynchronous exceptions may be routed to EL3.
797 Integrated the TSPD with EHF.
799 - Updated PSCI support:
801 - Implemented PSCI v1.1 optional features `MEM_PROTECT` and `SYSTEM_RESET2`.
802 The supported PSCI version was updated to v1.1.
804 - Improved PSCI STAT timestamp collection, including moving accounting for
805 retention states to be inside the locks and fixing handling of wrap-around
806 when calculating residency in AArch32 execution state.
808 - Added optional handler for early suspend that executes when suspending to
809 a power-down state and with data caches enabled.
811 This may provide a performance improvement on platforms where it is safe
812 to perform some or all of the platform actions from `pwr_domain_suspend`
813 with the data caches enabled.
815 - Enabled build option, BL2_AT_EL3, for BL2 to allow execution at EL3 without
816 any dependency on TF BL1.
818 This allows platforms which already have a non-TF Boot ROM to directly load
819 and execute BL2 and subsequent BL stages without need for BL1. This was not
820 previously possible because BL2 executes at S-EL1 and cannot jump straight to
823 - Implemented support for SMCCC v1.1, including `SMCCC_VERSION` and
824 `SMCCC_ARCH_FEATURES`.
826 Additionally, added support for `SMCCC_VERSION` in PSCI features to enable
827 discovery of the SMCCC version via PSCI feature call.
829 - Added Dynamic Configuration framework which enables each of the boot loader
830 stages to be dynamically configured at runtime if required by the platform.
831 The boot loader stage may optionally specify a firmware configuration file
832 and/or hardware configuration file that can then be shared with the next boot
835 Introduced a new BL handover interface that essentially allows passing of 4
836 arguments between the different BL stages.
838 Updated cert_create and fip_tool to support the dynamic configuration files.
839 The COT also updated to support these new files.
841 - Code hygiene changes and alignment with MISRA guideline:
843 - Fix use of undefined macros.
845 - Achieved compliance with Mandatory MISRA coding rules.
847 - Achieved compliance for following Required MISRA rules for the default
848 build configurations on FVP and Juno platforms : 7.3, 8.3, 8.4, 8.5 and
851 - Added support for Armv8.2-A architectural features:
853 - Updated translation table set-up to set the CnP (Common not Private) bit
854 for secure page tables so that multiple PEs in the same Inner Shareable
855 domain can use the same translation table entries for a given stage of
856 translation in a particular translation regime.
858 - Extended the supported values of ID_AA64MMFR0_EL1.PARange to include the
859 52-bit Physical Address range.
861 - Added support for the Scalable Vector Extension to allow Normal world
862 software to access SVE functionality but disable access to SVE, SIMD and
863 floating point functionality from the Secure world in order to prevent
864 corruption of the Z-registers.
866 - Added support for Armv8.4-A architectural feature Activity Monitor Unit (AMU)
869 In addition to the v8.4 architectural extension, AMU support on Cortex-A75
872 - Enhanced OP-TEE support to enable use of pageable OP-TEE image. The Arm
873 standard platforms are updated to load up to 3 images for OP-TEE; header,
874 pager image and paged image.
876 The chain of trust is extended to support the additional images.
878 - Enhancements to the translation table library:
880 - Introduced APIs to get and set the memory attributes of a region.
882 - Added support to manage both privilege levels in translation regimes that
883 describe translations for 2 Exception levels, specifically the EL1&0
884 translation regime, and extended the memory map region attributes to
885 include specifying Non-privileged access.
887 - Added support to specify the granularity of the mappings of each region,
888 for instance a 2MB region can be specified to be mapped with 4KB page
889 tables instead of a 2MB block.
891 - Disabled the higher VA range to avoid unpredictable behaviour if there is
892 an attempt to access addresses in the higher VA range.
894 - Added helpers for Device and Normal memory MAIR encodings that align with
895 the Arm Architecture Reference Manual for Armv8-A (Arm DDI0487B.b).
897 - Code hygiene including fixing type length and signedness of constants,
898 refactoring of function to enable the MMU, removing all instances where
899 the virtual address space is hardcoded and added comments that document
900 alignment needed between memory attributes and attributes specified in
903 - Updated GIC support:
905 - Introduce new APIs for GICv2 and GICv3 that provide the capability to
906 specify interrupt properties rather than list of interrupt numbers alone.
907 The Arm platforms and other upstream platforms are migrated to use
908 interrupt properties.
910 - Added helpers to save / restore the GICv3 context, specifically the
911 Distributor and Redistributor contexts and architectural parts of the ITS
912 power management. The Distributor and Redistributor helpers also support
913 the implementation-defined part of GIC-500 and GIC-600.
915 Updated the Arm FVP platform to save / restore the GICv3 context on system
916 suspend / resume as an example of how to use the helpers.
918 Introduced a new TZC secured DDR carve-out for use by Arm platforms for
919 storing EL3 runtime data such as the GICv3 register context.
921 - Added support for Armv7-A architecture via build option ARM_ARCH_MAJOR=7.
922 This includes following features:
924 - Updates GICv2 driver to manage GICv1 with security extensions.
926 - Software implementation for 32bit division.
928 - Enabled use of generic timer for platforms that do not set
931 - Support for Armv7-A Virtualization extensions [DDI0406C_C].
933 - Support for both Armv7-A platforms that only have 32-bit addressing and
934 Armv7-A platforms that support large page addressing.
936 - Included support for following Armv7 CPUs: Cortex-A12, Cortex-A17,
937 Cortex-A7, Cortex-A5, Cortex-A9, Cortex-A15.
939 - Added support in QEMU for Armv7-A/Cortex-A15.
941 - Enhancements to Firmware Update feature:
943 - Updated the FWU documentation to describe the additional images needed for
944 Firmware update, and how they are used for both the Juno platform and the
947 - Enhancements to Trusted Board Boot feature:
949 - Added support to cert_create tool for RSA PKCS1# v1.5 and SHA384, SHA512
952 - For Arm platforms added support to use ECDSA keys.
954 - Enhanced the mbed TLS wrapper layer to include support for both RSA and
955 ECDSA to enable runtime selection between RSA and ECDSA keys.
957 - Added support for secure interrupt handling in AArch32 sp_min, hardcoded to
960 - Added support to allow a platform to load images from multiple boot sources,
961 for example from a second flash drive.
963 - Added a logging framework that allows platforms to reduce the logging level
964 at runtime and additionally the prefix string can be defined by the platform.
966 - Further improvements to register initialisation:
968 - Control register PMCR_EL0 / PMCR is set to prohibit cycle counting in the
969 secure world. This register is added to the list of registers that are
970 saved and restored during world switch.
972 - When EL3 is running in AArch32 execution state, the Non-secure version of
973 SCTLR is explicitly initialised during the warmboot flow rather than
974 relying on the hardware to set the correct reset values.
976 - Enhanced support for Arm platforms:
978 - Introduced driver for Shared-Data-Structure (SDS) framework which is used
979 for communication between SCP and the AP CPU, replacing Boot-Over_MHU
982 The Juno platform is migrated to use SDS with the SCMI support added in
983 v1.3 and is set as default.
985 The driver can be found in the plat/arm/css/drivers folder.
987 - Improved memory usage by only mapping TSP memory region when the TSPD has
988 been included in the build. This reduces the memory footprint and avoids
989 unnecessary memory being mapped.
991 - Updated support for multi-threading CPUs for FVP platforms - always check
992 the MT field in MPDIR and access the bit fields accordingly.
994 - Support building for platforms that model DynamIQ configuration by
995 implementing all CPUs in a single cluster.
997 - Improved nor flash driver, for instance clearing status registers before
998 sending commands. Driver can be found plat/arm/board/common folder.
1000 - Enhancements to QEMU platform:
1002 - Added support for TBB.
1004 - Added support for using OP-TEE pageable image.
1006 - Added support for LOAD_IMAGE_V2.
1008 - Migrated to use translation table library v2 by default.
1010 - Added support for SEPARATE_CODE_AND_RODATA.
1012 - Applied workarounds CVE-2017-5715 on Arm Cortex-A57, -A72, -A73 and -A75, and
1013 for Armv7-A CPUs Cortex-A9, -A15 and -A17.
1015 - Applied errata workaround for Arm Cortex-A57: 859972.
1017 - Applied errata workaround for Arm Cortex-A72: 859971.
1019 - Added support for Poplar 96Board platform.
1021 - Added support for Raspberry Pi 3 platform.
1023 - Added Call Frame Information (CFI) assembler directives to the vector entries
1024 which enables debuggers to display the backtrace of functions that triggered
1025 a synchronous abort.
1027 - Added ability to build dtb.
1029 - Added support for pre-tool (cert_create and fiptool) image processing
1030 enabling compression of the image files before processing by cert_create and
1033 This can reduce fip size and may also speed up loading of images. The image
1034 verification will also get faster because certificates are generated based on
1037 Imported zlib 1.2.11 to implement gunzip() for data compression.
1039 - Enhancements to fiptool:
1041 - Enabled the fiptool to be built using Visual Studio.
1043 - Added padding bytes at the end of the last image in the fip to be
1044 facilitate transfer by DMA.
1046 Issues resolved since last release
1047 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1049 - TF-A can be built with optimisations disabled (-O0).
1051 - Memory layout updated to enable Trusted Board Boot on Juno platform when
1052 running TF-A in AArch32 execution mode (resolving `tf-issue#501`_).
1057 - DTB creation not supported when building on a Windows host. This step in the
1058 build process is skipped when running on a Windows host.
1066 - Enabled support for platforms with hardware assisted coherency.
1068 A new build option HW_ASSISTED_COHERENCY allows platforms to take advantage
1069 of the following optimisations:
1071 - Skip performing cache maintenance during power-up and power-down.
1073 - Use spin-locks instead of bakery locks.
1075 - Enable data caches early on warm-booted CPUs.
1077 - Added support for Cortex-A75 and Cortex-A55 processors.
1079 Both Cortex-A75 and Cortex-A55 processors use the Arm DynamIQ Shared Unit
1080 (DSU). The power-down and power-up sequences are therefore mostly managed in
1081 hardware, reducing complexity of the software operations.
1083 - Introduced Arm GIC-600 driver.
1085 Arm GIC-600 IP complies with Arm GICv3 architecture. For FVP platforms, the
1086 GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600.
1088 - Updated GICv3 support:
1090 - Introduced power management APIs for GICv3 Redistributor. These APIs
1091 allow platforms to power down the Redistributor during CPU power on/off.
1092 Requires the GICv3 implementations to have power management operations.
1094 Implemented the power management APIs for FVP.
1096 - GIC driver data is flushed by the primary CPU so that secondary CPU do
1097 not read stale GIC data.
1099 - Added support for Arm System Control and Management Interface v1.0 (SCMI).
1101 The SCMI driver implements the power domain management and system power
1102 management protocol of the SCMI specification (Arm DEN 0056ASCMI) for
1103 communicating with any compliant power controller.
1105 Support is added for the Juno platform. The driver can be found in the
1106 plat/arm/css/drivers folder.
1108 - Added support to enable pre-integration of TBB with the Arm TrustZone
1109 CryptoCell product, to take advantage of its hardware Root of Trust and
1110 crypto acceleration services.
1112 - Enabled Statistical Profiling Extensions for lower ELs.
1114 The firmware support is limited to the use of SPE in the Non-secure state
1115 and accesses to the SPE specific registers from S-EL1 will trap to EL3.
1117 The SPE are architecturally specified for AArch64 only.
1119 - Code hygiene changes aligned with MISRA guidelines:
1121 - Fixed signed / unsigned comparison warnings in the translation table
1124 - Added U(_x) macro and together with the existing ULL(_x) macro fixed
1125 some of the signed-ness defects flagged by the MISRA scanner.
1127 - Enhancements to Firmware Update feature:
1129 - The FWU logic now checks for overlapping images to prevent execution of
1130 unauthenticated arbitrary code.
1132 - Introduced new FWU_SMC_IMAGE_RESET SMC that changes the image loading
1133 state machine to go from COPYING, COPIED or AUTHENTICATED states to
1134 RESET state. Previously, this was only possible when the authentication
1135 of an image failed or when the execution of the image finished.
1137 - Fixed integer overflow which addressed TFV-1: Malformed Firmware Update
1138 SMC can result in copy of unexpectedly large data into secure memory.
1140 - Introduced support for Arm Compiler 6 and LLVM (clang).
1142 TF-A can now also be built with the Arm Compiler 6 or the clang compilers.
1143 The assembler and linker must be provided by the GNU toolchain.
1145 Tested with Arm CC 6.7 and clang 3.9.x and 4.0.x.
1147 - Memory footprint improvements:
1149 - Introduced `tf_snprintf`, a reduced version of `snprintf` which has
1150 support for a limited set of formats.
1152 The mbedtls driver is updated to optionally use `tf_snprintf` instead of
1155 - The `assert()` is updated to no longer print the function name, and
1156 additional logging options are supported via an optional platform define
1157 `PLAT_LOG_LEVEL_ASSERT`, which controls how verbose the assert output is.
1159 - Enhancements to TF-A support when running in AArch32 execution state:
1161 - Support booting SP_MIN and BL33 in AArch32 execution mode on Juno. Due to
1162 hardware limitations, BL1 and BL2 boot in AArch64 state and there is
1163 additional trampoline code to warm reset into SP_MIN in AArch32 execution
1166 - Added support for Arm Cortex-A53/57/72 MPCore processors including the
1167 errata workarounds that are already implemented for AArch64 execution
1170 - For FVP platforms, added AArch32 Trusted Board Boot support, including the
1171 Firmware Update feature.
1173 - Introduced Arm SiP service for use by Arm standard platforms.
1175 - Added new Arm SiP Service SMCs to enable the Non-secure world to read PMF
1178 Added PMF instrumentation points in TF-A in order to quantify the
1179 overall time spent in the PSCI software implementation.
1181 - Added new Arm SiP service SMC to switch execution state.
1183 This allows the lower exception level to change its execution state from
1184 AArch64 to AArch32, or vice verse, via a request to EL3.
1186 - Migrated to use SPDX[0] license identifiers to make software license
1190 Files that have been imported by FreeBSD have not been modified.
1192 [0]: https://spdx.org/
1194 - Enhancements to the translation table library:
1196 - Added version 2 of translation table library that allows different
1197 translation tables to be modified by using different 'contexts'. Version 1
1198 of the translation table library only allows the current EL's translation
1199 tables to be modified.
1201 Version 2 of the translation table also added support for dynamic
1202 regions; regions that can be added and removed dynamically whilst the
1203 MMU is enabled. Static regions can only be added or removed before the
1206 The dynamic mapping functionality is enabled or disabled when compiling
1207 by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1 or 0. This can
1210 - Added support for translation regimes with two virtual address spaces
1211 such as the one shared by EL1 and EL0.
1213 The library does not support initializing translation tables for EL0
1216 - Added support to mark the translation tables as non-cacheable using an
1217 additional build option `XLAT_TABLE_NC`.
1219 - Added support for GCC stack protection. A new build option
1220 ENABLE_STACK_PROTECTOR was introduced that enables compilation of all BL
1221 images with one of the GCC -fstack-protector-* options.
1223 A new platform function plat_get_stack_protector_canary() was introduced
1224 that returns a value used to initialize the canary for stack corruption
1225 detection. For increased effectiveness of protection platforms must provide
1226 an implementation that returns a random value.
1228 - Enhanced support for Arm platforms:
1230 - Added support for multi-threading CPUs, indicated by `MT` field in MPDIR.
1231 A new build flag `ARM_PLAT_MT` is added, and when enabled, the functions
1232 accessing MPIDR assume that the `MT` bit is set for the platform and
1233 access the bit fields accordingly.
1235 Also, a new API `plat_arm_get_cpu_pe_count` is added when `ARM_PLAT_MT` is
1236 enabled, returning the Processing Element count within the physical CPU
1237 corresponding to `mpidr`.
1239 - The Arm platforms migrated to use version 2 of the translation tables.
1241 - Introduced a new Arm platform layer API `plat_arm_psci_override_pm_ops`
1242 which allows Arm platforms to modify `plat_arm_psci_pm_ops` and therefore
1243 dynamically define PSCI capability.
1245 - The Arm platforms migrated to use IMAGE_LOAD_V2 by default.
1247 - Enhanced reporting of errata workaround status with the following policy:
1249 - If an errata workaround is enabled:
1251 - If it applies (i.e. the CPU is affected by the errata), an INFO message
1252 is printed, confirming that the errata workaround has been applied.
1254 - If it does not apply, a VERBOSE message is printed, confirming that the
1255 errata workaround has been skipped.
1257 - If an errata workaround is not enabled, but would have applied had it
1258 been, a WARN message is printed, alerting that errata workaround is
1261 - Added build options ARM_ARCH_MAJOR and ARM_ARM_MINOR to choose the
1262 architecture version to target TF-A.
1264 - Updated the spin lock implementation to use the more efficient CAS (Compare
1265 And Swap) instruction when available. This instruction was introduced in
1268 - Applied errata workaround for Arm Cortex-A53: 855873.
1270 - Applied errata workaround for Arm-Cortex-A57: 813419.
1272 - Enabled all A53 and A57 errata workarounds for Juno, both in AArch64 and
1273 AArch32 execution states.
1275 - Added support for Socionext UniPhier SoC platform.
1277 - Added support for Hikey960 and Hikey platforms.
1279 - Added support for Rockchip RK3328 platform.
1281 - Added support for NVidia Tegra T186 platform.
1283 - Added support for Designware emmc driver.
1285 - Imported libfdt v1.4.2 that addresses buffer overflow in fdt_offset_ptr().
1287 - Enhanced the CPU operations framework to allow power handlers to be
1288 registered on per-level basis. This enables support for future CPUs that
1289 have multiple threads which might need powering down individually.
1291 - Updated register initialisation to prevent unexpected behaviour:
1293 - Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
1294 unexpected traps into the higher exception levels and disable secure
1295 self-hosted debug. Additionally, secure privileged external debug on
1296 Juno is disabled by programming the appropriate Juno SoC registers.
1298 - EL2 and EL3 configurable controls are initialised to avoid unexpected
1299 traps in the higher exception levels.
1301 - Essential control registers are fully initialised on EL3 start-up, when
1302 initialising the non-secure and secure context structures and when
1303 preparing to leave EL3 for a lower EL. This gives better alignment with
1304 the Arm ARM which states that software must initialise RES0 and RES1
1307 - Enhanced PSCI support:
1309 - Introduced new platform interfaces that decouple PSCI stat residency
1310 calculation from PMF, enabling platforms to use alternative methods of
1311 capturing timestamps.
1313 - PSCI stat accounting performed for retention/standby states when
1314 requested at multiple power levels.
1316 - Simplified fiptool to have a single linked list of image descriptors.
1318 - For the TSP, resolved corruption of pre-empted secure context by aborting any
1319 pre-empted SMC during PSCI power management requests.
1321 Issues resolved since last release
1322 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1324 - TF-A can be built with the latest mbed TLS version (v2.4.2). The earlier
1325 version 2.3.0 cannot be used due to build warnings that the TF-A build
1326 system interprets as errors.
1328 - TBBR, including the Firmware Update feature is now supported on FVP
1329 platforms when running TF-A in AArch32 state.
1331 - The version of the AEMv8 Base FVP used in this release has resolved the issue
1332 of the model executing a reset instead of terminating in response to a
1333 shutdown request using the PSCI SYSTEM_OFF API.
1338 - Building TF-A with compiler optimisations disabled (-O0) fails.
1340 - Trusted Board Boot currently does not work on Juno when running Trusted
1341 Firmware in AArch32 execution state due to error when loading the sp_min to
1342 memory because of lack of free space available. See `tf-issue#501`_ for more
1345 - The errata workaround for A53 errata 843419 is only available from binutils
1346 2.26 and is not present in GCC4.9. If this errata is applicable to the
1347 platform, please use GCC compiler version of at least 5.0. See `PR#1002`_ for
1357 - Added support for running TF-A in AArch32 execution state.
1359 The PSCI library has been refactored to allow integration with **EL3 Runtime
1360 Software**. This is software that is executing at the highest secure
1361 privilege which is EL3 in AArch64 or Secure SVC/Monitor mode in AArch32. See
1362 :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
1364 Included is a minimal AArch32 Secure Payload, **SP-MIN**, that illustrates
1365 the usage and integration of the PSCI library with EL3 Runtime Software
1366 running in AArch32 state.
1368 Booting to the BL1/BL2 images as well as booting straight to the Secure
1369 Payload is supported.
1371 - Improvements to the initialization framework for the PSCI service and Arm
1372 Standard Services in general.
1374 The PSCI service is now initialized as part of Arm Standard Service
1375 initialization. This consolidates the initializations of any Arm Standard
1376 Service that may be added in the future.
1378 A new function ``get_arm_std_svc_args()`` is introduced to get arguments
1379 corresponding to each standard service and must be implemented by the EL3
1382 For PSCI, a new versioned structure ``psci_lib_args_t`` is introduced to
1383 initialize the PSCI Library. **Note** this is a compatibility break due to
1384 the change in the prototype of ``psci_setup()``.
1386 - To support AArch32 builds of BL1 and BL2, implemented a new, alternative
1387 firmware image loading mechanism that adds flexibility.
1389 The current mechanism has a hard-coded set of images and execution order
1390 (BL31, BL32, etc). The new mechanism is data-driven by a list of image
1391 descriptors provided by the platform code.
1393 Arm platforms have been updated to support the new loading mechanism.
1395 The new mechanism is enabled by a build flag (``LOAD_IMAGE_V2``) which is
1396 currently off by default for the AArch64 build.
1398 **Note** ``TRUSTED_BOARD_BOOT`` is currently not supported when
1399 ``LOAD_IMAGE_V2`` is enabled.
1401 - Updated requirements for making contributions to TF-A.
1403 Commits now must have a 'Signed-off-by:' field to certify that the
1404 contribution has been made under the terms of the
1405 :download:`Developer Certificate of Origin <../dco.txt>`.
1407 A signed CLA is no longer required.
1409 The :ref:`Contributor's Guide` has been updated to reflect this change.
1411 - Introduced Performance Measurement Framework (PMF) which provides support
1412 for capturing, storing, dumping and retrieving time-stamps to measure the
1413 execution time of critical paths in the firmware. This relies on defining
1414 fixed sample points at key places in the code.
1416 - To support the QEMU platform port, imported libfdt v1.4.1 from
1417 https://git.kernel.org/pub/scm/utils/dtc/dtc.git
1419 - Updated PSCI support:
1421 - Added support for PSCI NODE_HW_STATE API for Arm platforms.
1423 - New optional platform hook, ``pwr_domain_pwr_down_wfi()``, in
1424 ``plat_psci_ops`` to enable platforms to perform platform-specific actions
1425 needed to enter powerdown, including the 'wfi' invocation.
1427 - PSCI STAT residency and count functions have been added on Arm platforms
1430 - Enhancements to the translation table library:
1432 - Limited memory mapping support for region overlaps to only allow regions
1433 to overlap that are identity mapped or have the same virtual to physical
1434 address offset, and overlap completely but must not cover the same area.
1436 This limitation will enable future enhancements without having to
1437 support complex edge cases that may not be necessary.
1439 - The initial translation lookup level is now inferred from the virtual
1440 address space size. Previously, it was hard-coded.
1442 - Added support for mapping Normal, Inner Non-cacheable, Outer
1443 Non-cacheable memory in the translation table library.
1445 This can be useful to map a non-cacheable memory region, such as a DMA
1448 - Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to
1449 specify the access permissions for instruction execution of a memory
1452 - Enabled support to isolate code and read-only data on separate memory pages,
1453 allowing independent access control to be applied to each.
1455 - Enabled SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common
1456 architectural setup code, preventing fetching instructions from non-secure
1457 memory when in secure state.
1459 - Enhancements to FIP support:
1461 - Replaced ``fip_create`` with ``fiptool`` which provides a more consistent
1462 and intuitive interface as well as additional support to remove an image
1465 - Enabled printing the SHA256 digest with info command, allowing quick
1466 verification of an image within a FIP without having to extract the
1467 image and running sha256sum on it.
1469 - Added support for unpacking the contents of an existing FIP file into
1470 the working directory.
1472 - Aligned command line options for specifying images to use same naming
1473 convention as specified by TBBR and already used in cert_create tool.
1475 - Refactored the TZC-400 driver to also support memory controllers that
1476 integrate TZC functionality, for example Arm CoreLink DMC-500. Also added
1477 DMC-500 specific support.
1479 - Implemented generic delay timer based on the system generic counter and
1480 migrated all platforms to use it.
1482 - Enhanced support for Arm platforms:
1484 - Updated image loading support to make SCP images (SCP_BL2 and SCP_BL2U)
1487 - Enhanced topology description support to allow multi-cluster topology
1490 - Added interconnect abstraction layer to help platform ports select the
1491 right interconnect driver, CCI or CCN, for the platform.
1493 - Added support to allow loading BL31 in the TZC-secured DRAM instead of
1494 the default secure SRAM.
1496 - Added support to use a System Security Control (SSC) Registers Unit
1497 enabling TF-A to be compiled to support multiple Arm platforms and
1498 then select one at runtime.
1500 - Restricted mapping of Trusted ROM in BL1 to what is actually needed by
1501 BL1 rather than entire Trusted ROM region.
1503 - Flash is now mapped as execute-never by default. This increases security
1504 by restricting the executable region to what is strictly needed.
1506 - Applied following erratum workarounds for Cortex-A57: 833471, 826977,
1507 829520, 828024 and 826974.
1509 - Added support for Mediatek MT6795 platform.
1511 - Added support for QEMU virtualization Armv8-A target.
1513 - Added support for Rockchip RK3368 and RK3399 platforms.
1515 - Added support for Xilinx Zynq UltraScale+ MPSoC platform.
1517 - Added support for Arm Cortex-A73 MPCore Processor.
1519 - Added support for Arm Cortex-A72 processor.
1521 - Added support for Arm Cortex-A35 processor.
1523 - Added support for Arm Cortex-A32 MPCore Processor.
1525 - Enabled preloaded BL33 alternative boot flow, in which BL2 does not load
1526 BL33 from non-volatile storage and BL31 hands execution over to a preloaded
1527 BL33. The User Guide has been updated with an example of how to use this
1528 option with a bootwrapped kernel.
1530 - Added support to build TF-A on a Windows-based host machine.
1532 - Updated Trusted Board Boot prototype implementation:
1534 - Enabled the ability for a production ROM with TBBR enabled to boot test
1535 software before a real ROTPK is deployed (e.g. manufacturing mode).
1536 Added support to use ROTPK in certificate without verifying against the
1537 platform value when ``ROTPK_NOT_DEPLOYED`` bit is set.
1539 - Added support for non-volatile counter authentication to the
1540 Authentication Module to protect against roll-back.
1542 - Updated GICv3 support:
1544 - Enabled processor power-down and automatic power-on using GICv3.
1546 - Enabled G1S or G0 interrupts to be configured independently.
1548 - Changed FVP default interrupt driver to be the GICv3-only driver.
1549 **Note** the default build of TF-A will not be able to boot
1550 Linux kernel with GICv2 FDT blob.
1552 - Enabled wake-up from CPU_SUSPEND to stand-by by temporarily re-routing
1553 interrupts and then restoring after resume.
1555 Issues resolved since last release
1556 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1561 - The version of the AEMv8 Base FVP used in this release resets the model
1562 instead of terminating its execution in response to a shutdown request using
1563 the PSCI ``SYSTEM_OFF`` API. This issue will be fixed in a future version of
1566 - Building TF-A with compiler optimisations disabled (``-O0``) fails.
1568 - TF-A cannot be built with mbed TLS version v2.3.0 due to build warnings
1569 that the TF-A build system interprets as errors.
1571 - TBBR is not currently supported when running TF-A in AArch32 state.
1579 - The Trusted Board Boot implementation on Arm platforms now conforms to the
1580 mandatory requirements of the TBBR specification.
1582 In particular, the boot process is now guarded by a Trusted Watchdog, which
1583 will reset the system in case of an authentication or loading error. On Arm
1584 platforms, a secure instance of Arm SP805 is used as the Trusted Watchdog.
1586 Also, a firmware update process has been implemented. It enables
1587 authenticated firmware to update firmware images from external interfaces to
1588 SoC Non-Volatile memories. This feature functions even when the current
1589 firmware in the system is corrupt or missing; it therefore may be used as
1592 - Improvements have been made to the Certificate Generation Tool
1593 (``cert_create``) as follows.
1595 - Added support for the Firmware Update process by extending the Chain
1596 of Trust definition in the tool to include the Firmware Update
1597 certificate and the required extensions.
1599 - Introduced a new API that allows one to specify command line options in
1600 the Chain of Trust description. This makes the declaration of the tool's
1601 arguments more flexible and easier to extend.
1603 - The tool has been reworked to follow a data driven approach, which
1604 makes it easier to maintain and extend.
1606 - Extended the FIP tool (``fip_create``) to support the new set of images
1607 involved in the Firmware Update process.
1609 - Various memory footprint improvements. In particular:
1611 - The bakery lock structure for coherent memory has been optimised.
1613 - The mbed TLS SHA1 functions are not needed, as SHA256 is used to
1614 generate the certificate signature. Therefore, they have been compiled
1615 out, reducing the memory footprint of BL1 and BL2 by approximately
1618 - On Arm development platforms, each BL stage now individually defines
1619 the number of regions that it needs to map in the MMU.
1621 - Added the following new design documents:
1623 - :ref:`Authentication Framework & Chain of Trust`
1624 - :ref:`Firmware Update (FWU)`
1626 - :ref:`PSCI Power Domain Tree Structure`
1628 - Applied the new image terminology to the code base and documentation, as
1629 described in the :ref:`Image Terminology` document.
1631 - The build system has been reworked to improve readability and facilitate
1632 adding future extensions.
1634 - On Arm standard platforms, BL31 uses the boot console during cold boot
1635 but switches to the runtime console for any later logs at runtime. The TSP
1636 uses the runtime console for all output.
1638 - Implemented a basic NOR flash driver for Arm platforms. It programs the
1639 device using CFI (Common Flash Interface) standard commands.
1641 - Implemented support for booting EL3 payloads on Arm platforms, which
1642 reduces the complexity of developing EL3 baremetal code by doing essential
1643 baremetal initialization.
1645 - Provided separate drivers for GICv3 and GICv2. These expect the entire
1646 software stack to use either GICv2 or GICv3; hybrid GIC software systems
1647 are no longer supported and the legacy Arm GIC driver has been deprecated.
1649 - Added support for Juno r1 and r2. A single set of Juno TF-A binaries can run
1650 on Juno r0, r1 and r2 boards. Note that this TF-A version depends on a Linaro
1651 release that does *not* contain Juno r2 support.
1653 - Added support for MediaTek mt8173 platform.
1655 - Implemented a generic driver for Arm CCN IP.
1657 - Major rework of the PSCI implementation.
1659 - Added framework to handle composite power states.
1661 - Decoupled the notions of affinity instances (which describes the
1662 hierarchical arrangement of cores) and of power domain topology, instead
1663 of assuming a one-to-one mapping.
1665 - Better alignment with version 1.0 of the PSCI specification.
1667 - Added support for the SYSTEM_SUSPEND PSCI API on Arm platforms. When invoked
1668 on the last running core on a supported platform, this puts the system
1669 into a low power mode with memory retention.
1671 - Unified the reset handling code as much as possible across BL stages.
1672 Also introduced some build options to enable optimization of the reset path
1673 on platforms that support it.
1675 - Added a simple delay timer API, as well as an SP804 timer driver, which is
1678 - Added support for NVidia Tegra T210 and T132 SoCs.
1680 - Reorganised Arm platforms ports to greatly improve code shareability and
1681 facilitate the reuse of some of this code by other platforms.
1683 - Added support for Arm Cortex-A72 processor in the CPU specific framework.
1685 - Provided better error handling. Platform ports can now define their own
1686 error handling, for example to perform platform specific bookkeeping or
1689 - Implemented a unified driver for Arm Cache Coherent Interconnects used for
1690 both CCI-400 & CCI-500 IPs. Arm platforms ports have been migrated to this
1691 common driver. The standalone CCI-400 driver has been deprecated.
1693 Issues resolved since last release
1694 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1696 - The Trusted Board Boot implementation has been redesigned to provide greater
1697 modularity and scalability. See the
1698 :ref:`Authentication Framework & Chain of Trust` document.
1699 All missing mandatory features are now implemented.
1701 - The FVP and Juno ports may now use the hash of the ROTPK stored in the
1702 Trusted Key Storage registers to verify the ROTPK. Alternatively, a
1703 development public key hash embedded in the BL1 and BL2 binaries might be
1704 used instead. The location of the ROTPK is chosen at build-time using the
1705 ``ARM_ROTPK_LOCATION`` build option.
1707 - GICv3 is now fully supported and stable.
1712 - The version of the AEMv8 Base FVP used in this release resets the model
1713 instead of terminating its execution in response to a shutdown request using
1714 the PSCI ``SYSTEM_OFF`` API. This issue will be fixed in a future version of
1717 - While this version has low on-chip RAM requirements, there are further
1718 RAM usage enhancements that could be made.
1720 - The upstream documentation could be improved for structural consistency,
1721 clarity and completeness. In particular, the design documentation is
1722 incomplete for PSCI, the TSP(D) and the Juno platform.
1724 - Building TF-A with compiler optimisations disabled (``-O0``) fails.
1732 - A prototype implementation of Trusted Board Boot has been added. Boot
1733 loader images are verified by BL1 and BL2 during the cold boot path. BL1 and
1734 BL2 use the PolarSSL SSL library to verify certificates and images. The
1735 OpenSSL library is used to create the X.509 certificates. Support has been
1736 added to ``fip_create`` tool to package the certificates in a FIP.
1738 - Support for calling CPU and platform specific reset handlers upon entry into
1739 BL3-1 during the cold and warm boot paths has been added. This happens after
1740 another Boot ROM ``reset_handler()`` has already run. This enables a developer
1741 to perform additional actions or undo actions already performed during the
1742 first call of the reset handlers e.g. apply additional errata workarounds.
1744 - Support has been added to demonstrate routing of IRQs to EL3 instead of
1745 S-EL1 when execution is in secure world.
1747 - The PSCI implementation now conforms to version 1.0 of the PSCI
1748 specification. All the mandatory APIs and selected optional APIs are
1749 supported. In particular, support for the ``PSCI_FEATURES`` API has been
1750 added. A capability variable is constructed during initialization by
1751 examining the ``plat_pm_ops`` and ``spd_pm_ops`` exported by the platform and
1752 the Secure Payload Dispatcher. This is used by the PSCI FEATURES function
1753 to determine which PSCI APIs are supported by the platform.
1755 - Improvements have been made to the PSCI code as follows.
1757 - The code has been refactored to remove redundant parameters from
1760 - Changes have been made to the code for PSCI ``CPU_SUSPEND``, ``CPU_ON`` and
1761 ``CPU_OFF`` calls to facilitate an early return to the caller in case a
1762 failure condition is detected. For example, a PSCI ``CPU_SUSPEND`` call
1763 returns ``SUCCESS`` to the caller if a pending interrupt is detected early
1766 - Optional platform APIs have been added to validate the ``power_state`` and
1767 ``entrypoint`` parameters early in PSCI ``CPU_ON`` and ``CPU_SUSPEND`` code
1770 - PSCI migrate APIs have been reworked to invoke the SPD hook to determine
1771 the type of Trusted OS and the CPU it is resident on (if
1772 applicable). Also, during a PSCI ``MIGRATE`` call, the SPD hook to migrate
1773 the Trusted OS is invoked.
1775 - It is now possible to build TF-A without marking at least an extra page of
1776 memory as coherent. The build flag ``USE_COHERENT_MEM`` can be used to
1777 choose between the two implementations. This has been made possible through
1780 - An implementation of Bakery locks, where the locks are not allocated in
1781 coherent memory has been added.
1783 - Memory which was previously marked as coherent is now kept coherent
1784 through the use of software cache maintenance operations.
1786 Approximately, 4K worth of memory is saved for each boot loader stage when
1787 ``USE_COHERENT_MEM=0``. Enabling this option increases the latencies
1788 associated with acquire and release of locks. It also requires changes to
1791 - It is now possible to specify the name of the FIP at build time by defining
1792 the ``FIP_NAME`` variable.
1794 - Issues with dependencies on the 'fiptool' makefile target have been
1795 rectified. The ``fip_create`` tool is now rebuilt whenever its source files
1798 - The BL3-1 runtime console is now also used as the crash console. The crash
1799 console is changed to SoC UART0 (UART2) from the previous FPGA UART0 (UART0)
1800 on Juno. In FVP, it is changed from UART0 to UART1.
1802 - CPU errata workarounds are applied only when the revision and part number
1803 match. This behaviour has been made consistent across the debug and release
1804 builds. The debug build additionally prints a warning if a mismatch is
1807 - It is now possible to issue cache maintenance operations by set/way for a
1808 particular level of data cache. Levels 1-3 are currently supported.
1810 - The following improvements have been made to the FVP port.
1812 - The build option ``FVP_SHARED_DATA_LOCATION`` which allowed relocation of
1813 shared data into the Trusted DRAM has been deprecated. Shared data is
1814 now always located at the base of Trusted SRAM.
1816 - BL2 Translation tables have been updated to map only the region of
1817 DRAM which is accessible to normal world. This is the region of the 2GB
1818 DDR-DRAM memory at 0x80000000 excluding the top 16MB. The top 16MB is
1819 accessible to only the secure world.
1821 - BL3-2 can now reside in the top 16MB of DRAM which is accessible only to
1822 the secure world. This can be done by setting the build flag
1823 ``FVP_TSP_RAM_LOCATION`` to the value ``dram``.
1825 - Separate translation tables are created for each boot loader image. The
1826 ``IMAGE_BLx`` build options are used to do this. This allows each stage to
1827 create mappings only for areas in the memory map that it needs.
1829 - A Secure Payload Dispatcher (OPTEED) for the OP-TEE Trusted OS has been
1830 added. Details of using it with TF-A can be found in :ref:`OP-TEE Dispatcher`
1832 Issues resolved since last release
1833 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1835 - The Juno port has been aligned with the FVP port as follows.
1837 - Support for reclaiming all BL1 RW memory and BL2 memory by overlaying
1838 the BL3-1/BL3-2 NOBITS sections on top of them has been added to the
1841 - The top 16MB of the 2GB DDR-DRAM memory at 0x80000000 is configured
1842 using the TZC-400 controller to be accessible only to the secure world.
1844 - The Arm GIC driver is used to configure the GIC-400 instead of using a
1845 GIC driver private to the Juno port.
1847 - PSCI ``CPU_SUSPEND`` calls that target a standby state are now supported.
1849 - The TZC-400 driver is used to configure the controller instead of direct
1850 accesses to the registers.
1852 - The Linux kernel version referred to in the user guide has DVFS and HMP
1855 - DS-5 v5.19 did not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in
1856 CADI server mode. This issue is not seen with DS-5 v5.20 and Version 6.2 of
1857 the Cortex-A57-A53 Base FVPs.
1862 - The Trusted Board Boot implementation is a prototype. There are issues with
1863 the modularity and scalability of the design. Support for a Trusted
1864 Watchdog, firmware update mechanism, recovery images and Trusted debug is
1865 absent. These issues will be addressed in future releases.
1867 - The FVP and Juno ports do not use the hash of the ROTPK stored in the
1868 Trusted Key Storage registers to verify the ROTPK in the
1869 ``plat_match_rotpk()`` function. This prevents the correct establishment of
1870 the Chain of Trust at the first step in the Trusted Board Boot process.
1872 - The version of the AEMv8 Base FVP used in this release resets the model
1873 instead of terminating its execution in response to a shutdown request using
1874 the PSCI ``SYSTEM_OFF`` API. This issue will be fixed in a future version of
1877 - GICv3 support is experimental. There are known issues with GICv3
1878 initialization in the TF-A.
1880 - While this version greatly reduces the on-chip RAM requirements, there are
1881 further RAM usage enhancements that could be made.
1883 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
1884 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
1886 - The Juno-specific firmware design documentation is incomplete.
1894 - It is now possible to map higher physical addresses using non-flat virtual
1895 to physical address mappings in the MMU setup.
1897 - Wider use is now made of the per-CPU data cache in BL3-1 to store:
1899 - Pointers to the non-secure and secure security state contexts.
1901 - A pointer to the CPU-specific operations.
1903 - A pointer to PSCI specific information (for example the current power
1906 - A crash reporting buffer.
1908 - The following RAM usage improvements result in a BL3-1 RAM usage reduction
1909 from 96KB to 56KB (for FVP with TSPD), and a total RAM usage reduction
1910 across all images from 208KB to 88KB, compared to the previous release.
1912 - Removed the separate ``early_exception`` vectors from BL3-1 (2KB code size
1915 - Removed NSRAM from the FVP memory map, allowing the removal of one
1916 (4KB) translation table.
1918 - Eliminated the internal ``psci_suspend_context`` array, saving 2KB.
1920 - Correctly dimensioned the PSCI ``aff_map_node`` array, saving 1.5KB in the
1923 - Removed calling CPU mpidr from the bakery lock API, saving 160 bytes.
1925 - Removed current CPU mpidr from PSCI common code, saving 160 bytes.
1927 - Inlined the mmio accessor functions, saving 360 bytes.
1929 - Fully reclaimed all BL1 RW memory and BL2 memory on the FVP port by
1930 overlaying the BL3-1/BL3-2 NOBITS sections on top of these at runtime.
1932 - Made storing the FP register context optional, saving 0.5KB per context
1933 (8KB on the FVP port, with TSPD enabled and running on 8 CPUs).
1935 - Implemented a leaner ``tf_printf()`` function, allowing the stack to be
1938 - Removed coherent stacks from the codebase. Stacks allocated in normal
1939 memory are now used before and after the MMU is enabled. This saves 768
1940 bytes per CPU in BL3-1.
1942 - Reworked the crash reporting in BL3-1 to use less stack.
1944 - Optimized the EL3 register state stored in the ``cpu_context`` structure
1945 so that registers that do not change during normal execution are
1946 re-initialized each time during cold/warm boot, rather than restored
1947 from memory. This saves about 1.2KB.
1949 - As a result of some of the above, reduced the runtime stack size in all
1950 BL images. For BL3-1, this saves 1KB per CPU.
1952 - PSCI SMC handler improvements to correctly handle calls from secure states
1955 - CPU contexts are now initialized from the ``entry_point_info``. BL3-1 fully
1956 determines the exception level to use for the non-trusted firmware (BL3-3)
1957 based on the SPSR value provided by the BL2 platform code (or otherwise
1958 provided to BL3-1). This allows platform code to directly run non-trusted
1959 firmware payloads at either EL2 or EL1 without requiring an EL2 stub or OS
1962 - Code refactoring improvements:
1964 - Refactored ``fvp_config`` into a common platform header.
1966 - Refactored the fvp gic code to be a generic driver that no longer has an
1967 explicit dependency on platform code.
1969 - Refactored the CCI-400 driver to not have dependency on platform code.
1971 - Simplified the IO driver so it's no longer necessary to call ``io_init()``
1972 and moved all the IO storage framework code to one place.
1974 - Simplified the interface the the TZC-400 driver.
1976 - Clarified the platform porting interface to the TSP.
1978 - Reworked the TSPD setup code to support the alternate BL3-2
1979 initialization flow where BL3-1 generic code hands control to BL3-2,
1980 rather than expecting the TSPD to hand control directly to BL3-2.
1982 - Considerable rework to PSCI generic code to support CPU specific
1985 - Improved console log output, by:
1987 - Adding the concept of debug log levels.
1989 - Rationalizing the existing debug messages and adding new ones.
1991 - Printing out the version of each BL stage at runtime.
1993 - Adding support for printing console output from assembler code,
1994 including when a crash occurs before the C runtime is initialized.
1996 - Moved up to the latest versions of the FVPs, toolchain, EDK2, kernel, Linaro
1997 file system and DS-5.
1999 - On the FVP port, made the use of the Trusted DRAM region optional at build
2000 time (off by default). Normal platforms will not have such a "ready-to-use"
2001 DRAM area so it is not a good example to use it.
2003 - Added support for PSCI ``SYSTEM_OFF`` and ``SYSTEM_RESET`` APIs.
2005 - Added support for CPU specific reset sequences, power down sequences and
2006 register dumping during crash reporting. The CPU specific reset sequences
2007 include support for errata workarounds.
2009 - Merged the Juno port into the master branch. Added support for CPU hotplug
2010 and CPU idle. Updated the user guide to describe how to build and run on the
2013 Issues resolved since last release
2014 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2016 - Removed the concept of top/bottom image loading. The image loader now
2017 automatically detects the position of the image inside the current memory
2018 layout and updates the layout to minimize fragmentation. This resolves the
2019 image loader limitations of previously releases. There are currently no
2020 plans to support dynamic image loading.
2022 - CPU idle now works on the publicized version of the Foundation FVP.
2024 - All known issues relating to the compiler version used have now been
2025 resolved. This TF-A version uses Linaro toolchain 14.07 (based on GCC 4.9).
2030 - GICv3 support is experimental. The Linux kernel patches to support this are
2031 not widely available. There are known issues with GICv3 initialization in
2034 - While this version greatly reduces the on-chip RAM requirements, there are
2035 further RAM usage enhancements that could be made.
2037 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
2038 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
2040 - The Juno-specific firmware design documentation is incomplete.
2042 - Some recent enhancements to the FVP port have not yet been translated into
2043 the Juno port. These will be tracked via the tf-issues project.
2045 - The Linux kernel version referred to in the user guide has DVFS and HMP
2046 support disabled due to some known instabilities at the time of this
2047 release. A future kernel version will re-enable these features.
2049 - DS-5 v5.19 does not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in
2050 CADI server mode. This is because the ``<SimName>`` reported by the FVP in
2051 this version has changed. For example, for the Cortex-A57x4-A53x4 Base FVP,
2052 the ``<SimName>`` reported by the FVP is ``FVP_Base_Cortex_A57x4_A53x4``, while
2053 DS-5 expects it to be ``FVP_Base_A57x4_A53x4``.
2055 The temporary fix to this problem is to change the name of the FVP in
2056 ``sw/debugger/configdb/Boards/ARM FVP/Base_A57x4_A53x4/cadi_config.xml``.
2057 Change the following line:
2061 <SimName>System Generator:FVP_Base_A57x4_A53x4</SimName>
2064 System Generator:FVP_Base_Cortex-A57x4_A53x4
2066 A similar change can be made to the other Cortex-A57-A53 Base FVP variants.
2074 - Makefile improvements:
2076 - Improved dependency checking when building.
2078 - Removed ``dump`` target (build now always produces dump files).
2080 - Enabled platform ports to optionally make use of parts of the Trusted
2081 Firmware (e.g. BL3-1 only), rather than being forced to use all parts.
2082 Also made the ``fip`` target optional.
2084 - Specified the full path to source files and removed use of the ``vpath``
2087 - Provided translation table library code for potential re-use by platforms
2088 other than the FVPs.
2090 - Moved architectural timer setup to platform-specific code.
2092 - Added standby state support to PSCI cpu_suspend implementation.
2094 - SRAM usage improvements:
2096 - Started using the ``-ffunction-sections``, ``-fdata-sections`` and
2097 ``--gc-sections`` compiler/linker options to remove unused code and data
2098 from the images. Previously, all common functions were being built into
2099 all binary images, whether or not they were actually used.
2101 - Placed all assembler functions in their own section to allow more unused
2102 functions to be removed from images.
2104 - Updated BL1 and BL2 to use a single coherent stack each, rather than one
2107 - Changed variables that were unnecessarily declared and initialized as
2108 non-const (i.e. in the .data section) so they are either uninitialized
2109 (zero init) or const.
2111 - Moved the Test Secure-EL1 Payload (BL3-2) to execute in Trusted SRAM by
2112 default. The option for it to run in Trusted DRAM remains.
2114 - Implemented a TrustZone Address Space Controller (TZC-400) driver. A
2115 default configuration is provided for the Base FVPs. This means the model
2116 parameter ``-C bp.secure_memory=1`` is now supported.
2118 - Started saving the PSCI cpu_suspend 'power_state' parameter prior to
2119 suspending a CPU. This allows platforms that implement multiple power-down
2120 states at the same affinity level to identify a specific state.
2122 - Refactored the entire codebase to reduce the amount of nesting in header
2123 files and to make the use of system/user includes more consistent. Also
2124 split platform.h to separate out the platform porting declarations from the
2125 required platform porting definitions and the definitions/declarations
2126 specific to the platform port.
2128 - Optimized the data cache clean/invalidate operations.
2130 - Improved the BL3-1 unhandled exception handling and reporting. Unhandled
2131 exceptions now result in a dump of registers to the console.
2133 - Major rework to the handover interface between BL stages, in particular the
2134 interface to BL3-1. The interface now conforms to a specification and is
2137 - Added support for optionally making the BL3-1 entrypoint a reset handler
2138 (instead of BL1). This allows platforms with an alternative image loading
2139 architecture to re-use BL3-1 with fewer modifications to generic code.
2141 - Reserved some DDR DRAM for secure use on FVP platforms to avoid future
2142 compatibility problems with non-secure software.
2144 - Added support for secure interrupts targeting the Secure-EL1 Payload (SP)
2145 (using GICv2 routing only). Demonstrated this working by adding an interrupt
2146 target and supporting test code to the TSP. Also demonstrated non-secure
2147 interrupt handling during TSP processing.
2149 Issues resolved since last release
2150 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2152 - Now support use of the model parameter ``-C bp.secure_memory=1`` in the Base
2153 FVPs (see **New features**).
2155 - Support for secure world interrupt handling now available (see **New
2158 - Made enough SRAM savings (see **New features**) to enable the Test Secure-EL1
2159 Payload (BL3-2) to execute in Trusted SRAM by default.
2161 - The tested filesystem used for this release (Linaro AArch64 OpenEmbedded
2162 14.04) now correctly reports progress in the console.
2164 - Improved the Makefile structure to make it easier to separate out parts of
2165 the TF-A for re-use in platform ports. Also, improved target dependency
2171 - GICv3 support is experimental. The Linux kernel patches to support this are
2172 not widely available. There are known issues with GICv3 initialization in
2175 - Dynamic image loading is not available yet. The current image loader
2176 implementation (used to load BL2 and all subsequent images) has some
2177 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead
2178 to loading errors, even if the images should theoretically fit in memory.
2180 - TF-A still uses too much on-chip Trusted SRAM. A number of RAM usage
2181 enhancements have been identified to rectify this situation.
2183 - CPU idle does not work on the advertised version of the Foundation FVP.
2184 Some FVP fixes are required that are not available externally at the time
2185 of writing. This can be worked around by disabling CPU idle in the Linux
2188 - Various bugs in TF-A, UEFI and the Linux kernel have been observed when
2189 using Linaro toolchain versions later than 13.11. Although most of these
2190 have been fixed, some remain at the time of writing. These mainly seem to
2191 relate to a subtle change in the way the compiler converts between 64-bit
2192 and 32-bit values (e.g. during casting operations), which reveals
2193 previously hidden bugs in client code.
2195 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
2196 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
2204 - Support for Foundation FVP Version 2.0 added.
2205 The documented UEFI configuration disables some devices that are unavailable
2206 in the Foundation FVP, including MMC and CLCD. The resultant UEFI binary can
2207 be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation
2211 The software will not work on Version 1.0 of the Foundation FVP.
2213 - Enabled third party contributions. Added a new contributing.md containing
2214 instructions for how to contribute and updated copyright text in all files
2215 to acknowledge contributors.
2217 - The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be
2218 used for entry into power down states with the following restrictions:
2220 - Entry into standby states is not supported.
2221 - The API is only supported on the AEMv8 and Cortex-A57-A53 Base FVPs.
2223 - The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to
2224 allow experimental use.
2226 - Required C library and runtime header files are now included locally in
2227 TF-A instead of depending on the toolchain standard include paths. The
2228 local implementation has been cleaned up and reduced in scope.
2230 - Added I/O abstraction framework, primarily to allow generic code to load
2231 images in a platform-independent way. The existing image loading code has
2232 been reworked to use the new framework. Semi-hosting and NOR flash I/O
2233 drivers are provided.
2235 - Introduced Firmware Image Package (FIP) handling code and tools. A FIP
2236 combines multiple firmware images with a Table of Contents (ToC) into a
2237 single binary image. The new FIP driver is another type of I/O driver. The
2238 Makefile builds a FIP by default and the FVP platform code expect to load a
2239 FIP from NOR flash, although some support for image loading using semi-
2240 hosting is retained.
2243 Building a FIP by default is a non-backwards-compatible change.
2246 Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into
2247 DRAM instead of expecting this to be pre-loaded at known location. This is
2248 also a non-backwards-compatible change.
2251 Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that
2252 it knows the new location to execute from and no longer needs to copy
2253 particular code modules to DRAM itself.
2255 - Reworked BL2 to BL3-1 handover interface. A new composite structure
2256 (bl31_args) holds the superset of information that needs to be passed from
2257 BL2 to BL3-1, including information on how handover execution control to
2258 BL3-2 (if present) and BL3-3 (non-trusted firmware).
2260 - Added library support for CPU context management, allowing the saving and
2263 - Shared system registers between Secure-EL1 and EL1.
2265 - Essential EL3 system registers.
2267 - Added a framework for implementing EL3 runtime services. Reworked the PSCI
2268 implementation to be one such runtime service.
2270 - Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3
2271 stack pointers for determining the type of exception, managing general
2272 purpose and system register context on exception entry/exit, and handling
2273 SMCs. SMCs are directed to the correct EL3 runtime service.
2275 - Added support for a Test Secure-EL1 Payload (TSP) and a corresponding
2276 Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD
2277 implements Secure Monitor functionality such as world switching and
2278 EL1 context management, and is responsible for communication with the TSP.
2281 The TSPD does not yet contain support for secure world interrupts.
2283 The TSP/TSPD is not built by default.
2285 Issues resolved since last release
2286 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2288 - Support has been added for switching context between secure and normal
2291 - PSCI API calls ``AFFINITY_INFO`` & ``PSCI_VERSION`` have now been tested (to
2294 - The TF-A build artifacts are now placed in the ``./build`` directory and
2295 sub-directories instead of being placed in the root of the project.
2297 - TF-A is now free from build warnings. Build warnings are now treated as
2300 - TF-A now provides C library support locally within the project to maintain
2301 compatibility between toolchains/systems.
2303 - The PSCI locking code has been reworked so it no longer takes locks in an
2306 - The RAM-disk method of loading a Linux file-system has been confirmed to
2307 work with the TF-A and Linux kernel version (based on version 3.13) used
2308 in this release, for both Foundation and Base FVPs.
2313 The following is a list of issues which are expected to be fixed in the future
2316 - The TrustZone Address Space Controller (TZC-400) is not being programmed
2317 yet. Use of model parameter ``-C bp.secure_memory=1`` is not supported.
2319 - No support yet for secure world interrupt handling.
2321 - GICv3 support is experimental. The Linux kernel patches to support this are
2322 not widely available. There are known issues with GICv3 initialization in
2325 - Dynamic image loading is not available yet. The current image loader
2326 implementation (used to load BL2 and all subsequent images) has some
2327 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead
2328 to loading errors, even if the images should theoretically fit in memory.
2330 - TF-A uses too much on-chip Trusted SRAM. Currently the Test Secure-EL1
2331 Payload (BL3-2) executes in Trusted DRAM since there is not enough SRAM.
2332 A number of RAM usage enhancements have been identified to rectify this
2335 - CPU idle does not work on the advertised version of the Foundation FVP.
2336 Some FVP fixes are required that are not available externally at the time
2339 - Various bugs in TF-A, UEFI and the Linux kernel have been observed when
2340 using Linaro toolchain versions later than 13.11. Although most of these
2341 have been fixed, some remain at the time of writing. These mainly seem to
2342 relate to a subtle change in the way the compiler converts between 64-bit
2343 and 32-bit values (e.g. during casting operations), which reveals
2344 previously hidden bugs in client code.
2346 - The tested filesystem used for this release (Linaro AArch64 OpenEmbedded
2347 14.01) does not report progress correctly in the console. It only seems to
2348 produce error output, not standard output. It otherwise appears to function
2349 correctly. Other filesystem versions on the same software stack do not
2350 exhibit the problem.
2352 - The Makefile structure doesn't make it easy to separate out parts of the
2353 TF-A for re-use in platform ports, for example if only BL3-1 is required in
2354 a platform port. Also, dependency checking in the Makefile is flawed.
2356 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
2357 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
2365 - First source release.
2367 - Code for the PSCI suspend feature is supplied, although this is not enabled
2368 by default since there are known issues (see below).
2370 Issues resolved since last release
2371 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2373 - The "psci" nodes in the FDTs provided in this release now fully comply
2374 with the recommendations made in the PSCI specification.
2379 The following is a list of issues which are expected to be fixed in the future
2382 - The TrustZone Address Space Controller (TZC-400) is not being programmed
2383 yet. Use of model parameter ``-C bp.secure_memory=1`` is not supported.
2385 - No support yet for secure world interrupt handling or for switching context
2386 between secure and normal worlds in EL3.
2388 - GICv3 support is experimental. The Linux kernel patches to support this are
2389 not widely available. There are known issues with GICv3 initialization in
2392 - Dynamic image loading is not available yet. The current image loader
2393 implementation (used to load BL2 and all subsequent images) has some
2394 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead
2395 to loading errors, even if the images should theoretically fit in memory.
2397 - Although support for PSCI ``CPU_SUSPEND`` is present, it is not yet stable
2400 - PSCI API calls ``AFFINITY_INFO`` & ``PSCI_VERSION`` are implemented but have
2403 - The TF-A make files result in all build artifacts being placed in the root
2404 of the project. These should be placed in appropriate sub-directories.
2406 - The compilation of TF-A is not free from compilation warnings. Some of these
2407 warnings have not been investigated yet so they could mask real bugs.
2409 - TF-A currently uses toolchain/system include files like stdio.h. It should
2410 provide versions of these within the project to maintain compatibility
2411 between toolchains/systems.
2413 - The PSCI code takes some locks in an incorrect sequence. This may cause
2414 problems with suspend and hotplug in certain conditions.
2416 - The Linux kernel used in this release is based on version 3.12-rc4. Using
2417 this kernel with the TF-A fails to start the file-system as a RAM-disk. It
2418 fails to execute user-space ``init`` from the RAM-disk. As an alternative,
2419 the VirtioBlock mechanism can be used to provide a file-system to the
2424 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
2426 .. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
2427 .. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501
2428 .. _PR#1002: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
2429 .. _mbed TLS releases: https://tls.mbed.org/tech-updates/releases