1 Change Log & Release Notes
2 ==========================
4 This document contains a summary of the new features, changes, fixes and known
5 issues in each release of Trusted Firmware-A.
14 - Enable Pointer Authentication (PAuth) support for Secure World
15 - Adds support for ARMv8.3-PAuth in BL1 SMC calls and
16 BL2U image for firmware updates.
18 - Enable Memory Tagging Extension (MTE) support in both secure and non-secure
20 - Adds support for the new Memory Tagging Extension arriving in
21 ARMv8.5. MTE support is now enabled by default on systems that
23 - To enable it at ELx for both the non-secure and the secure
24 world, the compiler flag ``CTX_INCLUDE_MTE_REGS`` includes register
25 saving and restoring when necessary in order to prevent information
26 leakage between the worlds.
28 - Add support for Branch Target Identification (BTI)
31 - Modify FVP makefile for CPUs that support both AArch64/32
33 - AArch32: Allow compiling with soft-float toolchain
35 - Makefile: Add default warning flags
37 - Add Makefile check for PAuth and AArch64
39 - Add compile-time errors for HW_ASSISTED_COHERENCY flag
41 - Apply compile-time check for AArch64-only CPUs
43 - build_macros: Add mechanism to prevent bin generation.
45 - Add support for default stack-protector flag
47 - spd: opteed: Enable NS_TIMER_SWITCH
49 - plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is set
51 - Add new build option to let each platform select which implementation of spinlocks
55 - DSU: Workaround for erratum 798953 and 936184
57 - Neoverse N1: Force cacheable atomic to near atomic
58 - Neoverse N1: Workaround for erratum 1073348, 1130799, 1165347, 1207823,
59 1220197, 1257314, 1262606, 1262888, 1275112, 1315703, 1542419
61 - Neoverse Zeus: Apply the MSR SSBS instruction
63 - cortex-a76AE: Support added for Cortex-A76AE CPU
64 - cortex-a76: Workaround for erratum 1257314, 1262606, 1262888, 1275112,
67 - cortex-a65/a65AE: Support added for Cortex-A65 and Cortex-A65AE CPUs
68 - cortex-a65: Enable AMU for Cortex-A65
70 - cortex-a55: Workaround for erratum 1221012
72 - cortex-a35: Workaround for erratum 855472
74 - cortex-a9: Workaround for erratum 794073
77 - console: Allow the console to register multiple times
79 - delay: Timeout detection support
81 - gicv3: Enabled multi-socket GIC redistributor frame discovery and migrated
82 ARM platforms to the new API
83 - Adds ``gicv3_rdistif_probe`` function that delegates the responsibility
84 of discovering the corresponding redistributor base frame to each CPU
87 - sbsa: Add SBSA watchdog driver
89 - st/stm32_hash: Add HASH driver
91 - ti/uart: Add an AArch32 variant
93 - Library at ROM (romlib)
94 - Introduce BTI support in Library at ROM (romlib)
96 - New Platforms Support
97 - amlogic: g12a: New platform support added for the S905X2 (G12A) platform
98 - amlogic: meson/gxl: New platform support added for Amlogic Meson
101 - arm/a5ds: New platform support added for A5 DesignStart
103 - arm/corstone: New platform support added for Corstone-700
105 - intel: New platform support added for Agilex
107 - mediatek: New platform support added for MediaTek mt8183
109 - qemu/qemu_sbsa: New platform support added for QEMU SBSA platform
111 - renesas/rcar_gen3: plat: New platform support added for D3
113 - rockchip: New platform support added for px30
114 - rockchip: New platform support added for rk3288
116 - rpi: New platform support added for Raspberry Pi 4
119 - arm/common: Introduce wrapper functions to setup secure watchdog
121 - arm/fvp: Add Delay Timer driver to BL1 and BL31 and option for defining
123 - arm/fvp: Add Linux DTS files for 32 bit threaded FVPs
125 - arm/n1sdp: Add code for DDR ECC enablement and BL33 copy to DDR, Initialise CNTFRQ
126 in Non Secure CNTBaseN
128 - arm/juno: Use shared mbedtls heap between BL1 and BL2 and add basic support for
131 - imx: Basic support for PicoPi iMX7D, rdc module init, caam module init,
132 aipstz init, IMX_SIP_GET_SOC_INFO, IMX_SIP_BUILDINFO added
134 - intel: Add ncore ccu driver
136 - mediatek/mt81*: Use new bl31_params_parse() helper
138 - nvidia: tegra: Add support for multi console interface
140 - qemu/qemu_sbsa: Adding memory mapping for both FLASH0/FLASH1
141 - qemu: Added gicv3 support, new console interface in AArch32, and sub-platforms
143 - renesas/rcar_gen3: plat: Add R-Car V3M support, new board revision for H3ULCB, DBSC4
144 setting before self-refresh mode
146 - socionext/uniphier: Support console based on multi-console
148 - st: stm32mp1: Add OP-TEE, Avenger96, watchdog, LpDDR3, authentication support
149 and general SYSCFG management
151 - ti/k3: common: Add support for J721E, Use coherent memory for shared data, Trap all
152 asynchronous bus errors to EL3
154 - xilinx/zynqmp: Add support for multi console interface, Initialize IPI table from
155 zynqmp_config_setup()
158 - Adding new optional PSCI hook ``pwr_domain_on_finish_late``
159 - This PSCI hook ``pwr_domain_on_finish_late`` is similar to
160 ``pwr_domain_on_finish`` but is guaranteed to be invoked when the
161 respective core and cluster are participating in coherency.
164 - Speculative Store Bypass Safe (SSBS): Further enhance protection against Spectre
165 variant 4 by disabling speculative loads/stores (SPSR.SSBS bit) by default.
167 - UBSAN support and handlers
168 - Adds support for the Undefined Behaviour sanitizer. There are two types of
169 support offered - minimalistic trapping support which essentially immediately
170 crashes on undefined behaviour and full support with full debug messages.
173 - cert_create: Add support for bigger RSA key sizes (3KB and 4KB),
174 previously the maximum size was 2KB.
176 - fiptool: Add support to build fiptool on Windows.
183 - Refactor ARMv8.3 Pointer Authentication support code
185 - backtrace: Strip PAC field when PAUTH is enabled
187 - Prettify crash reporting output on AArch64.
189 - Rework smc_unknown return code path in smc_handler
190 - Leverage the existing ``el3_exit()`` return routine for smc_unknown return
191 path rather than a custom set of instructions.
194 - Invalidate dcache build option for BL2 entry at EL3
196 - Add missing support for BL2_AT_EL3 in XIP memory
199 - Add helper to parse BL31 parameters (both versions)
201 - Factor out cross-BL API into export headers suitable for 3rd party code
203 - Introduce lightweight BL platform parameter library
206 - auth: Memory optimization for Chain of Trust (CoT) description
208 - bsec: Move bsec_mode_is_closed_device() service to platform
210 - cryptocell: Move Cryptocell specific API into driver
212 - gicv3: Prevent pending G1S interrupt from becoming G0 interrupt
214 - mbedtls: Remove weak heap implementation
216 - mmc: Increase delay between ACMD41 retries
217 - mmc: stm32_sdmmc2: Correctly manage block size
218 - mmc: stm32_sdmmc2: Manage max-frequency property from DT
220 - synopsys/emmc: Do not change FIFO TH as this breaks some platforms
221 - synopsys: Update synopsys drivers to not rely on undefined overflow behaviour
223 - ufs: Extend the delay after reset to wait for some slower chips
226 - amlogic/meson/gxl: Remove BL2 dependency from BL31
228 - arm/common: Shorten the Firmware Update (FWU) process
230 - arm/fvp: Remove GIC initialisation from secondary core cold boot
232 - arm/sgm: Temporarily disable shared Mbed TLS heap for SGM
234 - hisilicon: Update hisilicon drivers to not rely on undefined overflow behaviour
236 - imx: imx8: Replace PLAT_IMX8* with PLAT_imx8*, remove duplicated linker symbols and
237 deprecated code include, keep only IRQ 32 unmasked, enable all power domain by default
239 - marvell: Prevent SError accessing PCIe link, Switch to xlat_tables_v2, do not rely on
240 argument passed via smc, make sure that comphy init will use correct address
242 - mediatek: mt8173: Refactor RTC and PMIC drivers
243 - mediatek: mt8173: Apply MULTI_CONSOLE framework
245 - nvidia: Tegra: memctrl_v2: fix "overflow before widen" coverity issue
247 - qemu: Simplify the image size calculation, Move and generalise FDT PSCI fixup, move
248 gicv2 codes to separate file
250 - renesas/rcar_gen3: Convert to multi-console API, update QoS setting, Update IPL and
251 Secure Monitor Rev2.0.4, Change to restore timer counter value at resume, Update DDR
252 setting rev.0.35, qos: change subslot cycle, Change periodic write DQ training option.
254 - rockchip: Allow SOCs with undefined wfe check bits, Streamline and complete UARTn_BASE
255 macros, drop rockchip-specific imported linker symbols for bl31, Disable binary generation
256 for all SOCs, Allow console device to be set by DTB, Use new bl31_params_parse functions
258 - rpi/rpi3: Move shared rpi3 files into common directory
260 - socionext/uniphier: Set CONSOLE_FLAG_TRANSLATE_CRLF and clean up console driver
261 - socionext/uniphier: Replace DIV_ROUND_UP() with div_round_up() from utils_def.h
263 - st/stm32mp: Split stm32mp_io_setup function, move stm32_get_gpio_bank_clock() to private
264 file, correctly handle Clock Spreading Generator, move oscillator functions to generic file,
265 realign device tree files with internal devs, enable RTCAPB clock for dual-core chips, use a
266 common function to check spinlock is available, move check_header() to common code
268 - ti/k3: Enable SEPARATE_CODE_AND_RODATA by default, Remove shared RAM space,
269 Drop _ADDRESS from K3_USART_BASE to match other defines, Remove MSMC port
270 definitions, Allow USE_COHERENT_MEM for K3, Set L2 latency on A72 cores
273 - PSCI: Lookup list of parent nodes to lock only once
275 - Secure Partition Manager (SPM): SPCI Prototype
276 - Fix service UUID lookup
278 - Adjust size of virtual address space per partition
280 - Refactor xlat context creation
282 - Move shim layer to TTBR1_EL1
284 - Ignore empty regions in resource description
287 - Refactor SPSR initialisation code
289 - SMMUv3: Abort DMA transactions
290 - For security DMA should be blocked at the SMMU by default unless explicitly
291 enabled for a device. SMMU is disabled after reset with all streams bypassing
292 the SMMU, and abortion of all incoming transactions implements a default deny
294 - Moves ``bl1_platform_setup()`` function from arm_bl1_setup.c to FVP platforms'
295 fvp_bl1_setup.c and fvp_ve_bl1_setup.c files.
298 - cert_create: Remove RSA PKCS#1 v1.5 support
305 - Fix the CAS spinlock implementation by adding a missing DSB in ``spin_unlock()``
307 - AArch64: Fix SCTLR bit definitions
308 - Removes incorrect ``SCTLR_V_BIT`` definition and adds definitions for
309 ARMv8.3-Pauth `EnIB`, `EnDA` and `EnDB` bits.
311 - Fix restoration of PAuth context
312 - Replace call to ``pauth_context_save()`` with ``pauth_context_restore()`` in
313 case of unknown SMC call.
316 - Fix BL31 crash reporting on AArch64 only platforms
319 - Remove several warnings reported with W=2 and W=1
321 - Code Quality Issues
322 - SCTLR and ACTLR are 32-bit for AArch32 and 64-bit for AArch64
323 - Unify type of "cpu_idx" across PSCI module.
324 - Assert if power level value greater then PSCI_INVALID_PWR_LVL
325 - Unsigned long should not be used as per coding guidelines
326 - Reduce the number of memory leaks in cert_create
327 - Fix type of cot_desc_ptr
328 - Use explicit-width data types in AAPCS parameter structs
329 - Add python configuration for editorconfig
330 - BL1: Fix type consistency
332 - Enable -Wshift-overflow=2 to check for undefined shift behavior
333 - Updated upstream platforms to not rely on undefined overflow behaviour
335 - Coverity Quality Issues
336 - Remove GGC ignore -Warray-bounds
337 - Fix Coverity #261967, Infinite loop
338 - Fix Coverity #343017, Missing unlock
339 - Fix Coverity #343008, Side affect in assertion
340 - Fix Coverity #342970, Uninitialized scalar variable
343 - cortex-a12: Fix MIDR mask
346 - console: Remove Arm console unregister on suspend
348 - gicv3: Fix support for full SPI range
350 - scmi: Fix wrong payload length
353 - libc: Fix sparse warning for __assert()
355 - libc: Fix memchr implementation
358 - rpi: rpi3: Fix compilation error when stack protector is enabled
360 - socionext/uniphier: Fix compilation fail for SPM support build config
362 - st/stm32mp1: Fix TZC400 configuration against non-secure DDR
364 - ti/k3: common: Fix RO data area size calculation
367 - AArch32: Disable Secure Cycle Counter
368 - Changes the implementation for disabling Secure Cycle Counter.
369 For ARMv8.5 the counter gets disabled by setting ``SDCR.SCCD`` bit on
370 CPU cold/warm boot. For the earlier architectures PMCR register is
371 saved/restored on secure world entry/exit from/to Non-secure state,
372 and cycle counting gets disabled by setting PMCR.DP bit.
373 - AArch64: Disable Secure Cycle Counter
374 - For ARMv8.5 the counter gets disabled by setting ``MDCR_El3.SCCD`` bit on
375 CPU cold/warm boot. For the earlier architectures PMCR_EL0 register is
376 saved/restored on secure world entry/exit from/to Non-secure state,
377 and cycle counting gets disabled by setting PMCR_EL0.DP bit.
383 - Remove MULTI_CONSOLE_API flag and references to it
385 - Remove deprecated `plat_crash_console_*`
387 - Remove deprecated interfaces `get_afflvl_shift`, `mpidr_mask_lower_afflvls`, `eret`
389 - AARCH32/AARCH64 macros are now deprecated in favor of ``__aarch64__``
391 - ``__ASSEMBLY__`` macro is now deprecated in favor of ``__ASSEMBLER__``
394 - console: Removed legacy console API
395 - console: Remove deprecated finish_console_register
397 - tzc: Remove deprecated types `tzc_action_t` and `tzc_region_attributes_t`
399 - Secure Partition Manager (SPM):
400 - Prototype SPCI-based SPM (services/std_svc/spm) will be replaced with alternative
401 methods of secure partitioning support.
406 - Build System Issues
407 - dtb: DTB creation not supported when building on a Windows host.
409 This step in the build process is skipped when running on a Windows host. A
410 known issue from the 1.6 release.
413 - arm/juno: System suspend from Linux does not function as documented in the
416 Following the instructions provided in the user guide document does not
417 result in the platform entering system suspend state as expected. A message
418 relating to the hdlcd driver failing to suspend will be emitted on the
421 - mediatek/mt6795: This platform does not build in this release
430 - Support for ARMv8.3 pointer authentication in the normal and secure worlds
432 The use of pointer authentication in the normal world is enabled whenever
433 architectural support is available, without the need for additional build
436 Use of pointer authentication in the secure world remains an
437 experimental configuration at this time. Using both the ``ENABLE_PAUTH``
438 and ``CTX_INCLUDE_PAUTH_REGS`` build flags, pointer authentication can be
439 enabled in EL3 and S-EL1/0.
441 See the :ref:`Firmware Design` document for additional details on the use
442 of pointer authentication.
444 - Enable Data Independent Timing (DIT) in EL3, where supported
447 - Support for BL-specific build flags
449 - Support setting compiler target architecture based on ``ARM_ARCH_MINOR``
452 - New ``RECLAIM_INIT_CODE`` build flag:
454 A significant amount of the code used for the initialization of BL31 is
455 not needed again after boot time. In order to reduce the runtime memory
456 footprint, the memory used for this code can be reclaimed after
459 Certain boot-time functions were marked with the ``__init`` attribute to
460 enable this reclamation.
463 - cortex-a76: Workaround for erratum 1073348
464 - cortex-a76: Workaround for erratum 1220197
465 - cortex-a76: Workaround for erratum 1130799
467 - cortex-a75: Workaround for erratum 790748
468 - cortex-a75: Workaround for erratum 764081
470 - cortex-a73: Workaround for erratum 852427
471 - cortex-a73: Workaround for erratum 855423
473 - cortex-a57: Workaround for erratum 817169
474 - cortex-a57: Workaround for erratum 814670
476 - cortex-a55: Workaround for erratum 903758
477 - cortex-a55: Workaround for erratum 846532
478 - cortex-a55: Workaround for erratum 798797
479 - cortex-a55: Workaround for erratum 778703
480 - cortex-a55: Workaround for erratum 768277
482 - cortex-a53: Workaround for erratum 819472
483 - cortex-a53: Workaround for erratum 824069
484 - cortex-a53: Workaround for erratum 827319
486 - cortex-a17: Workaround for erratum 852423
487 - cortex-a17: Workaround for erratum 852421
489 - cortex-a15: Workaround for erratum 816470
490 - cortex-a15: Workaround for erratum 827671
493 - Exception Handling Framework documentation
495 - Library at ROM (romlib) documentation
497 - RAS framework documentation
499 - Coding Guidelines document
502 - ccn: Add API for setting and reading node registers
503 - Adds ``ccn_read_node_reg`` function
504 - Adds ``ccn_write_node_reg`` function
506 - partition: Support MBR partition entries
508 - scmi: Add ``plat_css_get_scmi_info`` function
510 Adds a new API ``plat_css_get_scmi_info`` which lets the platform
511 register a platform-specific instance of ``scmi_channel_plat_info_t`` and
512 remove the default values
514 - tzc380: Add TZC-380 TrustZone Controller driver
516 - tzc-dmc620: Add driver to manage the TrustZone Controller within the
517 DMC-620 Dynamic Memory Controller
519 - Library at ROM (romlib)
520 - Add platform-specific jump table list
522 - Allow patching of romlib functions
524 This change allows patching of functions in the romlib. This can be done by
525 adding "patch" at the end of the jump table entry for the function that
526 needs to be patched in the file jmptbl.i.
529 - Support non-LPAE-enabled MMU tables in AArch32
531 - mmio: Add ``mmio_clrsetbits_16`` function
532 - 16-bit variant of ``mmio_clrsetbits``
534 - object_pool: Add Object Pool Allocator
535 - Manages object allocation using a fixed-size static array
536 - Adds ``pool_alloc`` and ``pool_alloc_n`` functions
537 - Does not provide any functions to free allocated objects (by design)
539 - libc: Added ``strlcpy`` function
541 - libc: Import ``strrchr`` function from FreeBSD
543 - xlat_tables: Add support for ARMv8.4-TTST
545 - xlat_tables: Support mapping regions without an explicitly specified VA
548 - Added softudiv macro to support software division
550 - Memory Partitioning And Monitoring (MPAM)
551 - Enabled MPAM EL2 traps (``MPAMHCR_EL2`` and ``MPAM_EL2``)
554 - amlogic: Add support for Meson S905 (GXBB)
556 - arm/fvp_ve: Add support for FVP Versatile Express platform
558 - arm/n1sdp: Add support for Neoverse N1 System Development platform
560 - arm/rde1edge: Add support for Neoverse E1 platform
562 - arm/rdn1edge: Add support for Neoverse N1 platform
564 - arm: Add support for booting directly to Linux without an intermediate
567 - arm/juno: Enable new CPU errata workarounds for A53 and A57
569 - arm/juno: Add romlib support
571 Building a combined BL1 and ROMLIB binary file with the correct page
572 alignment is now supported on the Juno platform. When ``USE_ROMLIB`` is set
573 for Juno, it generates the combined file ``bl1_romlib.bin`` which needs to
574 be used instead of bl1.bin.
576 - intel/stratix: Add support for Intel Stratix 10 SoC FPGA platform
578 - marvell: Add support for Armada-37xx SoC platform
580 - nxp: Add support for i.MX8M and i.MX7 Warp7 platforms
582 - renesas: Add support for R-Car Gen3 platform
584 - xilinx: Add support for Versal ACAP platforms
586 - Position-Independent Executable (PIE)
588 PIE support has initially been added to BL31. The ``ENABLE_PIE`` build flag is
589 used to enable or disable this functionality as required.
591 - Secure Partition Manager
592 - New SPM implementation based on SPCI Alpha 1 draft specification
594 A new version of SPM has been implemented, based on the SPCI (Secure
595 Partition Client Interface) and SPRT (Secure Partition Runtime) draft
598 The new implementation is a prototype that is expected to undergo intensive
599 rework as the specifications change. It has basic support for multiple
600 Secure Partitions and Resource Descriptions.
602 The older version of SPM, based on MM (ARM Management Mode Interface
603 Specification), is still present in the codebase. A new build flag,
604 ``SPM_MM`` has been added to allow selection of the desired implementation.
605 This flag defaults to 1, selecting the MM-based implementation.
608 - Spectre Variant-1 mitigations (``CVE-2017-5753``)
610 - Use Speculation Store Bypass Safe (SSBS) functionality where available
612 Provides mitigation against ``CVE-2018-19440`` (Not saving x0 to x3
613 registers can leak information from one Normal World SMC client to another)
620 - Warning levels are now selectable with ``W=<1,2,3>``
622 - Removed unneeded include paths in PLAT_INCLUDES
624 - "Warnings as errors" (Werror) can be disabled using ``E=0``
626 - Support totally quiet output with ``-s`` flag
628 - Support passing options to checkpatch using ``CHECKPATCH_OPTS=<opts>``
630 - Invoke host compiler with ``HOSTCC / HOSTCCFLAGS`` instead of ``CC / CFLAGS``
632 - Make device tree pre-processing similar to U-boot/Linux by:
633 - Creating separate ``CPPFLAGS`` for DT preprocessing so that compiler
634 options specific to it can be accommodated.
635 - Replacing ``CPP`` with ``PP`` for DT pre-processing
638 - Errata report function definition is now mandatory for CPU support files
640 CPU operation files must now define a ``<name>_errata_report`` function to
641 print errata status. This is no longer a weak reference.
644 - Migrated some content from GitHub wiki to ``docs/`` directory
646 - Security advisories now have CVE links
648 - Updated copyright guidelines
651 - console: The ``MULTI_CONSOLE_API`` framework has been rewritten in C
653 - console: Ported multi-console driver to AArch32
655 - gic: Remove 'lowest priority' constants
657 Removed ``GIC_LOWEST_SEC_PRIORITY`` and ``GIC_LOWEST_NS_PRIORITY``.
658 Platforms should define these if required, or instead determine the correct
659 priority values at runtime.
661 - delay_timer: Check that the Generic Timer extension is present
663 - mmc: Increase command reply timeout to 10 milliseconds
665 - mmc: Poll eMMC device status to ensure ``EXT_CSD`` command completion
667 - mmc: Correctly check return code from ``mmc_fill_device_info``
671 - libfdt: Upgraded from 1.4.2 to 1.4.6-9
673 - mbed TLS: Upgraded from 2.12 to 2.16
675 This change incorporates fixes for security issues that should be reviewed
676 to determine if they are relevant for software implementations using
677 Trusted Firmware-A. See the `mbed TLS releases`_ page for details on
678 changes from the 2.12 to the 2.16 release.
681 - compiler-rt: Updated ``lshrdi3.c`` and ``int_lib.h`` with changes from
682 LLVM master branch (r345645)
684 - cpu: Updated macro that checks need for ``CVE-2017-5715`` mitigation
686 - libc: Made setjmp and longjmp C standard compliant
688 - libc: Allowed overriding the default libc (use ``OVERRIDE_LIBC``)
690 - libc: Moved setjmp and longjmp to the ``libc/`` directory
693 - Removed Mbed TLS dependency from plat_bl_common.c
695 - arm: Removed unused ``ARM_MAP_BL_ROMLIB`` macro
697 - arm: Removed ``ARM_BOARD_OPTIMISE_MEM`` feature and build flag
699 - arm: Moved several components into ``drivers/`` directory
701 This affects the SDS, SCP, SCPI, MHU and SCMI components
703 - arm/juno: Increased maximum BL2 image size to ``0xF000``
705 This change was required to accommodate a larger ``libfdt`` library
708 - Optimized bakery locks when hardware-assisted coherency is enabled using the
709 ``HW_ASSISTED_COHERENCY`` build flag
712 - Added support for unconditionally resuming secure world execution after
713 |SDEI| event processing completes
715 |SDEI| interrupts, although targeting EL3, occur on behalf of the non-secure
716 world, and may have higher priority than secure world
717 interrupts. Therefore they might preempt secure execution and yield
718 execution to the non-secure |SDEI| handler. Upon completion of |SDEI| event
719 handling, resume secure execution if it was preempted.
721 - Translation Tables (XLAT)
722 - Dynamically detect need for ``Common not Private (TTBRn_ELx.CnP)`` bit
724 Properly handle the case where ``ARMv8.2-TTCNP`` is implemented in a CPU
725 that does not implement all mandatory v8.2 features (and so must claim to
726 implement a lower architecture version).
733 - Incorrect check for SSBS feature detection
735 - Unintentional register clobber in AArch32 reset_handler function
738 - Dependency issue during DTB image build
740 - Incorrect variable expansion in Arm platform makefiles
742 - Building on Windows with verbose mode (``V=1``) enabled is broken
744 - AArch32 compilation flags is missing ``$(march32-directive)``
747 - bl2: ``uintptr_t is not defined`` error when ``BL2_IN_XIP_MEM`` is defined
749 - bl2: Missing prototype warning in ``bl2_arch_setup``
751 - bl31: Omission of Global Offset Table (GOT) section
753 - Code Quality Issues
754 - Multiple MISRA compliance issues
756 - Potential NULL pointer dereference (Coverity-detected)
759 - mmc: Local declaration of ``scr`` variable causes a cache issue when
760 invalidating after the read DMA transfer completes
762 - mmc: ``ACMD41`` does not send voltage information during initialization,
763 resulting in the command being treated as a query. This prevents the
764 command from initializing the controller.
766 - mmc: When checking device state using ``mmc_device_state()`` there are no
767 retries attempted in the event of an error
769 - ccn: Incorrect Region ID calculation for RN-I nodes
771 - console: ``Fix MULTI_CONSOLE_API`` when used as a crash console
773 - partition: Improper NULL checking in gpt.c
775 - partition: Compilation failure in ``VERBOSE`` mode (``V=1``)
778 - common: Incorrect check for Address Authentication support
780 - xlat: Fix XLAT_V1 / XLAT_V2 incompatibility
782 The file ``arm_xlat_tables.h`` has been renamed to ``xlat_tables_compat.h``
783 and has been moved to a common folder. This header can be used to guarantee
784 compatibility, as it includes the correct header based on
785 ``XLAT_TABLES_LIB_V2``.
787 - xlat: armclang unused-function warning on ``xlat_clean_dcache_range``
789 - xlat: Invalid ``mm_cursor`` checks in ``mmap_add`` and ``mmap_add_ctx``
791 - sdei: Missing ``context.h`` header
794 - common: Missing prototype warning for ``plat_log_get_prefix``
796 - arm: Insufficient maximum BL33 image size
798 - arm: Potential memory corruption during BL2-BL31 transition
800 On Arm platforms, the BL2 memory can be overlaid by BL31/BL32. The memory
801 descriptors describing the list of executable images are created in BL2
802 R/W memory, which could be possibly corrupted later on by BL31/BL32 due
803 to overlay. This patch creates a reserved location in SRAM for these
804 descriptors and are copied over by BL2 before handing over to next BL
807 - juno: Invalid behaviour when ``CSS_USE_SCMI_SDS_DRIVER`` is not set
809 In ``juno_pm.c`` the ``css_scmi_override_pm_ops`` function was used
810 regardless of whether the build flag was set. The original behaviour has
811 been restored in the case where the build flag is not set.
814 - fiptool: Incorrect UUID parsing of blob parameters
816 - doimage: Incorrect object rules in Makefile
823 - ``plat_crash_console_init`` function
825 - ``plat_crash_console_putc`` function
827 - ``plat_crash_console_flush`` function
829 - ``finish_console_register`` macro
831 - AArch64-specific Code
832 - helpers: ``get_afflvl_shift``
834 - helpers: ``mpidr_mask_lower_afflvls``
838 - Secure Partition Manager (SPM)
839 - Boot-info structure
845 - Build System Issues
846 - dtb: DTB creation not supported when building on a Windows host.
848 This step in the build process is skipped when running on a Windows host. A
849 known issue from the 1.6 release.
852 - arm/juno: System suspend from Linux does not function as documented in the
855 Following the instructions provided in the user guide document does not
856 result in the platform entering system suspend state as expected. A message
857 relating to the hdlcd driver failing to suspend will be emitted on the
860 - arm/juno: The firmware update use-cases do not work with motherboard
861 firmware version < v1.5.0 (the reset reason is not preserved). The Linaro
862 18.04 release has MB v1.4.9. The MB v1.5.0 is available in Linaro 18.10
865 - mediatek/mt6795: This platform does not build in this release
873 - Removal of a number of deprecated APIs
875 - A new Platform Compatibility Policy document has been created which
876 references a wiki page that maintains a listing of deprecated
877 interfaces and the release after which they will be removed.
879 - All deprecated interfaces except the MULTI_CONSOLE_API have been removed
882 - Various Arm and partner platforms have been updated to remove the use of
883 removed APIs in this release.
885 - This release is otherwise unchanged from 1.6 release
887 Issues resolved since last release
888 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
890 - No issues known at 1.6 release resolved in 2.0 release
895 - DTB creation not supported when building on a Windows host. This step in the
896 build process is skipped when running on a Windows host. Known issue from
899 - As a result of removal of deprecated interfaces the Nvidia Tegra, Marvell
900 Armada 8K and MediaTek MT6795 platforms do not build in this release.
901 Also MediaTek MT8173, NXP QorIQ LS1043A, NXP i.MX8QX, NXP i.MX8QMa,
902 Rockchip RK3328, Rockchip RK3368 and Rockchip RK3399 platforms have not been
903 confirmed to be working after the removal of the deprecated interfaces
904 although they do build.
912 - Addressing Speculation Security Vulnerabilities
914 - Implement static workaround for CVE-2018-3639 for AArch32 and AArch64
916 - Add support for dynamic mitigation for CVE-2018-3639
918 - Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
920 - Ensure |SDEI| handler executes with CVE-2018-3639 mitigation enabled
922 - Introduce RAS handling on AArch64
924 - Some RAS extensions are mandatory for Armv8.2 CPUs, with others
925 mandatory for Armv8.4 CPUs however, all extensions are also optional
926 extensions to the base Armv8.0 architecture.
928 - The Armv8 RAS Extensions introduced Standard Error Records which are a
929 set of standard registers to configure RAS node policy and allow RAS
930 Nodes to record and expose error information for error handling agents.
932 - Capabilities are provided to support RAS Node enumeration and iteration
933 along with individual interrupt registrations and fault injections
936 - Introduce handlers for Uncontainable errors, Double Faults and EL3
939 - Enable Memory Partitioning And Monitoring (MPAM) for lower EL's
941 - Memory Partitioning And Monitoring is an Armv8.4 feature that enables
942 various memory system components and resources to define partitions.
943 Software running at various ELs can then assign themselves to the
944 desired partition to control their performance aspects.
946 - When ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows
947 lower ELs to access their own MPAM registers without trapping to EL3.
948 This patch however, doesn't make use of partitioning in EL3; platform
949 initialisation code should configure and use partitions in EL3 if
952 - Introduce ROM Lib Feature
954 - Support combining several libraries into a self-called "romlib" image,
955 that may be shared across images to reduce memory footprint. The romlib
956 image is stored in ROM but is accessed through a jump-table that may be
957 stored in read-write memory, allowing for the library code to be patched.
959 - Introduce Backtrace Feature
961 - This function displays the backtrace, the current EL and security state
962 to allow a post-processing tool to choose the right binary to interpret
965 - Print backtrace in assert() and panic() to the console.
967 - Code hygiene changes and alignment with MISRA C-2012 guideline with fixes
968 addressing issues complying to the following rules:
970 - MISRA rules 4.9, 5.1, 5.3, 5.7, 8.2-8.5, 8.8, 8.13, 9.3, 10.1,
971 10.3-10.4, 10.8, 11.3, 11.6, 12.1, 14.4, 15.7, 16.1-16.7, 17.7-17.8,
972 20.7, 20.10, 20.12, 21.1, 21.15, 22.7
974 - Clean up the usage of void pointers to access symbols
976 - Increase usage of static qualifier to locally used functions and data
978 - Migrated to use of u_register_t for register read/write to better
979 match AArch32 and AArch64 type sizes
981 - Use int-ll64 for both AArch32 and AArch64 to assist in consistent
982 format strings between architectures
984 - Clean up TF-A libc by removing non arm copyrighted implementations
985 and replacing them with modified FreeBSD and SCC implementations
987 - Various changes to support Clang linker and assembler
989 - The clang assembler/preprocessor is used when Clang is selected. However,
990 the clang linker is not used because it is unable to link TF-A objects
991 due to immaturity of clang linker functionality at this time.
993 - Refactor support APIs into Libraries
995 - Evolve libfdt, mbed TLS library and standard C library sources as
996 proper libraries that TF-A may be linked against.
1000 - Add CPU support for Cortex-Ares and Cortex-A76
1002 - Add AMU support for Cortex-Ares
1004 - Add initial CPU support for Cortex-Deimos
1006 - Add initial CPU support for Cortex-Helios
1008 - Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
1010 - Implement Cortex-Ares erratum 1043202 workaround
1012 - Implement DSU erratum 936184 workaround
1014 - Check presence of fix for errata 843419 in Cortex-A53
1016 - Check presence of fix for errata 835769 in Cortex-A53
1018 - Translation Tables Enhancements
1020 - The xlat v2 library has been refactored in order to be reused by
1021 different TF components at different EL's including the addition of EL2.
1022 Some refactoring to make the code more generic and less specific to TF,
1023 in order to reuse the library outside of this project.
1027 - General cleanups and refactoring to pave the way to multiple partitions
1032 - Allow platforms to define explicit events
1034 - Determine client EL from NS context's SCR_EL3
1036 - Make dispatches synchronous
1038 - Introduce jump primitives for BL31
1040 - Mask events after CPU wakeup in |SDEI| dispatcher to conform to the
1043 - Misc TF-A Core Common Code Enhancements
1045 - Add support for eXecute In Place (XIP) memory in BL2
1047 - Add support for the SMC Calling Convention 2.0
1049 - Introduce External Abort handling on AArch64
1050 External Abort routed to EL3 was reported as an unhandled exception
1051 and caused a panic. This change enables Trusted Firmware-A to handle
1052 External Aborts routed to EL3.
1054 - Save value of ACTLR_EL1 implementation-defined register in the CPU
1055 context structure rather than forcing it to 0.
1057 - Introduce ARM_LINUX_KERNEL_AS_BL33 build option, which allows BL31 to
1058 directly jump to a Linux kernel. This makes for a quicker and simpler
1059 boot flow, which might be useful in some test environments.
1061 - Add dynamic configurations for BL31, BL32 and BL33 enabling support for
1062 Chain of Trust (COT).
1064 - Make TF UUID RFC 4122 compliant
1066 - New Platform Support
1072 - Allwinner sun50i_64
1074 - Allwinner sun50i_h6
1082 - NXP i.MX7Solo WaRP7
1086 - Socionext Synquacer SC2A11
1090 - STMicroelectronics STM32MP1
1092 - Misc Generic Platform Common Code Enhancements
1094 - Add MMC framework that supports both eMMC and SD card devices
1096 - Misc Arm Platform Common Code Enhancements
1098 - Demonstrate PSCI MEM_PROTECT from el3_runtime
1100 - Provide RAS support
1102 - Migrate AArch64 port to the multi console driver. The old API is
1103 deprecated and will eventually be removed.
1105 - Move BL31 below BL2 to enable BL2 overlay resulting in changes in the
1106 layout of BL images in memory to enable more efficient use of available
1109 - Add cpp build processing for dtb that allows processing device tree
1110 with external includes.
1112 - Extend FIP io driver to support multiple FIP devices
1114 - Add support for SCMI AP core configuration protocol v1.0
1116 - Use SCMI AP core protocol to set the warm boot entrypoint
1118 - Add support to Mbed TLS drivers for shared heap among different
1119 BL images to help optimise memory usage
1121 - Enable non-secure access to UART1 through a build option to support
1122 a serial debug port for debugger connection
1124 - Enhancements for Arm Juno Platform
1126 - Add support for TrustZone Media Protection 1 (TZMP1)
1128 - Enhancements for Arm FVP Platform
1130 - Dynamic_config: remove the FVP dtb files
1132 - Set DYNAMIC_WORKAROUND_CVE_2018_3639=1 on FVP by default
1134 - Set the ability to dynamically disable Trusted Boot Board
1135 authentication to be off by default with DYN_DISABLE_AUTH
1137 - Add librom enhancement support in FVP
1139 - Support shared Mbed TLS heap between BL1 and BL2 that allow a
1140 reduction in BL2 size for FVP
1142 - Enhancements for Arm SGI/SGM Platform
1144 - Enable ARM_PLAT_MT flag for SGI-575
1146 - Add dts files to enable support for dynamic config
1150 - Support shared Mbed TLS heap for SGI and SGM between BL1 and BL2
1152 - Enhancements for Non Arm Platforms
1154 - Raspberry Pi Platform
1162 - Rockchip rk3399 Platform
1166 - Socionext Platforms
1168 - Allwinner Platforms
1172 - NVIDIA Tegra Platform
1176 - STMicroelectronics STM32MP1 Platform
1178 Issues resolved since last release
1179 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1181 - No issues known at 1.5 release resolved in 1.6 release
1186 - DTB creation not supported when building on a Windows host. This step in the
1187 build process is skipped when running on a Windows host. Known issue from
1196 - Added new firmware support to enable RAS (Reliability, Availability, and
1197 Serviceability) functionality.
1199 - Secure Partition Manager (SPM): A Secure Partition is a software execution
1200 environment instantiated in S-EL0 that can be used to implement simple
1201 management and security services. The SPM is the firmware component that
1202 is responsible for managing a Secure Partition.
1204 - SDEI dispatcher: Support for interrupt-based |SDEI| events and all
1205 interfaces as defined by the |SDEI| specification v1.0, see
1206 `SDEI Specification`_
1208 - Exception Handling Framework (EHF): Framework that allows dispatching of
1209 EL3 interrupts to their registered handlers which are registered based on
1210 their priorities. Facilitates firmware-first error handling policy where
1211 asynchronous exceptions may be routed to EL3.
1213 Integrated the TSPD with EHF.
1215 - Updated PSCI support:
1217 - Implemented PSCI v1.1 optional features `MEM_PROTECT` and `SYSTEM_RESET2`.
1218 The supported PSCI version was updated to v1.1.
1220 - Improved PSCI STAT timestamp collection, including moving accounting for
1221 retention states to be inside the locks and fixing handling of wrap-around
1222 when calculating residency in AArch32 execution state.
1224 - Added optional handler for early suspend that executes when suspending to
1225 a power-down state and with data caches enabled.
1227 This may provide a performance improvement on platforms where it is safe
1228 to perform some or all of the platform actions from `pwr_domain_suspend`
1229 with the data caches enabled.
1231 - Enabled build option, BL2_AT_EL3, for BL2 to allow execution at EL3 without
1232 any dependency on TF BL1.
1234 This allows platforms which already have a non-TF Boot ROM to directly load
1235 and execute BL2 and subsequent BL stages without need for BL1. This was not
1236 previously possible because BL2 executes at S-EL1 and cannot jump straight to
1239 - Implemented support for SMCCC v1.1, including `SMCCC_VERSION` and
1240 `SMCCC_ARCH_FEATURES`.
1242 Additionally, added support for `SMCCC_VERSION` in PSCI features to enable
1243 discovery of the SMCCC version via PSCI feature call.
1245 - Added Dynamic Configuration framework which enables each of the boot loader
1246 stages to be dynamically configured at runtime if required by the platform.
1247 The boot loader stage may optionally specify a firmware configuration file
1248 and/or hardware configuration file that can then be shared with the next boot
1251 Introduced a new BL handover interface that essentially allows passing of 4
1252 arguments between the different BL stages.
1254 Updated cert_create and fip_tool to support the dynamic configuration files.
1255 The COT also updated to support these new files.
1257 - Code hygiene changes and alignment with MISRA guideline:
1259 - Fix use of undefined macros.
1261 - Achieved compliance with Mandatory MISRA coding rules.
1263 - Achieved compliance for following Required MISRA rules for the default
1264 build configurations on FVP and Juno platforms : 7.3, 8.3, 8.4, 8.5 and
1267 - Added support for Armv8.2-A architectural features:
1269 - Updated translation table set-up to set the CnP (Common not Private) bit
1270 for secure page tables so that multiple PEs in the same Inner Shareable
1271 domain can use the same translation table entries for a given stage of
1272 translation in a particular translation regime.
1274 - Extended the supported values of ID_AA64MMFR0_EL1.PARange to include the
1275 52-bit Physical Address range.
1277 - Added support for the Scalable Vector Extension to allow Normal world
1278 software to access SVE functionality but disable access to SVE, SIMD and
1279 floating point functionality from the Secure world in order to prevent
1280 corruption of the Z-registers.
1282 - Added support for Armv8.4-A architectural feature Activity Monitor Unit (AMU)
1285 In addition to the v8.4 architectural extension, AMU support on Cortex-A75
1288 - Enhanced OP-TEE support to enable use of pageable OP-TEE image. The Arm
1289 standard platforms are updated to load up to 3 images for OP-TEE; header,
1290 pager image and paged image.
1292 The chain of trust is extended to support the additional images.
1294 - Enhancements to the translation table library:
1296 - Introduced APIs to get and set the memory attributes of a region.
1298 - Added support to manage both privilege levels in translation regimes that
1299 describe translations for 2 Exception levels, specifically the EL1&0
1300 translation regime, and extended the memory map region attributes to
1301 include specifying Non-privileged access.
1303 - Added support to specify the granularity of the mappings of each region,
1304 for instance a 2MB region can be specified to be mapped with 4KB page
1305 tables instead of a 2MB block.
1307 - Disabled the higher VA range to avoid unpredictable behaviour if there is
1308 an attempt to access addresses in the higher VA range.
1310 - Added helpers for Device and Normal memory MAIR encodings that align with
1311 the Arm Architecture Reference Manual for Armv8-A (Arm DDI0487B.b).
1313 - Code hygiene including fixing type length and signedness of constants,
1314 refactoring of function to enable the MMU, removing all instances where
1315 the virtual address space is hardcoded and added comments that document
1316 alignment needed between memory attributes and attributes specified in
1319 - Updated GIC support:
1321 - Introduce new APIs for GICv2 and GICv3 that provide the capability to
1322 specify interrupt properties rather than list of interrupt numbers alone.
1323 The Arm platforms and other upstream platforms are migrated to use
1324 interrupt properties.
1326 - Added helpers to save / restore the GICv3 context, specifically the
1327 Distributor and Redistributor contexts and architectural parts of the ITS
1328 power management. The Distributor and Redistributor helpers also support
1329 the implementation-defined part of GIC-500 and GIC-600.
1331 Updated the Arm FVP platform to save / restore the GICv3 context on system
1332 suspend / resume as an example of how to use the helpers.
1334 Introduced a new TZC secured DDR carve-out for use by Arm platforms for
1335 storing EL3 runtime data such as the GICv3 register context.
1337 - Added support for Armv7-A architecture via build option ARM_ARCH_MAJOR=7.
1338 This includes following features:
1340 - Updates GICv2 driver to manage GICv1 with security extensions.
1342 - Software implementation for 32bit division.
1344 - Enabled use of generic timer for platforms that do not set
1347 - Support for Armv7-A Virtualization extensions [DDI0406C_C].
1349 - Support for both Armv7-A platforms that only have 32-bit addressing and
1350 Armv7-A platforms that support large page addressing.
1352 - Included support for following Armv7 CPUs: Cortex-A12, Cortex-A17,
1353 Cortex-A7, Cortex-A5, Cortex-A9, Cortex-A15.
1355 - Added support in QEMU for Armv7-A/Cortex-A15.
1357 - Enhancements to Firmware Update feature:
1359 - Updated the FWU documentation to describe the additional images needed for
1360 Firmware update, and how they are used for both the Juno platform and the
1363 - Enhancements to Trusted Board Boot feature:
1365 - Added support to cert_create tool for RSA PKCS1# v1.5 and SHA384, SHA512
1368 - For Arm platforms added support to use ECDSA keys.
1370 - Enhanced the mbed TLS wrapper layer to include support for both RSA and
1371 ECDSA to enable runtime selection between RSA and ECDSA keys.
1373 - Added support for secure interrupt handling in AArch32 sp_min, hardcoded to
1376 - Added support to allow a platform to load images from multiple boot sources,
1377 for example from a second flash drive.
1379 - Added a logging framework that allows platforms to reduce the logging level
1380 at runtime and additionally the prefix string can be defined by the platform.
1382 - Further improvements to register initialisation:
1384 - Control register PMCR_EL0 / PMCR is set to prohibit cycle counting in the
1385 secure world. This register is added to the list of registers that are
1386 saved and restored during world switch.
1388 - When EL3 is running in AArch32 execution state, the Non-secure version of
1389 SCTLR is explicitly initialised during the warmboot flow rather than
1390 relying on the hardware to set the correct reset values.
1392 - Enhanced support for Arm platforms:
1394 - Introduced driver for Shared-Data-Structure (SDS) framework which is used
1395 for communication between SCP and the AP CPU, replacing Boot-Over_MHU
1398 The Juno platform is migrated to use SDS with the SCMI support added in
1399 v1.3 and is set as default.
1401 The driver can be found in the plat/arm/css/drivers folder.
1403 - Improved memory usage by only mapping TSP memory region when the TSPD has
1404 been included in the build. This reduces the memory footprint and avoids
1405 unnecessary memory being mapped.
1407 - Updated support for multi-threading CPUs for FVP platforms - always check
1408 the MT field in MPDIR and access the bit fields accordingly.
1410 - Support building for platforms that model DynamIQ configuration by
1411 implementing all CPUs in a single cluster.
1413 - Improved nor flash driver, for instance clearing status registers before
1414 sending commands. Driver can be found plat/arm/board/common folder.
1416 - Enhancements to QEMU platform:
1418 - Added support for TBB.
1420 - Added support for using OP-TEE pageable image.
1422 - Added support for LOAD_IMAGE_V2.
1424 - Migrated to use translation table library v2 by default.
1426 - Added support for SEPARATE_CODE_AND_RODATA.
1428 - Applied workarounds CVE-2017-5715 on Arm Cortex-A57, -A72, -A73 and -A75, and
1429 for Armv7-A CPUs Cortex-A9, -A15 and -A17.
1431 - Applied errata workaround for Arm Cortex-A57: 859972.
1433 - Applied errata workaround for Arm Cortex-A72: 859971.
1435 - Added support for Poplar 96Board platform.
1437 - Added support for Raspberry Pi 3 platform.
1439 - Added Call Frame Information (CFI) assembler directives to the vector entries
1440 which enables debuggers to display the backtrace of functions that triggered
1441 a synchronous abort.
1443 - Added ability to build dtb.
1445 - Added support for pre-tool (cert_create and fiptool) image processing
1446 enabling compression of the image files before processing by cert_create and
1449 This can reduce fip size and may also speed up loading of images. The image
1450 verification will also get faster because certificates are generated based on
1453 Imported zlib 1.2.11 to implement gunzip() for data compression.
1455 - Enhancements to fiptool:
1457 - Enabled the fiptool to be built using Visual Studio.
1459 - Added padding bytes at the end of the last image in the fip to be
1460 facilitate transfer by DMA.
1462 Issues resolved since last release
1463 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1465 - TF-A can be built with optimisations disabled (-O0).
1467 - Memory layout updated to enable Trusted Board Boot on Juno platform when
1468 running TF-A in AArch32 execution mode (resolving `tf-issue#501`_).
1473 - DTB creation not supported when building on a Windows host. This step in the
1474 build process is skipped when running on a Windows host.
1482 - Enabled support for platforms with hardware assisted coherency.
1484 A new build option HW_ASSISTED_COHERENCY allows platforms to take advantage
1485 of the following optimisations:
1487 - Skip performing cache maintenance during power-up and power-down.
1489 - Use spin-locks instead of bakery locks.
1491 - Enable data caches early on warm-booted CPUs.
1493 - Added support for Cortex-A75 and Cortex-A55 processors.
1495 Both Cortex-A75 and Cortex-A55 processors use the Arm DynamIQ Shared Unit
1496 (DSU). The power-down and power-up sequences are therefore mostly managed in
1497 hardware, reducing complexity of the software operations.
1499 - Introduced Arm GIC-600 driver.
1501 Arm GIC-600 IP complies with Arm GICv3 architecture. For FVP platforms, the
1502 GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600.
1504 - Updated GICv3 support:
1506 - Introduced power management APIs for GICv3 Redistributor. These APIs
1507 allow platforms to power down the Redistributor during CPU power on/off.
1508 Requires the GICv3 implementations to have power management operations.
1510 Implemented the power management APIs for FVP.
1512 - GIC driver data is flushed by the primary CPU so that secondary CPU do
1513 not read stale GIC data.
1515 - Added support for Arm System Control and Management Interface v1.0 (SCMI).
1517 The SCMI driver implements the power domain management and system power
1518 management protocol of the SCMI specification (Arm DEN 0056ASCMI) for
1519 communicating with any compliant power controller.
1521 Support is added for the Juno platform. The driver can be found in the
1522 plat/arm/css/drivers folder.
1524 - Added support to enable pre-integration of TBB with the Arm TrustZone
1525 CryptoCell product, to take advantage of its hardware Root of Trust and
1526 crypto acceleration services.
1528 - Enabled Statistical Profiling Extensions for lower ELs.
1530 The firmware support is limited to the use of SPE in the Non-secure state
1531 and accesses to the SPE specific registers from S-EL1 will trap to EL3.
1533 The SPE are architecturally specified for AArch64 only.
1535 - Code hygiene changes aligned with MISRA guidelines:
1537 - Fixed signed / unsigned comparison warnings in the translation table
1540 - Added U(_x) macro and together with the existing ULL(_x) macro fixed
1541 some of the signed-ness defects flagged by the MISRA scanner.
1543 - Enhancements to Firmware Update feature:
1545 - The FWU logic now checks for overlapping images to prevent execution of
1546 unauthenticated arbitrary code.
1548 - Introduced new FWU_SMC_IMAGE_RESET SMC that changes the image loading
1549 state machine to go from COPYING, COPIED or AUTHENTICATED states to
1550 RESET state. Previously, this was only possible when the authentication
1551 of an image failed or when the execution of the image finished.
1553 - Fixed integer overflow which addressed TFV-1: Malformed Firmware Update
1554 SMC can result in copy of unexpectedly large data into secure memory.
1556 - Introduced support for Arm Compiler 6 and LLVM (clang).
1558 TF-A can now also be built with the Arm Compiler 6 or the clang compilers.
1559 The assembler and linker must be provided by the GNU toolchain.
1561 Tested with Arm CC 6.7 and clang 3.9.x and 4.0.x.
1563 - Memory footprint improvements:
1565 - Introduced `tf_snprintf`, a reduced version of `snprintf` which has
1566 support for a limited set of formats.
1568 The mbedtls driver is updated to optionally use `tf_snprintf` instead of
1571 - The `assert()` is updated to no longer print the function name, and
1572 additional logging options are supported via an optional platform define
1573 `PLAT_LOG_LEVEL_ASSERT`, which controls how verbose the assert output is.
1575 - Enhancements to TF-A support when running in AArch32 execution state:
1577 - Support booting SP_MIN and BL33 in AArch32 execution mode on Juno. Due to
1578 hardware limitations, BL1 and BL2 boot in AArch64 state and there is
1579 additional trampoline code to warm reset into SP_MIN in AArch32 execution
1582 - Added support for Arm Cortex-A53/57/72 MPCore processors including the
1583 errata workarounds that are already implemented for AArch64 execution
1586 - For FVP platforms, added AArch32 Trusted Board Boot support, including the
1587 Firmware Update feature.
1589 - Introduced Arm SiP service for use by Arm standard platforms.
1591 - Added new Arm SiP Service SMCs to enable the Non-secure world to read PMF
1594 Added PMF instrumentation points in TF-A in order to quantify the
1595 overall time spent in the PSCI software implementation.
1597 - Added new Arm SiP service SMC to switch execution state.
1599 This allows the lower exception level to change its execution state from
1600 AArch64 to AArch32, or vice verse, via a request to EL3.
1602 - Migrated to use SPDX[0] license identifiers to make software license
1606 Files that have been imported by FreeBSD have not been modified.
1608 [0]: https://spdx.org/
1610 - Enhancements to the translation table library:
1612 - Added version 2 of translation table library that allows different
1613 translation tables to be modified by using different 'contexts'. Version 1
1614 of the translation table library only allows the current EL's translation
1615 tables to be modified.
1617 Version 2 of the translation table also added support for dynamic
1618 regions; regions that can be added and removed dynamically whilst the
1619 MMU is enabled. Static regions can only be added or removed before the
1622 The dynamic mapping functionality is enabled or disabled when compiling
1623 by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1 or 0. This can
1626 - Added support for translation regimes with two virtual address spaces
1627 such as the one shared by EL1 and EL0.
1629 The library does not support initializing translation tables for EL0
1632 - Added support to mark the translation tables as non-cacheable using an
1633 additional build option `XLAT_TABLE_NC`.
1635 - Added support for GCC stack protection. A new build option
1636 ENABLE_STACK_PROTECTOR was introduced that enables compilation of all BL
1637 images with one of the GCC -fstack-protector-* options.
1639 A new platform function plat_get_stack_protector_canary() was introduced
1640 that returns a value used to initialize the canary for stack corruption
1641 detection. For increased effectiveness of protection platforms must provide
1642 an implementation that returns a random value.
1644 - Enhanced support for Arm platforms:
1646 - Added support for multi-threading CPUs, indicated by `MT` field in MPDIR.
1647 A new build flag `ARM_PLAT_MT` is added, and when enabled, the functions
1648 accessing MPIDR assume that the `MT` bit is set for the platform and
1649 access the bit fields accordingly.
1651 Also, a new API `plat_arm_get_cpu_pe_count` is added when `ARM_PLAT_MT` is
1652 enabled, returning the Processing Element count within the physical CPU
1653 corresponding to `mpidr`.
1655 - The Arm platforms migrated to use version 2 of the translation tables.
1657 - Introduced a new Arm platform layer API `plat_arm_psci_override_pm_ops`
1658 which allows Arm platforms to modify `plat_arm_psci_pm_ops` and therefore
1659 dynamically define PSCI capability.
1661 - The Arm platforms migrated to use IMAGE_LOAD_V2 by default.
1663 - Enhanced reporting of errata workaround status with the following policy:
1665 - If an errata workaround is enabled:
1667 - If it applies (i.e. the CPU is affected by the errata), an INFO message
1668 is printed, confirming that the errata workaround has been applied.
1670 - If it does not apply, a VERBOSE message is printed, confirming that the
1671 errata workaround has been skipped.
1673 - If an errata workaround is not enabled, but would have applied had it
1674 been, a WARN message is printed, alerting that errata workaround is
1677 - Added build options ARM_ARCH_MAJOR and ARM_ARM_MINOR to choose the
1678 architecture version to target TF-A.
1680 - Updated the spin lock implementation to use the more efficient CAS (Compare
1681 And Swap) instruction when available. This instruction was introduced in
1684 - Applied errata workaround for Arm Cortex-A53: 855873.
1686 - Applied errata workaround for Arm-Cortex-A57: 813419.
1688 - Enabled all A53 and A57 errata workarounds for Juno, both in AArch64 and
1689 AArch32 execution states.
1691 - Added support for Socionext UniPhier SoC platform.
1693 - Added support for Hikey960 and Hikey platforms.
1695 - Added support for Rockchip RK3328 platform.
1697 - Added support for NVidia Tegra T186 platform.
1699 - Added support for Designware emmc driver.
1701 - Imported libfdt v1.4.2 that addresses buffer overflow in fdt_offset_ptr().
1703 - Enhanced the CPU operations framework to allow power handlers to be
1704 registered on per-level basis. This enables support for future CPUs that
1705 have multiple threads which might need powering down individually.
1707 - Updated register initialisation to prevent unexpected behaviour:
1709 - Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
1710 unexpected traps into the higher exception levels and disable secure
1711 self-hosted debug. Additionally, secure privileged external debug on
1712 Juno is disabled by programming the appropriate Juno SoC registers.
1714 - EL2 and EL3 configurable controls are initialised to avoid unexpected
1715 traps in the higher exception levels.
1717 - Essential control registers are fully initialised on EL3 start-up, when
1718 initialising the non-secure and secure context structures and when
1719 preparing to leave EL3 for a lower EL. This gives better alignment with
1720 the Arm ARM which states that software must initialise RES0 and RES1
1723 - Enhanced PSCI support:
1725 - Introduced new platform interfaces that decouple PSCI stat residency
1726 calculation from PMF, enabling platforms to use alternative methods of
1727 capturing timestamps.
1729 - PSCI stat accounting performed for retention/standby states when
1730 requested at multiple power levels.
1732 - Simplified fiptool to have a single linked list of image descriptors.
1734 - For the TSP, resolved corruption of pre-empted secure context by aborting any
1735 pre-empted SMC during PSCI power management requests.
1737 Issues resolved since last release
1738 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1740 - TF-A can be built with the latest mbed TLS version (v2.4.2). The earlier
1741 version 2.3.0 cannot be used due to build warnings that the TF-A build
1742 system interprets as errors.
1744 - TBBR, including the Firmware Update feature is now supported on FVP
1745 platforms when running TF-A in AArch32 state.
1747 - The version of the AEMv8 Base FVP used in this release has resolved the issue
1748 of the model executing a reset instead of terminating in response to a
1749 shutdown request using the PSCI SYSTEM_OFF API.
1754 - Building TF-A with compiler optimisations disabled (-O0) fails.
1756 - Trusted Board Boot currently does not work on Juno when running Trusted
1757 Firmware in AArch32 execution state due to error when loading the sp_min to
1758 memory because of lack of free space available. See `tf-issue#501`_ for more
1761 - The errata workaround for A53 errata 843419 is only available from binutils
1762 2.26 and is not present in GCC4.9. If this errata is applicable to the
1763 platform, please use GCC compiler version of at least 5.0. See `PR#1002`_ for
1773 - Added support for running TF-A in AArch32 execution state.
1775 The PSCI library has been refactored to allow integration with **EL3 Runtime
1776 Software**. This is software that is executing at the highest secure
1777 privilege which is EL3 in AArch64 or Secure SVC/Monitor mode in AArch32. See
1778 :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
1780 Included is a minimal AArch32 Secure Payload, **SP-MIN**, that illustrates
1781 the usage and integration of the PSCI library with EL3 Runtime Software
1782 running in AArch32 state.
1784 Booting to the BL1/BL2 images as well as booting straight to the Secure
1785 Payload is supported.
1787 - Improvements to the initialization framework for the PSCI service and Arm
1788 Standard Services in general.
1790 The PSCI service is now initialized as part of Arm Standard Service
1791 initialization. This consolidates the initializations of any Arm Standard
1792 Service that may be added in the future.
1794 A new function ``get_arm_std_svc_args()`` is introduced to get arguments
1795 corresponding to each standard service and must be implemented by the EL3
1798 For PSCI, a new versioned structure ``psci_lib_args_t`` is introduced to
1799 initialize the PSCI Library. **Note** this is a compatibility break due to
1800 the change in the prototype of ``psci_setup()``.
1802 - To support AArch32 builds of BL1 and BL2, implemented a new, alternative
1803 firmware image loading mechanism that adds flexibility.
1805 The current mechanism has a hard-coded set of images and execution order
1806 (BL31, BL32, etc). The new mechanism is data-driven by a list of image
1807 descriptors provided by the platform code.
1809 Arm platforms have been updated to support the new loading mechanism.
1811 The new mechanism is enabled by a build flag (``LOAD_IMAGE_V2``) which is
1812 currently off by default for the AArch64 build.
1814 **Note** ``TRUSTED_BOARD_BOOT`` is currently not supported when
1815 ``LOAD_IMAGE_V2`` is enabled.
1817 - Updated requirements for making contributions to TF-A.
1819 Commits now must have a 'Signed-off-by:' field to certify that the
1820 contribution has been made under the terms of the
1821 :download:`Developer Certificate of Origin <../dco.txt>`.
1823 A signed CLA is no longer required.
1825 The :ref:`Contributor's Guide` has been updated to reflect this change.
1827 - Introduced Performance Measurement Framework (PMF) which provides support
1828 for capturing, storing, dumping and retrieving time-stamps to measure the
1829 execution time of critical paths in the firmware. This relies on defining
1830 fixed sample points at key places in the code.
1832 - To support the QEMU platform port, imported libfdt v1.4.1 from
1833 https://git.kernel.org/pub/scm/utils/dtc/dtc.git
1835 - Updated PSCI support:
1837 - Added support for PSCI NODE_HW_STATE API for Arm platforms.
1839 - New optional platform hook, ``pwr_domain_pwr_down_wfi()``, in
1840 ``plat_psci_ops`` to enable platforms to perform platform-specific actions
1841 needed to enter powerdown, including the 'wfi' invocation.
1843 - PSCI STAT residency and count functions have been added on Arm platforms
1846 - Enhancements to the translation table library:
1848 - Limited memory mapping support for region overlaps to only allow regions
1849 to overlap that are identity mapped or have the same virtual to physical
1850 address offset, and overlap completely but must not cover the same area.
1852 This limitation will enable future enhancements without having to
1853 support complex edge cases that may not be necessary.
1855 - The initial translation lookup level is now inferred from the virtual
1856 address space size. Previously, it was hard-coded.
1858 - Added support for mapping Normal, Inner Non-cacheable, Outer
1859 Non-cacheable memory in the translation table library.
1861 This can be useful to map a non-cacheable memory region, such as a DMA
1864 - Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to
1865 specify the access permissions for instruction execution of a memory
1868 - Enabled support to isolate code and read-only data on separate memory pages,
1869 allowing independent access control to be applied to each.
1871 - Enabled SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common
1872 architectural setup code, preventing fetching instructions from non-secure
1873 memory when in secure state.
1875 - Enhancements to FIP support:
1877 - Replaced ``fip_create`` with ``fiptool`` which provides a more consistent
1878 and intuitive interface as well as additional support to remove an image
1881 - Enabled printing the SHA256 digest with info command, allowing quick
1882 verification of an image within a FIP without having to extract the
1883 image and running sha256sum on it.
1885 - Added support for unpacking the contents of an existing FIP file into
1886 the working directory.
1888 - Aligned command line options for specifying images to use same naming
1889 convention as specified by TBBR and already used in cert_create tool.
1891 - Refactored the TZC-400 driver to also support memory controllers that
1892 integrate TZC functionality, for example Arm CoreLink DMC-500. Also added
1893 DMC-500 specific support.
1895 - Implemented generic delay timer based on the system generic counter and
1896 migrated all platforms to use it.
1898 - Enhanced support for Arm platforms:
1900 - Updated image loading support to make SCP images (SCP_BL2 and SCP_BL2U)
1903 - Enhanced topology description support to allow multi-cluster topology
1906 - Added interconnect abstraction layer to help platform ports select the
1907 right interconnect driver, CCI or CCN, for the platform.
1909 - Added support to allow loading BL31 in the TZC-secured DRAM instead of
1910 the default secure SRAM.
1912 - Added support to use a System Security Control (SSC) Registers Unit
1913 enabling TF-A to be compiled to support multiple Arm platforms and
1914 then select one at runtime.
1916 - Restricted mapping of Trusted ROM in BL1 to what is actually needed by
1917 BL1 rather than entire Trusted ROM region.
1919 - Flash is now mapped as execute-never by default. This increases security
1920 by restricting the executable region to what is strictly needed.
1922 - Applied following erratum workarounds for Cortex-A57: 833471, 826977,
1923 829520, 828024 and 826974.
1925 - Added support for Mediatek MT6795 platform.
1927 - Added support for QEMU virtualization Armv8-A target.
1929 - Added support for Rockchip RK3368 and RK3399 platforms.
1931 - Added support for Xilinx Zynq UltraScale+ MPSoC platform.
1933 - Added support for Arm Cortex-A73 MPCore Processor.
1935 - Added support for Arm Cortex-A72 processor.
1937 - Added support for Arm Cortex-A35 processor.
1939 - Added support for Arm Cortex-A32 MPCore Processor.
1941 - Enabled preloaded BL33 alternative boot flow, in which BL2 does not load
1942 BL33 from non-volatile storage and BL31 hands execution over to a preloaded
1943 BL33. The User Guide has been updated with an example of how to use this
1944 option with a bootwrapped kernel.
1946 - Added support to build TF-A on a Windows-based host machine.
1948 - Updated Trusted Board Boot prototype implementation:
1950 - Enabled the ability for a production ROM with TBBR enabled to boot test
1951 software before a real ROTPK is deployed (e.g. manufacturing mode).
1952 Added support to use ROTPK in certificate without verifying against the
1953 platform value when ``ROTPK_NOT_DEPLOYED`` bit is set.
1955 - Added support for non-volatile counter authentication to the
1956 Authentication Module to protect against roll-back.
1958 - Updated GICv3 support:
1960 - Enabled processor power-down and automatic power-on using GICv3.
1962 - Enabled G1S or G0 interrupts to be configured independently.
1964 - Changed FVP default interrupt driver to be the GICv3-only driver.
1965 **Note** the default build of TF-A will not be able to boot
1966 Linux kernel with GICv2 FDT blob.
1968 - Enabled wake-up from CPU_SUSPEND to stand-by by temporarily re-routing
1969 interrupts and then restoring after resume.
1971 Issues resolved since last release
1972 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1977 - The version of the AEMv8 Base FVP used in this release resets the model
1978 instead of terminating its execution in response to a shutdown request using
1979 the PSCI ``SYSTEM_OFF`` API. This issue will be fixed in a future version of
1982 - Building TF-A with compiler optimisations disabled (``-O0``) fails.
1984 - TF-A cannot be built with mbed TLS version v2.3.0 due to build warnings
1985 that the TF-A build system interprets as errors.
1987 - TBBR is not currently supported when running TF-A in AArch32 state.
1995 - The Trusted Board Boot implementation on Arm platforms now conforms to the
1996 mandatory requirements of the TBBR specification.
1998 In particular, the boot process is now guarded by a Trusted Watchdog, which
1999 will reset the system in case of an authentication or loading error. On Arm
2000 platforms, a secure instance of Arm SP805 is used as the Trusted Watchdog.
2002 Also, a firmware update process has been implemented. It enables
2003 authenticated firmware to update firmware images from external interfaces to
2004 SoC Non-Volatile memories. This feature functions even when the current
2005 firmware in the system is corrupt or missing; it therefore may be used as
2008 - Improvements have been made to the Certificate Generation Tool
2009 (``cert_create``) as follows.
2011 - Added support for the Firmware Update process by extending the Chain
2012 of Trust definition in the tool to include the Firmware Update
2013 certificate and the required extensions.
2015 - Introduced a new API that allows one to specify command line options in
2016 the Chain of Trust description. This makes the declaration of the tool's
2017 arguments more flexible and easier to extend.
2019 - The tool has been reworked to follow a data driven approach, which
2020 makes it easier to maintain and extend.
2022 - Extended the FIP tool (``fip_create``) to support the new set of images
2023 involved in the Firmware Update process.
2025 - Various memory footprint improvements. In particular:
2027 - The bakery lock structure for coherent memory has been optimised.
2029 - The mbed TLS SHA1 functions are not needed, as SHA256 is used to
2030 generate the certificate signature. Therefore, they have been compiled
2031 out, reducing the memory footprint of BL1 and BL2 by approximately
2034 - On Arm development platforms, each BL stage now individually defines
2035 the number of regions that it needs to map in the MMU.
2037 - Added the following new design documents:
2039 - :ref:`Authentication Framework & Chain of Trust`
2040 - :ref:`Firmware Update (FWU)`
2042 - :ref:`PSCI Power Domain Tree Structure`
2044 - Applied the new image terminology to the code base and documentation, as
2045 described in the :ref:`Image Terminology` document.
2047 - The build system has been reworked to improve readability and facilitate
2048 adding future extensions.
2050 - On Arm standard platforms, BL31 uses the boot console during cold boot
2051 but switches to the runtime console for any later logs at runtime. The TSP
2052 uses the runtime console for all output.
2054 - Implemented a basic NOR flash driver for Arm platforms. It programs the
2055 device using CFI (Common Flash Interface) standard commands.
2057 - Implemented support for booting EL3 payloads on Arm platforms, which
2058 reduces the complexity of developing EL3 baremetal code by doing essential
2059 baremetal initialization.
2061 - Provided separate drivers for GICv3 and GICv2. These expect the entire
2062 software stack to use either GICv2 or GICv3; hybrid GIC software systems
2063 are no longer supported and the legacy Arm GIC driver has been deprecated.
2065 - Added support for Juno r1 and r2. A single set of Juno TF-A binaries can run
2066 on Juno r0, r1 and r2 boards. Note that this TF-A version depends on a Linaro
2067 release that does *not* contain Juno r2 support.
2069 - Added support for MediaTek mt8173 platform.
2071 - Implemented a generic driver for Arm CCN IP.
2073 - Major rework of the PSCI implementation.
2075 - Added framework to handle composite power states.
2077 - Decoupled the notions of affinity instances (which describes the
2078 hierarchical arrangement of cores) and of power domain topology, instead
2079 of assuming a one-to-one mapping.
2081 - Better alignment with version 1.0 of the PSCI specification.
2083 - Added support for the SYSTEM_SUSPEND PSCI API on Arm platforms. When invoked
2084 on the last running core on a supported platform, this puts the system
2085 into a low power mode with memory retention.
2087 - Unified the reset handling code as much as possible across BL stages.
2088 Also introduced some build options to enable optimization of the reset path
2089 on platforms that support it.
2091 - Added a simple delay timer API, as well as an SP804 timer driver, which is
2094 - Added support for NVidia Tegra T210 and T132 SoCs.
2096 - Reorganised Arm platforms ports to greatly improve code shareability and
2097 facilitate the reuse of some of this code by other platforms.
2099 - Added support for Arm Cortex-A72 processor in the CPU specific framework.
2101 - Provided better error handling. Platform ports can now define their own
2102 error handling, for example to perform platform specific bookkeeping or
2105 - Implemented a unified driver for Arm Cache Coherent Interconnects used for
2106 both CCI-400 & CCI-500 IPs. Arm platforms ports have been migrated to this
2107 common driver. The standalone CCI-400 driver has been deprecated.
2109 Issues resolved since last release
2110 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2112 - The Trusted Board Boot implementation has been redesigned to provide greater
2113 modularity and scalability. See the
2114 :ref:`Authentication Framework & Chain of Trust` document.
2115 All missing mandatory features are now implemented.
2117 - The FVP and Juno ports may now use the hash of the ROTPK stored in the
2118 Trusted Key Storage registers to verify the ROTPK. Alternatively, a
2119 development public key hash embedded in the BL1 and BL2 binaries might be
2120 used instead. The location of the ROTPK is chosen at build-time using the
2121 ``ARM_ROTPK_LOCATION`` build option.
2123 - GICv3 is now fully supported and stable.
2128 - The version of the AEMv8 Base FVP used in this release resets the model
2129 instead of terminating its execution in response to a shutdown request using
2130 the PSCI ``SYSTEM_OFF`` API. This issue will be fixed in a future version of
2133 - While this version has low on-chip RAM requirements, there are further
2134 RAM usage enhancements that could be made.
2136 - The upstream documentation could be improved for structural consistency,
2137 clarity and completeness. In particular, the design documentation is
2138 incomplete for PSCI, the TSP(D) and the Juno platform.
2140 - Building TF-A with compiler optimisations disabled (``-O0``) fails.
2148 - A prototype implementation of Trusted Board Boot has been added. Boot
2149 loader images are verified by BL1 and BL2 during the cold boot path. BL1 and
2150 BL2 use the PolarSSL SSL library to verify certificates and images. The
2151 OpenSSL library is used to create the X.509 certificates. Support has been
2152 added to ``fip_create`` tool to package the certificates in a FIP.
2154 - Support for calling CPU and platform specific reset handlers upon entry into
2155 BL3-1 during the cold and warm boot paths has been added. This happens after
2156 another Boot ROM ``reset_handler()`` has already run. This enables a developer
2157 to perform additional actions or undo actions already performed during the
2158 first call of the reset handlers e.g. apply additional errata workarounds.
2160 - Support has been added to demonstrate routing of IRQs to EL3 instead of
2161 S-EL1 when execution is in secure world.
2163 - The PSCI implementation now conforms to version 1.0 of the PSCI
2164 specification. All the mandatory APIs and selected optional APIs are
2165 supported. In particular, support for the ``PSCI_FEATURES`` API has been
2166 added. A capability variable is constructed during initialization by
2167 examining the ``plat_pm_ops`` and ``spd_pm_ops`` exported by the platform and
2168 the Secure Payload Dispatcher. This is used by the PSCI FEATURES function
2169 to determine which PSCI APIs are supported by the platform.
2171 - Improvements have been made to the PSCI code as follows.
2173 - The code has been refactored to remove redundant parameters from
2176 - Changes have been made to the code for PSCI ``CPU_SUSPEND``, ``CPU_ON`` and
2177 ``CPU_OFF`` calls to facilitate an early return to the caller in case a
2178 failure condition is detected. For example, a PSCI ``CPU_SUSPEND`` call
2179 returns ``SUCCESS`` to the caller if a pending interrupt is detected early
2182 - Optional platform APIs have been added to validate the ``power_state`` and
2183 ``entrypoint`` parameters early in PSCI ``CPU_ON`` and ``CPU_SUSPEND`` code
2186 - PSCI migrate APIs have been reworked to invoke the SPD hook to determine
2187 the type of Trusted OS and the CPU it is resident on (if
2188 applicable). Also, during a PSCI ``MIGRATE`` call, the SPD hook to migrate
2189 the Trusted OS is invoked.
2191 - It is now possible to build TF-A without marking at least an extra page of
2192 memory as coherent. The build flag ``USE_COHERENT_MEM`` can be used to
2193 choose between the two implementations. This has been made possible through
2196 - An implementation of Bakery locks, where the locks are not allocated in
2197 coherent memory has been added.
2199 - Memory which was previously marked as coherent is now kept coherent
2200 through the use of software cache maintenance operations.
2202 Approximately, 4K worth of memory is saved for each boot loader stage when
2203 ``USE_COHERENT_MEM=0``. Enabling this option increases the latencies
2204 associated with acquire and release of locks. It also requires changes to
2207 - It is now possible to specify the name of the FIP at build time by defining
2208 the ``FIP_NAME`` variable.
2210 - Issues with dependencies on the 'fiptool' makefile target have been
2211 rectified. The ``fip_create`` tool is now rebuilt whenever its source files
2214 - The BL3-1 runtime console is now also used as the crash console. The crash
2215 console is changed to SoC UART0 (UART2) from the previous FPGA UART0 (UART0)
2216 on Juno. In FVP, it is changed from UART0 to UART1.
2218 - CPU errata workarounds are applied only when the revision and part number
2219 match. This behaviour has been made consistent across the debug and release
2220 builds. The debug build additionally prints a warning if a mismatch is
2223 - It is now possible to issue cache maintenance operations by set/way for a
2224 particular level of data cache. Levels 1-3 are currently supported.
2226 - The following improvements have been made to the FVP port.
2228 - The build option ``FVP_SHARED_DATA_LOCATION`` which allowed relocation of
2229 shared data into the Trusted DRAM has been deprecated. Shared data is
2230 now always located at the base of Trusted SRAM.
2232 - BL2 Translation tables have been updated to map only the region of
2233 DRAM which is accessible to normal world. This is the region of the 2GB
2234 DDR-DRAM memory at 0x80000000 excluding the top 16MB. The top 16MB is
2235 accessible to only the secure world.
2237 - BL3-2 can now reside in the top 16MB of DRAM which is accessible only to
2238 the secure world. This can be done by setting the build flag
2239 ``FVP_TSP_RAM_LOCATION`` to the value ``dram``.
2241 - Separate translation tables are created for each boot loader image. The
2242 ``IMAGE_BLx`` build options are used to do this. This allows each stage to
2243 create mappings only for areas in the memory map that it needs.
2245 - A Secure Payload Dispatcher (OPTEED) for the OP-TEE Trusted OS has been
2246 added. Details of using it with TF-A can be found in :ref:`OP-TEE Dispatcher`
2248 Issues resolved since last release
2249 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2251 - The Juno port has been aligned with the FVP port as follows.
2253 - Support for reclaiming all BL1 RW memory and BL2 memory by overlaying
2254 the BL3-1/BL3-2 NOBITS sections on top of them has been added to the
2257 - The top 16MB of the 2GB DDR-DRAM memory at 0x80000000 is configured
2258 using the TZC-400 controller to be accessible only to the secure world.
2260 - The Arm GIC driver is used to configure the GIC-400 instead of using a
2261 GIC driver private to the Juno port.
2263 - PSCI ``CPU_SUSPEND`` calls that target a standby state are now supported.
2265 - The TZC-400 driver is used to configure the controller instead of direct
2266 accesses to the registers.
2268 - The Linux kernel version referred to in the user guide has DVFS and HMP
2271 - DS-5 v5.19 did not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in
2272 CADI server mode. This issue is not seen with DS-5 v5.20 and Version 6.2 of
2273 the Cortex-A57-A53 Base FVPs.
2278 - The Trusted Board Boot implementation is a prototype. There are issues with
2279 the modularity and scalability of the design. Support for a Trusted
2280 Watchdog, firmware update mechanism, recovery images and Trusted debug is
2281 absent. These issues will be addressed in future releases.
2283 - The FVP and Juno ports do not use the hash of the ROTPK stored in the
2284 Trusted Key Storage registers to verify the ROTPK in the
2285 ``plat_match_rotpk()`` function. This prevents the correct establishment of
2286 the Chain of Trust at the first step in the Trusted Board Boot process.
2288 - The version of the AEMv8 Base FVP used in this release resets the model
2289 instead of terminating its execution in response to a shutdown request using
2290 the PSCI ``SYSTEM_OFF`` API. This issue will be fixed in a future version of
2293 - GICv3 support is experimental. There are known issues with GICv3
2294 initialization in the TF-A.
2296 - While this version greatly reduces the on-chip RAM requirements, there are
2297 further RAM usage enhancements that could be made.
2299 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
2300 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
2302 - The Juno-specific firmware design documentation is incomplete.
2310 - It is now possible to map higher physical addresses using non-flat virtual
2311 to physical address mappings in the MMU setup.
2313 - Wider use is now made of the per-CPU data cache in BL3-1 to store:
2315 - Pointers to the non-secure and secure security state contexts.
2317 - A pointer to the CPU-specific operations.
2319 - A pointer to PSCI specific information (for example the current power
2322 - A crash reporting buffer.
2324 - The following RAM usage improvements result in a BL3-1 RAM usage reduction
2325 from 96KB to 56KB (for FVP with TSPD), and a total RAM usage reduction
2326 across all images from 208KB to 88KB, compared to the previous release.
2328 - Removed the separate ``early_exception`` vectors from BL3-1 (2KB code size
2331 - Removed NSRAM from the FVP memory map, allowing the removal of one
2332 (4KB) translation table.
2334 - Eliminated the internal ``psci_suspend_context`` array, saving 2KB.
2336 - Correctly dimensioned the PSCI ``aff_map_node`` array, saving 1.5KB in the
2339 - Removed calling CPU mpidr from the bakery lock API, saving 160 bytes.
2341 - Removed current CPU mpidr from PSCI common code, saving 160 bytes.
2343 - Inlined the mmio accessor functions, saving 360 bytes.
2345 - Fully reclaimed all BL1 RW memory and BL2 memory on the FVP port by
2346 overlaying the BL3-1/BL3-2 NOBITS sections on top of these at runtime.
2348 - Made storing the FP register context optional, saving 0.5KB per context
2349 (8KB on the FVP port, with TSPD enabled and running on 8 CPUs).
2351 - Implemented a leaner ``tf_printf()`` function, allowing the stack to be
2354 - Removed coherent stacks from the codebase. Stacks allocated in normal
2355 memory are now used before and after the MMU is enabled. This saves 768
2356 bytes per CPU in BL3-1.
2358 - Reworked the crash reporting in BL3-1 to use less stack.
2360 - Optimized the EL3 register state stored in the ``cpu_context`` structure
2361 so that registers that do not change during normal execution are
2362 re-initialized each time during cold/warm boot, rather than restored
2363 from memory. This saves about 1.2KB.
2365 - As a result of some of the above, reduced the runtime stack size in all
2366 BL images. For BL3-1, this saves 1KB per CPU.
2368 - PSCI SMC handler improvements to correctly handle calls from secure states
2371 - CPU contexts are now initialized from the ``entry_point_info``. BL3-1 fully
2372 determines the exception level to use for the non-trusted firmware (BL3-3)
2373 based on the SPSR value provided by the BL2 platform code (or otherwise
2374 provided to BL3-1). This allows platform code to directly run non-trusted
2375 firmware payloads at either EL2 or EL1 without requiring an EL2 stub or OS
2378 - Code refactoring improvements:
2380 - Refactored ``fvp_config`` into a common platform header.
2382 - Refactored the fvp gic code to be a generic driver that no longer has an
2383 explicit dependency on platform code.
2385 - Refactored the CCI-400 driver to not have dependency on platform code.
2387 - Simplified the IO driver so it's no longer necessary to call ``io_init()``
2388 and moved all the IO storage framework code to one place.
2390 - Simplified the interface the the TZC-400 driver.
2392 - Clarified the platform porting interface to the TSP.
2394 - Reworked the TSPD setup code to support the alternate BL3-2
2395 initialization flow where BL3-1 generic code hands control to BL3-2,
2396 rather than expecting the TSPD to hand control directly to BL3-2.
2398 - Considerable rework to PSCI generic code to support CPU specific
2401 - Improved console log output, by:
2403 - Adding the concept of debug log levels.
2405 - Rationalizing the existing debug messages and adding new ones.
2407 - Printing out the version of each BL stage at runtime.
2409 - Adding support for printing console output from assembler code,
2410 including when a crash occurs before the C runtime is initialized.
2412 - Moved up to the latest versions of the FVPs, toolchain, EDK2, kernel, Linaro
2413 file system and DS-5.
2415 - On the FVP port, made the use of the Trusted DRAM region optional at build
2416 time (off by default). Normal platforms will not have such a "ready-to-use"
2417 DRAM area so it is not a good example to use it.
2419 - Added support for PSCI ``SYSTEM_OFF`` and ``SYSTEM_RESET`` APIs.
2421 - Added support for CPU specific reset sequences, power down sequences and
2422 register dumping during crash reporting. The CPU specific reset sequences
2423 include support for errata workarounds.
2425 - Merged the Juno port into the master branch. Added support for CPU hotplug
2426 and CPU idle. Updated the user guide to describe how to build and run on the
2429 Issues resolved since last release
2430 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2432 - Removed the concept of top/bottom image loading. The image loader now
2433 automatically detects the position of the image inside the current memory
2434 layout and updates the layout to minimize fragmentation. This resolves the
2435 image loader limitations of previously releases. There are currently no
2436 plans to support dynamic image loading.
2438 - CPU idle now works on the publicized version of the Foundation FVP.
2440 - All known issues relating to the compiler version used have now been
2441 resolved. This TF-A version uses Linaro toolchain 14.07 (based on GCC 4.9).
2446 - GICv3 support is experimental. The Linux kernel patches to support this are
2447 not widely available. There are known issues with GICv3 initialization in
2450 - While this version greatly reduces the on-chip RAM requirements, there are
2451 further RAM usage enhancements that could be made.
2453 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
2454 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
2456 - The Juno-specific firmware design documentation is incomplete.
2458 - Some recent enhancements to the FVP port have not yet been translated into
2459 the Juno port. These will be tracked via the tf-issues project.
2461 - The Linux kernel version referred to in the user guide has DVFS and HMP
2462 support disabled due to some known instabilities at the time of this
2463 release. A future kernel version will re-enable these features.
2465 - DS-5 v5.19 does not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in
2466 CADI server mode. This is because the ``<SimName>`` reported by the FVP in
2467 this version has changed. For example, for the Cortex-A57x4-A53x4 Base FVP,
2468 the ``<SimName>`` reported by the FVP is ``FVP_Base_Cortex_A57x4_A53x4``, while
2469 DS-5 expects it to be ``FVP_Base_A57x4_A53x4``.
2471 The temporary fix to this problem is to change the name of the FVP in
2472 ``sw/debugger/configdb/Boards/ARM FVP/Base_A57x4_A53x4/cadi_config.xml``.
2473 Change the following line:
2477 <SimName>System Generator:FVP_Base_A57x4_A53x4</SimName>
2480 System Generator:FVP_Base_Cortex-A57x4_A53x4
2482 A similar change can be made to the other Cortex-A57-A53 Base FVP variants.
2490 - Makefile improvements:
2492 - Improved dependency checking when building.
2494 - Removed ``dump`` target (build now always produces dump files).
2496 - Enabled platform ports to optionally make use of parts of the Trusted
2497 Firmware (e.g. BL3-1 only), rather than being forced to use all parts.
2498 Also made the ``fip`` target optional.
2500 - Specified the full path to source files and removed use of the ``vpath``
2503 - Provided translation table library code for potential re-use by platforms
2504 other than the FVPs.
2506 - Moved architectural timer setup to platform-specific code.
2508 - Added standby state support to PSCI cpu_suspend implementation.
2510 - SRAM usage improvements:
2512 - Started using the ``-ffunction-sections``, ``-fdata-sections`` and
2513 ``--gc-sections`` compiler/linker options to remove unused code and data
2514 from the images. Previously, all common functions were being built into
2515 all binary images, whether or not they were actually used.
2517 - Placed all assembler functions in their own section to allow more unused
2518 functions to be removed from images.
2520 - Updated BL1 and BL2 to use a single coherent stack each, rather than one
2523 - Changed variables that were unnecessarily declared and initialized as
2524 non-const (i.e. in the .data section) so they are either uninitialized
2525 (zero init) or const.
2527 - Moved the Test Secure-EL1 Payload (BL3-2) to execute in Trusted SRAM by
2528 default. The option for it to run in Trusted DRAM remains.
2530 - Implemented a TrustZone Address Space Controller (TZC-400) driver. A
2531 default configuration is provided for the Base FVPs. This means the model
2532 parameter ``-C bp.secure_memory=1`` is now supported.
2534 - Started saving the PSCI cpu_suspend 'power_state' parameter prior to
2535 suspending a CPU. This allows platforms that implement multiple power-down
2536 states at the same affinity level to identify a specific state.
2538 - Refactored the entire codebase to reduce the amount of nesting in header
2539 files and to make the use of system/user includes more consistent. Also
2540 split platform.h to separate out the platform porting declarations from the
2541 required platform porting definitions and the definitions/declarations
2542 specific to the platform port.
2544 - Optimized the data cache clean/invalidate operations.
2546 - Improved the BL3-1 unhandled exception handling and reporting. Unhandled
2547 exceptions now result in a dump of registers to the console.
2549 - Major rework to the handover interface between BL stages, in particular the
2550 interface to BL3-1. The interface now conforms to a specification and is
2553 - Added support for optionally making the BL3-1 entrypoint a reset handler
2554 (instead of BL1). This allows platforms with an alternative image loading
2555 architecture to re-use BL3-1 with fewer modifications to generic code.
2557 - Reserved some DDR DRAM for secure use on FVP platforms to avoid future
2558 compatibility problems with non-secure software.
2560 - Added support for secure interrupts targeting the Secure-EL1 Payload (SP)
2561 (using GICv2 routing only). Demonstrated this working by adding an interrupt
2562 target and supporting test code to the TSP. Also demonstrated non-secure
2563 interrupt handling during TSP processing.
2565 Issues resolved since last release
2566 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2568 - Now support use of the model parameter ``-C bp.secure_memory=1`` in the Base
2569 FVPs (see **New features**).
2571 - Support for secure world interrupt handling now available (see **New
2574 - Made enough SRAM savings (see **New features**) to enable the Test Secure-EL1
2575 Payload (BL3-2) to execute in Trusted SRAM by default.
2577 - The tested filesystem used for this release (Linaro AArch64 OpenEmbedded
2578 14.04) now correctly reports progress in the console.
2580 - Improved the Makefile structure to make it easier to separate out parts of
2581 the TF-A for re-use in platform ports. Also, improved target dependency
2587 - GICv3 support is experimental. The Linux kernel patches to support this are
2588 not widely available. There are known issues with GICv3 initialization in
2591 - Dynamic image loading is not available yet. The current image loader
2592 implementation (used to load BL2 and all subsequent images) has some
2593 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead
2594 to loading errors, even if the images should theoretically fit in memory.
2596 - TF-A still uses too much on-chip Trusted SRAM. A number of RAM usage
2597 enhancements have been identified to rectify this situation.
2599 - CPU idle does not work on the advertised version of the Foundation FVP.
2600 Some FVP fixes are required that are not available externally at the time
2601 of writing. This can be worked around by disabling CPU idle in the Linux
2604 - Various bugs in TF-A, UEFI and the Linux kernel have been observed when
2605 using Linaro toolchain versions later than 13.11. Although most of these
2606 have been fixed, some remain at the time of writing. These mainly seem to
2607 relate to a subtle change in the way the compiler converts between 64-bit
2608 and 32-bit values (e.g. during casting operations), which reveals
2609 previously hidden bugs in client code.
2611 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
2612 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
2620 - Support for Foundation FVP Version 2.0 added.
2621 The documented UEFI configuration disables some devices that are unavailable
2622 in the Foundation FVP, including MMC and CLCD. The resultant UEFI binary can
2623 be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation
2627 The software will not work on Version 1.0 of the Foundation FVP.
2629 - Enabled third party contributions. Added a new contributing.md containing
2630 instructions for how to contribute and updated copyright text in all files
2631 to acknowledge contributors.
2633 - The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be
2634 used for entry into power down states with the following restrictions:
2636 - Entry into standby states is not supported.
2637 - The API is only supported on the AEMv8 and Cortex-A57-A53 Base FVPs.
2639 - The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to
2640 allow experimental use.
2642 - Required C library and runtime header files are now included locally in
2643 TF-A instead of depending on the toolchain standard include paths. The
2644 local implementation has been cleaned up and reduced in scope.
2646 - Added I/O abstraction framework, primarily to allow generic code to load
2647 images in a platform-independent way. The existing image loading code has
2648 been reworked to use the new framework. Semi-hosting and NOR flash I/O
2649 drivers are provided.
2651 - Introduced Firmware Image Package (FIP) handling code and tools. A FIP
2652 combines multiple firmware images with a Table of Contents (ToC) into a
2653 single binary image. The new FIP driver is another type of I/O driver. The
2654 Makefile builds a FIP by default and the FVP platform code expect to load a
2655 FIP from NOR flash, although some support for image loading using semi-
2656 hosting is retained.
2659 Building a FIP by default is a non-backwards-compatible change.
2662 Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into
2663 DRAM instead of expecting this to be pre-loaded at known location. This is
2664 also a non-backwards-compatible change.
2667 Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that
2668 it knows the new location to execute from and no longer needs to copy
2669 particular code modules to DRAM itself.
2671 - Reworked BL2 to BL3-1 handover interface. A new composite structure
2672 (bl31_args) holds the superset of information that needs to be passed from
2673 BL2 to BL3-1, including information on how handover execution control to
2674 BL3-2 (if present) and BL3-3 (non-trusted firmware).
2676 - Added library support for CPU context management, allowing the saving and
2679 - Shared system registers between Secure-EL1 and EL1.
2681 - Essential EL3 system registers.
2683 - Added a framework for implementing EL3 runtime services. Reworked the PSCI
2684 implementation to be one such runtime service.
2686 - Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3
2687 stack pointers for determining the type of exception, managing general
2688 purpose and system register context on exception entry/exit, and handling
2689 SMCs. SMCs are directed to the correct EL3 runtime service.
2691 - Added support for a Test Secure-EL1 Payload (TSP) and a corresponding
2692 Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD
2693 implements Secure Monitor functionality such as world switching and
2694 EL1 context management, and is responsible for communication with the TSP.
2697 The TSPD does not yet contain support for secure world interrupts.
2699 The TSP/TSPD is not built by default.
2701 Issues resolved since last release
2702 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2704 - Support has been added for switching context between secure and normal
2707 - PSCI API calls ``AFFINITY_INFO`` & ``PSCI_VERSION`` have now been tested (to
2710 - The TF-A build artifacts are now placed in the ``./build`` directory and
2711 sub-directories instead of being placed in the root of the project.
2713 - TF-A is now free from build warnings. Build warnings are now treated as
2716 - TF-A now provides C library support locally within the project to maintain
2717 compatibility between toolchains/systems.
2719 - The PSCI locking code has been reworked so it no longer takes locks in an
2722 - The RAM-disk method of loading a Linux file-system has been confirmed to
2723 work with the TF-A and Linux kernel version (based on version 3.13) used
2724 in this release, for both Foundation and Base FVPs.
2729 The following is a list of issues which are expected to be fixed in the future
2732 - The TrustZone Address Space Controller (TZC-400) is not being programmed
2733 yet. Use of model parameter ``-C bp.secure_memory=1`` is not supported.
2735 - No support yet for secure world interrupt handling.
2737 - GICv3 support is experimental. The Linux kernel patches to support this are
2738 not widely available. There are known issues with GICv3 initialization in
2741 - Dynamic image loading is not available yet. The current image loader
2742 implementation (used to load BL2 and all subsequent images) has some
2743 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead
2744 to loading errors, even if the images should theoretically fit in memory.
2746 - TF-A uses too much on-chip Trusted SRAM. Currently the Test Secure-EL1
2747 Payload (BL3-2) executes in Trusted DRAM since there is not enough SRAM.
2748 A number of RAM usage enhancements have been identified to rectify this
2751 - CPU idle does not work on the advertised version of the Foundation FVP.
2752 Some FVP fixes are required that are not available externally at the time
2755 - Various bugs in TF-A, UEFI and the Linux kernel have been observed when
2756 using Linaro toolchain versions later than 13.11. Although most of these
2757 have been fixed, some remain at the time of writing. These mainly seem to
2758 relate to a subtle change in the way the compiler converts between 64-bit
2759 and 32-bit values (e.g. during casting operations), which reveals
2760 previously hidden bugs in client code.
2762 - The tested filesystem used for this release (Linaro AArch64 OpenEmbedded
2763 14.01) does not report progress correctly in the console. It only seems to
2764 produce error output, not standard output. It otherwise appears to function
2765 correctly. Other filesystem versions on the same software stack do not
2766 exhibit the problem.
2768 - The Makefile structure doesn't make it easy to separate out parts of the
2769 TF-A for re-use in platform ports, for example if only BL3-1 is required in
2770 a platform port. Also, dependency checking in the Makefile is flawed.
2772 - The firmware design documentation for the Test Secure-EL1 Payload (TSP) and
2773 its dispatcher (TSPD) is incomplete. Similarly for the PSCI section.
2781 - First source release.
2783 - Code for the PSCI suspend feature is supplied, although this is not enabled
2784 by default since there are known issues (see below).
2786 Issues resolved since last release
2787 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2789 - The "psci" nodes in the FDTs provided in this release now fully comply
2790 with the recommendations made in the PSCI specification.
2795 The following is a list of issues which are expected to be fixed in the future
2798 - The TrustZone Address Space Controller (TZC-400) is not being programmed
2799 yet. Use of model parameter ``-C bp.secure_memory=1`` is not supported.
2801 - No support yet for secure world interrupt handling or for switching context
2802 between secure and normal worlds in EL3.
2804 - GICv3 support is experimental. The Linux kernel patches to support this are
2805 not widely available. There are known issues with GICv3 initialization in
2808 - Dynamic image loading is not available yet. The current image loader
2809 implementation (used to load BL2 and all subsequent images) has some
2810 limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead
2811 to loading errors, even if the images should theoretically fit in memory.
2813 - Although support for PSCI ``CPU_SUSPEND`` is present, it is not yet stable
2816 - PSCI API calls ``AFFINITY_INFO`` & ``PSCI_VERSION`` are implemented but have
2819 - The TF-A make files result in all build artifacts being placed in the root
2820 of the project. These should be placed in appropriate sub-directories.
2822 - The compilation of TF-A is not free from compilation warnings. Some of these
2823 warnings have not been investigated yet so they could mask real bugs.
2825 - TF-A currently uses toolchain/system include files like stdio.h. It should
2826 provide versions of these within the project to maintain compatibility
2827 between toolchains/systems.
2829 - The PSCI code takes some locks in an incorrect sequence. This may cause
2830 problems with suspend and hotplug in certain conditions.
2832 - The Linux kernel used in this release is based on version 3.12-rc4. Using
2833 this kernel with the TF-A fails to start the file-system as a RAM-disk. It
2834 fails to execute user-space ``init`` from the RAM-disk. As an alternative,
2835 the VirtioBlock mechanism can be used to provide a file-system to the
2840 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
2842 .. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
2843 .. _tf-issue#501: https://github.com/ARM-software/tf-issues/issues/501
2844 .. _PR#1002: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
2845 .. _mbed TLS releases: https://tls.mbed.org/tech-updates/releases