7 Porting Trusted Firmware-A (TF-A) to a new platform involves making some
8 mandatory and optional modifications for both the cold and warm boot paths.
9 Modifications consist of:
11 - Implementing a platform-specific function or variable,
12 - Setting up the execution context in a certain way, or
13 - Defining certain constants (for example #defines).
15 The platform-specific functions and variables are declared in
16 `include/plat/common/platform.h`_. The firmware provides a default implementation
17 of variables and functions to fulfill the optional requirements. These
18 implementations are all weakly defined; they are provided to ease the porting
19 effort. Each platform port can override them with its own implementation if the
20 default implementation is inadequate.
22 Some modifications are common to all Boot Loader (BL) stages. Section 2
23 discusses these in detail. The subsequent sections discuss the remaining
24 modifications for each BL stage in detail.
26 This document should be read in conjunction with the TF-A `User Guide`_.
28 Please refer to the `Platform compatibility policy`_ for the policy regarding
29 compatibility and deprecation of these porting interfaces.
31 Only Arm development platforms (such as FVP and Juno) may use the
32 functions/definitions in ``include/plat/arm/common/`` and the corresponding
33 source files in ``plat/arm/common/``. This is done so that there are no
34 dependencies between platforms maintained by different people/companies. If you
35 want to use any of the functionality present in ``plat/arm`` files, please
36 create a pull request that moves the code to ``plat/common`` so that it can be
42 This section covers the modifications that should be made by the platform for
43 each BL stage to correctly port the firmware stack. They are categorized as
44 either mandatory or optional.
46 Common mandatory modifications
47 ------------------------------
49 A platform port must enable the Memory Management Unit (MMU) as well as the
50 instruction and data caches for each BL stage. Setting up the translation
51 tables is the responsibility of the platform port because memory maps differ
52 across platforms. A memory translation library (see ``lib/xlat_tables/``) is
53 provided to help in this setup.
55 Note that although this library supports non-identity mappings, this is intended
56 only for re-mapping peripheral physical addresses and allows platforms with high
57 I/O addresses to reduce their virtual address space. All other addresses
58 corresponding to code and data must currently use an identity mapping.
60 Also, the only translation granule size supported in TF-A is 4KB, as various
61 parts of the code assume that is the case. It is not possible to switch to
62 16 KB or 64 KB granule sizes at the moment.
64 In Arm standard platforms, each BL stage configures the MMU in the
65 platform-specific architecture setup function, ``blX_plat_arch_setup()``, and uses
66 an identity mapping for all addresses.
68 If the build option ``USE_COHERENT_MEM`` is enabled, each platform can allocate a
69 block of identity mapped secure memory with Device-nGnRE attributes aligned to
70 page boundary (4K) for each BL stage. All sections which allocate coherent
71 memory are grouped under ``coherent_ram``. For ex: Bakery locks are placed in a
72 section identified by name ``bakery_lock`` inside ``coherent_ram`` so that its
73 possible for the firmware to place variables in it using the following C code
78 __section("bakery_lock")
80 Or alternatively the following assembler code directive:
86 The ``coherent_ram`` section is a sum of all sections like ``bakery_lock`` which are
87 used to allocate any data structures that are accessed both when a CPU is
88 executing with its MMU and caches enabled, and when it's running with its MMU
89 and caches disabled. Examples are given below.
91 The following variables, functions and constants must be defined by the platform
92 for the firmware to work correctly.
94 File : platform_def.h [mandatory]
95 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
97 Each platform must ensure that a header file of this name is in the system
98 include path with the following constants defined. This will require updating
99 the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
101 Platform ports may optionally use the file `include/plat/common/common_def.h`_,
102 which provides typical values for some of the constants below. These values are
103 likely to be suitable for all platform ports.
105 - **#define : PLATFORM_LINKER_FORMAT**
107 Defines the linker format used by the platform, for example
108 ``elf64-littleaarch64``.
110 - **#define : PLATFORM_LINKER_ARCH**
112 Defines the processor architecture for the linker by the platform, for
115 - **#define : PLATFORM_STACK_SIZE**
117 Defines the normal stack memory available to each CPU. This constant is used
118 by `plat/common/aarch64/platform_mp_stack.S`_ and
119 `plat/common/aarch64/platform_up_stack.S`_.
121 - **define : CACHE_WRITEBACK_GRANULE**
123 Defines the size in bits of the largest cache line across all the cache
124 levels in the platform.
126 - **#define : FIRMWARE_WELCOME_STR**
128 Defines the character string printed by BL1 upon entry into the ``bl1_main()``
131 - **#define : PLATFORM_CORE_COUNT**
133 Defines the total number of CPUs implemented by the platform across all
134 clusters in the system.
136 - **#define : PLAT_NUM_PWR_DOMAINS**
138 Defines the total number of nodes in the power domain topology
139 tree at all the power domain levels used by the platform.
140 This macro is used by the PSCI implementation to allocate
141 data structures to represent power domain topology.
143 - **#define : PLAT_MAX_PWR_LVL**
145 Defines the maximum power domain level that the power management operations
146 should apply to. More often, but not always, the power domain level
147 corresponds to affinity level. This macro allows the PSCI implementation
148 to know the highest power domain level that it should consider for power
149 management operations in the system that the platform implements. For
150 example, the Base AEM FVP implements two clusters with a configurable
151 number of CPUs and it reports the maximum power domain level as 1.
153 - **#define : PLAT_MAX_OFF_STATE**
155 Defines the local power state corresponding to the deepest power down
156 possible at every power domain level in the platform. The local power
157 states for each level may be sparsely allocated between 0 and this value
158 with 0 being reserved for the RUN state. The PSCI implementation uses this
159 value to initialize the local power states of the power domain nodes and
160 to specify the requested power state for a PSCI_CPU_OFF call.
162 - **#define : PLAT_MAX_RET_STATE**
164 Defines the local power state corresponding to the deepest retention state
165 possible at every power domain level in the platform. This macro should be
166 a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
167 PSCI implementation to distinguish between retention and power down local
168 power states within PSCI_CPU_SUSPEND call.
170 - **#define : PLAT_MAX_PWR_LVL_STATES**
172 Defines the maximum number of local power states per power domain level
173 that the platform supports. The default value of this macro is 2 since
174 most platforms just support a maximum of two local power states at each
175 power domain level (power-down and retention). If the platform needs to
176 account for more local power states, then it must redefine this macro.
178 Currently, this macro is used by the Generic PSCI implementation to size
179 the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
181 - **#define : BL1_RO_BASE**
183 Defines the base address in secure ROM where BL1 originally lives. Must be
184 aligned on a page-size boundary.
186 - **#define : BL1_RO_LIMIT**
188 Defines the maximum address in secure ROM that BL1's actual content (i.e.
189 excluding any data section allocated at runtime) can occupy.
191 - **#define : BL1_RW_BASE**
193 Defines the base address in secure RAM where BL1's read-write data will live
194 at runtime. Must be aligned on a page-size boundary.
196 - **#define : BL1_RW_LIMIT**
198 Defines the maximum address in secure RAM that BL1's read-write data can
201 - **#define : BL2_BASE**
203 Defines the base address in secure RAM where BL1 loads the BL2 binary image.
204 Must be aligned on a page-size boundary. This constant is not applicable
205 when BL2_IN_XIP_MEM is set to '1'.
207 - **#define : BL2_LIMIT**
209 Defines the maximum address in secure RAM that the BL2 image can occupy.
210 This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
212 - **#define : BL2_RO_BASE**
214 Defines the base address in secure XIP memory where BL2 RO section originally
215 lives. Must be aligned on a page-size boundary. This constant is only needed
216 when BL2_IN_XIP_MEM is set to '1'.
218 - **#define : BL2_RO_LIMIT**
220 Defines the maximum address in secure XIP memory that BL2's actual content
221 (i.e. excluding any data section allocated at runtime) can occupy. This
222 constant is only needed when BL2_IN_XIP_MEM is set to '1'.
224 - **#define : BL2_RW_BASE**
226 Defines the base address in secure RAM where BL2's read-write data will live
227 at runtime. Must be aligned on a page-size boundary. This constant is only
228 needed when BL2_IN_XIP_MEM is set to '1'.
230 - **#define : BL2_RW_LIMIT**
232 Defines the maximum address in secure RAM that BL2's read-write data can
233 occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
236 - **#define : BL31_BASE**
238 Defines the base address in secure RAM where BL2 loads the BL31 binary
239 image. Must be aligned on a page-size boundary.
241 - **#define : BL31_LIMIT**
243 Defines the maximum address in secure RAM that the BL31 image can occupy.
245 For every image, the platform must define individual identifiers that will be
246 used by BL1 or BL2 to load the corresponding image into memory from non-volatile
247 storage. For the sake of performance, integer numbers will be used as
248 identifiers. The platform will use those identifiers to return the relevant
249 information about the image to be loaded (file handler, load address,
250 authentication information, etc.). The following image identifiers are
253 - **#define : BL2_IMAGE_ID**
255 BL2 image identifier, used by BL1 to load BL2.
257 - **#define : BL31_IMAGE_ID**
259 BL31 image identifier, used by BL2 to load BL31.
261 - **#define : BL33_IMAGE_ID**
263 BL33 image identifier, used by BL2 to load BL33.
265 If Trusted Board Boot is enabled, the following certificate identifiers must
268 - **#define : TRUSTED_BOOT_FW_CERT_ID**
270 BL2 content certificate identifier, used by BL1 to load the BL2 content
273 - **#define : TRUSTED_KEY_CERT_ID**
275 Trusted key certificate identifier, used by BL2 to load the trusted key
278 - **#define : SOC_FW_KEY_CERT_ID**
280 BL31 key certificate identifier, used by BL2 to load the BL31 key
283 - **#define : SOC_FW_CONTENT_CERT_ID**
285 BL31 content certificate identifier, used by BL2 to load the BL31 content
288 - **#define : NON_TRUSTED_FW_KEY_CERT_ID**
290 BL33 key certificate identifier, used by BL2 to load the BL33 key
293 - **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
295 BL33 content certificate identifier, used by BL2 to load the BL33 content
298 - **#define : FWU_CERT_ID**
300 Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
301 FWU content certificate.
303 - **#define : PLAT_CRYPTOCELL_BASE**
305 This defines the base address of Arm® TrustZone® CryptoCell and must be
306 defined if CryptoCell crypto driver is used for Trusted Board Boot. For
307 capable Arm platforms, this driver is used if ``ARM_CRYPTOCELL_INTEG`` is
310 If the AP Firmware Updater Configuration image, BL2U is used, the following
311 must also be defined:
313 - **#define : BL2U_BASE**
315 Defines the base address in secure memory where BL1 copies the BL2U binary
316 image. Must be aligned on a page-size boundary.
318 - **#define : BL2U_LIMIT**
320 Defines the maximum address in secure memory that the BL2U image can occupy.
322 - **#define : BL2U_IMAGE_ID**
324 BL2U image identifier, used by BL1 to fetch an image descriptor
325 corresponding to BL2U.
327 If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
328 must also be defined:
330 - **#define : SCP_BL2U_IMAGE_ID**
332 SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
333 corresponding to SCP_BL2U.
336 TF-A does not provide source code for this image.
338 If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
341 - **#define : NS_BL1U_BASE**
343 Defines the base address in non-secure ROM where NS_BL1U executes.
344 Must be aligned on a page-size boundary.
347 TF-A does not provide source code for this image.
349 - **#define : NS_BL1U_IMAGE_ID**
351 NS_BL1U image identifier, used by BL1 to fetch an image descriptor
352 corresponding to NS_BL1U.
354 If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
357 - **#define : NS_BL2U_BASE**
359 Defines the base address in non-secure memory where NS_BL2U executes.
360 Must be aligned on a page-size boundary.
363 TF-A does not provide source code for this image.
365 - **#define : NS_BL2U_IMAGE_ID**
367 NS_BL2U image identifier, used by BL1 to fetch an image descriptor
368 corresponding to NS_BL2U.
370 For the the Firmware update capability of TRUSTED BOARD BOOT, the following
371 macros may also be defined:
373 - **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
375 Total number of images that can be loaded simultaneously. If the platform
376 doesn't specify any value, it defaults to 10.
378 If a SCP_BL2 image is supported by the platform, the following constants must
381 - **#define : SCP_BL2_IMAGE_ID**
383 SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
384 from platform storage before being transferred to the SCP.
386 - **#define : SCP_FW_KEY_CERT_ID**
388 SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
389 certificate (mandatory when Trusted Board Boot is enabled).
391 - **#define : SCP_FW_CONTENT_CERT_ID**
393 SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
394 content certificate (mandatory when Trusted Board Boot is enabled).
396 If a BL32 image is supported by the platform, the following constants must
399 - **#define : BL32_IMAGE_ID**
401 BL32 image identifier, used by BL2 to load BL32.
403 - **#define : TRUSTED_OS_FW_KEY_CERT_ID**
405 BL32 key certificate identifier, used by BL2 to load the BL32 key
406 certificate (mandatory when Trusted Board Boot is enabled).
408 - **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
410 BL32 content certificate identifier, used by BL2 to load the BL32 content
411 certificate (mandatory when Trusted Board Boot is enabled).
413 - **#define : BL32_BASE**
415 Defines the base address in secure memory where BL2 loads the BL32 binary
416 image. Must be aligned on a page-size boundary.
418 - **#define : BL32_LIMIT**
420 Defines the maximum address that the BL32 image can occupy.
422 If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
423 platform, the following constants must also be defined:
425 - **#define : TSP_SEC_MEM_BASE**
427 Defines the base address of the secure memory used by the TSP image on the
428 platform. This must be at the same address or below ``BL32_BASE``.
430 - **#define : TSP_SEC_MEM_SIZE**
432 Defines the size of the secure memory used by the BL32 image on the
433 platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
434 accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
437 - **#define : TSP_IRQ_SEC_PHY_TIMER**
439 Defines the ID of the secure physical generic timer interrupt used by the
440 TSP's interrupt handling code.
442 If the platform port uses the translation table library code, the following
443 constants must also be defined:
445 - **#define : PLAT_XLAT_TABLES_DYNAMIC**
447 Optional flag that can be set per-image to enable the dynamic allocation of
448 regions even when the MMU is enabled. If not defined, only static
449 functionality will be available, if defined and set to 1 it will also
450 include the dynamic functionality.
452 - **#define : MAX_XLAT_TABLES**
454 Defines the maximum number of translation tables that are allocated by the
455 translation table library code. To minimize the amount of runtime memory
456 used, choose the smallest value needed to map the required virtual addresses
457 for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is enabled for a BL
458 image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
461 - **#define : MAX_MMAP_REGIONS**
463 Defines the maximum number of regions that are allocated by the translation
464 table library code. A region consists of physical base address, virtual base
465 address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
466 defined in the ``mmap_region_t`` structure. The platform defines the regions
467 that should be mapped. Then, the translation table library will create the
468 corresponding tables and descriptors at runtime. To minimize the amount of
469 runtime memory used, choose the smallest value needed to register the
470 required regions for each BL stage. If ``PLAT_XLAT_TABLES_DYNAMIC`` flag is
471 enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
472 the dynamic regions as well.
474 - **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
476 Defines the total size of the virtual address space in bytes. For example,
477 for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
479 - **#define : PLAT_PHY_ADDR_SPACE_SIZE**
481 Defines the total size of the physical address space in bytes. For example,
482 for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
484 If the platform port uses the IO storage framework, the following constants
485 must also be defined:
487 - **#define : MAX_IO_DEVICES**
489 Defines the maximum number of registered IO devices. Attempting to register
490 more devices than this value using ``io_register_device()`` will fail with
493 - **#define : MAX_IO_HANDLES**
495 Defines the maximum number of open IO handles. Attempting to open more IO
496 entities than this value using ``io_open()`` will fail with -ENOMEM.
498 - **#define : MAX_IO_BLOCK_DEVICES**
500 Defines the maximum number of registered IO block devices. Attempting to
501 register more devices this value using ``io_dev_open()`` will fail
502 with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
503 With this macro, multiple block devices could be supported at the same
506 If the platform needs to allocate data within the per-cpu data framework in
507 BL31, it should define the following macro. Currently this is only required if
508 the platform decides not to use the coherent memory section by undefining the
509 ``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
510 required memory within the the per-cpu data to minimize wastage.
512 - **#define : PLAT_PCPU_DATA_SIZE**
514 Defines the memory (in bytes) to be reserved within the per-cpu data
515 structure for use by the platform layer.
517 The following constants are optional. They should be defined when the platform
518 memory layout implies some image overlaying like in Arm standard platforms.
520 - **#define : BL31_PROGBITS_LIMIT**
522 Defines the maximum address in secure RAM that the BL31's progbits sections
525 - **#define : TSP_PROGBITS_LIMIT**
527 Defines the maximum address that the TSP's progbits sections can occupy.
529 If the platform port uses the PL061 GPIO driver, the following constant may
530 optionally be defined:
532 - **PLAT_PL061_MAX_GPIOS**
533 Maximum number of GPIOs required by the platform. This allows control how
534 much memory is allocated for PL061 GPIO controllers. The default value is
536 #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
538 If the platform port uses the partition driver, the following constant may
539 optionally be defined:
541 - **PLAT_PARTITION_MAX_ENTRIES**
542 Maximum number of partition entries required by the platform. This allows
543 control how much memory is allocated for partition entries. The default
545 `For example, define the build flag in platform.mk`_:
546 PLAT_PARTITION_MAX_ENTRIES := 12
547 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
549 - **PLAT_PARTITION_BLOCK_SIZE**
550 The size of partition block. It could be either 512 bytes or 4096 bytes.
551 The default value is 512.
552 `For example, define the build flag in platform.mk`_:
553 PLAT_PARTITION_BLOCK_SIZE := 4096
554 $(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
556 The following constant is optional. It should be defined to override the default
557 behaviour of the ``assert()`` function (for example, to save memory).
559 - **PLAT_LOG_LEVEL_ASSERT**
560 If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
561 ``assert()`` prints the name of the file, the line number and the asserted
562 expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
563 name and the line number. Else if it is lower than ``LOG_LEVEL_INFO``, it
564 doesn't print anything to the console. If ``PLAT_LOG_LEVEL_ASSERT`` isn't
565 defined, it defaults to ``LOG_LEVEL``.
567 If the platform port uses the Activity Monitor Unit, the following constants
570 - **PLAT_AMU_GROUP1_COUNTERS_MASK**
571 This mask reflects the set of group counters that should be enabled. The
572 maximum number of group 1 counters supported by AMUv1 is 16 so the mask
573 can be at most 0xffff. If the platform does not define this mask, no group 1
574 counters are enabled. If the platform defines this mask, the following
575 constant needs to also be defined.
577 - **PLAT_AMU_GROUP1_NR_COUNTERS**
578 This value is used to allocate an array to save and restore the counters
579 specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend.
580 This value should be equal to the highest bit position set in the
581 mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16.
583 File : plat_macros.S [mandatory]
584 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
586 Each platform must ensure a file of this name is in the system include path with
587 the following macro defined. In the Arm development platforms, this file is
588 found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
590 - **Macro : plat_crash_print_regs**
592 This macro allows the crash reporting routine to print relevant platform
593 registers in case of an unhandled exception in BL31. This aids in debugging
594 and this macro can be defined to be empty in case register reporting is not
597 For instance, GIC or interconnect registers may be helpful for
603 BL1 by default implements the reset vector where execution starts from a cold
604 or warm boot. BL31 can be optionally set as a reset vector using the
605 ``RESET_TO_BL31`` make variable.
607 For each CPU, the reset vector code is responsible for the following tasks:
609 #. Distinguishing between a cold boot and a warm boot.
611 #. In the case of a cold boot and the CPU being a secondary CPU, ensuring that
612 the CPU is placed in a platform-specific state until the primary CPU
613 performs the necessary steps to remove it from this state.
615 #. In the case of a warm boot, ensuring that the CPU jumps to a platform-
616 specific address in the BL31 image in the same processor mode as it was
617 when released from reset.
619 The following functions need to be implemented by the platform port to enable
620 reset vector code to perform the above tasks.
622 Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
623 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
630 This function is called with the MMU and caches disabled
631 (``SCTLR_EL3.M`` = 0 and ``SCTLR_EL3.C`` = 0). The function is responsible for
632 distinguishing between a warm and cold reset for the current CPU using
633 platform-specific means. If it's a warm reset, then it returns the warm
634 reset entrypoint point provided to ``plat_setup_psci_ops()`` during
635 BL31 initialization. If it's a cold reset then this function must return zero.
637 This function does not follow the Procedure Call Standard used by the
638 Application Binary Interface for the Arm 64-bit architecture. The caller should
639 not assume that callee saved registers are preserved across a call to this
642 This function fulfills requirement 1 and 3 listed above.
644 Note that for platforms that support programming the reset address, it is
645 expected that a CPU will start executing code directly at the right address,
646 both on a cold and warm reset. In this case, there is no need to identify the
647 type of reset nor to query the warm reset entrypoint. Therefore, implementing
648 this function is not required on such platforms.
650 Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
651 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
657 This function is called with the MMU and data caches disabled. It is responsible
658 for placing the executing secondary CPU in a platform-specific state until the
659 primary CPU performs the necessary actions to bring it out of that state and
660 allow entry into the OS. This function must not return.
662 In the Arm FVP port, when using the normal boot flow, each secondary CPU powers
663 itself off. The primary CPU is responsible for powering up the secondary CPUs
664 when normal world software requires them. When booting an EL3 payload instead,
665 they stay powered on and are put in a holding pen until their mailbox gets
668 This function fulfills requirement 2 above.
670 Note that for platforms that can't release secondary CPUs out of reset, only the
671 primary CPU will execute the cold boot code. Therefore, implementing this
672 function is not required on such platforms.
674 Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
675 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
680 Return : unsigned int
682 This function identifies whether the current CPU is the primary CPU or a
683 secondary CPU. A return value of zero indicates that the CPU is not the
684 primary CPU, while a non-zero return value indicates that the CPU is the
687 Note that for platforms that can't release secondary CPUs out of reset, only the
688 primary CPU will execute the cold boot code. Therefore, there is no need to
689 distinguish between primary and secondary CPUs and implementing this function is
692 Function : platform_mem_init() [mandatory]
693 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
700 This function is called before any access to data is made by the firmware, in
701 order to carry out any essential memory initialization.
703 Function: plat_get_rotpk_info()
704 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
708 Argument : void *, void **, unsigned int *, unsigned int *
711 This function is mandatory when Trusted Board Boot is enabled. It returns a
712 pointer to the ROTPK stored in the platform (or a hash of it) and its length.
713 The ROTPK must be encoded in DER format according to the following ASN.1
718 AlgorithmIdentifier ::= SEQUENCE {
719 algorithm OBJECT IDENTIFIER,
720 parameters ANY DEFINED BY algorithm OPTIONAL
723 SubjectPublicKeyInfo ::= SEQUENCE {
724 algorithm AlgorithmIdentifier,
725 subjectPublicKey BIT STRING
728 In case the function returns a hash of the key:
732 DigestInfo ::= SEQUENCE {
733 digestAlgorithm AlgorithmIdentifier,
737 The function returns 0 on success. Any other value is treated as error by the
738 Trusted Board Boot. The function also reports extra information related
739 to the ROTPK in the flags parameter:
743 ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a
745 ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK
746 verification while the platform ROTPK is not deployed.
747 When this flag is set, the function does not need to
748 return a platform ROTPK, and the authentication
749 framework uses the ROTPK in the certificate without
750 verifying it against the platform value. This flag
751 must not be used in a deployed production environment.
753 Function: plat_get_nv_ctr()
754 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
758 Argument : void *, unsigned int *
761 This function is mandatory when Trusted Board Boot is enabled. It returns the
762 non-volatile counter value stored in the platform in the second argument. The
763 cookie in the first argument may be used to select the counter in case the
764 platform provides more than one (for example, on platforms that use the default
765 TBBR CoT, the cookie will correspond to the OID values defined in
766 TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
768 The function returns 0 on success. Any other value means the counter value could
769 not be retrieved from the platform.
771 Function: plat_set_nv_ctr()
772 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
776 Argument : void *, unsigned int
779 This function is mandatory when Trusted Board Boot is enabled. It sets a new
780 counter value in the platform. The cookie in the first argument may be used to
781 select the counter (as explained in plat_get_nv_ctr()). The second argument is
782 the updated counter value to be written to the NV counter.
784 The function returns 0 on success. Any other value means the counter value could
787 Function: plat_set_nv_ctr2()
788 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
792 Argument : void *, const auth_img_desc_t *, unsigned int
795 This function is optional when Trusted Board Boot is enabled. If this
796 interface is defined, then ``plat_set_nv_ctr()`` need not be defined. The
797 first argument passed is a cookie and is typically used to
798 differentiate between a Non Trusted NV Counter and a Trusted NV
799 Counter. The second argument is a pointer to an authentication image
800 descriptor and may be used to decide if the counter is allowed to be
801 updated or not. The third argument is the updated counter value to
802 be written to the NV counter.
804 The function returns 0 on success. Any other value means the counter value
805 either could not be updated or the authentication image descriptor indicates
806 that it is not allowed to be updated.
808 Common mandatory function modifications
809 ---------------------------------------
811 The following functions are mandatory functions which need to be implemented
812 by the platform port.
814 Function : plat_my_core_pos()
815 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
820 Return : unsigned int
822 This function returns the index of the calling CPU which is used as a
823 CPU-specific linear index into blocks of memory (for example while allocating
824 per-CPU stacks). This function will be invoked very early in the
825 initialization sequence which mandates that this function should be
826 implemented in assembly and should not rely on the availability of a C
827 runtime environment. This function can clobber x0 - x8 and must preserve
830 This function plays a crucial role in the power domain topology framework in
831 PSCI and details of this can be found in `Power Domain Topology Design`_.
833 Function : plat_core_pos_by_mpidr()
834 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
838 Argument : u_register_t
841 This function validates the ``MPIDR`` of a CPU and converts it to an index,
842 which can be used as a CPU-specific linear index into blocks of memory. In
843 case the ``MPIDR`` is invalid, this function returns -1. This function will only
844 be invoked by BL31 after the power domain topology is initialized and can
845 utilize the C runtime environment. For further details about how TF-A
846 represents the power domain topology and how this relates to the linear CPU
847 index, please refer `Power Domain Topology Design`_.
849 Function : plat_get_mbedtls_heap() [when TRUSTED_BOARD_BOOT == 1]
850 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
854 Arguments : void **heap_addr, size_t *heap_size
857 This function is invoked during Mbed TLS library initialisation to get a heap,
858 by means of a starting address and a size. This heap will then be used
859 internally by the Mbed TLS library. Hence, each BL stage that utilises Mbed TLS
860 must be able to provide a heap to it.
862 A helper function can be found in `drivers/auth/mbedtls/mbedtls_common.c` in
863 which a heap is statically reserved during compile time inside every image
864 (i.e. every BL stage) that utilises Mbed TLS. In this default implementation,
865 the function simply returns the address and size of this "pre-allocated" heap.
866 For a platform to use this default implementation, only a call to the helper
867 from inside plat_get_mbedtls_heap() body is enough and nothing else is needed.
869 However, by writting their own implementation, platforms have the potential to
870 optimise memory usage. For example, on some Arm platforms, the Mbed TLS heap is
871 shared between BL1 and BL2 stages and, thus, the necessary space is not reserved
874 On success the function should return 0 and a negative error code otherwise.
876 Common optional modifications
877 -----------------------------
879 The following are helper functions implemented by the firmware that perform
880 common platform-specific tasks. A platform may choose to override these
883 Function : plat_set_my_stack()
884 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
891 This function sets the current stack pointer to the normal memory stack that
892 has been allocated for the current CPU. For BL images that only require a
893 stack for the primary CPU, the UP version of the function is used. The size
894 of the stack allocated to each CPU is specified by the platform defined
895 constant ``PLATFORM_STACK_SIZE``.
897 Common implementations of this function for the UP and MP BL images are
898 provided in `plat/common/aarch64/platform_up_stack.S`_ and
899 `plat/common/aarch64/platform_mp_stack.S`_
901 Function : plat_get_my_stack()
902 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
909 This function returns the base address of the normal memory stack that
910 has been allocated for the current CPU. For BL images that only require a
911 stack for the primary CPU, the UP version of the function is used. The size
912 of the stack allocated to each CPU is specified by the platform defined
913 constant ``PLATFORM_STACK_SIZE``.
915 Common implementations of this function for the UP and MP BL images are
916 provided in `plat/common/aarch64/platform_up_stack.S`_ and
917 `plat/common/aarch64/platform_mp_stack.S`_
919 Function : plat_report_exception()
920 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
924 Argument : unsigned int
927 A platform may need to report various information about its status when an
928 exception is taken, for example the current exception level, the CPU security
929 state (secure/non-secure), the exception type, and so on. This function is
930 called in the following circumstances:
932 - In BL1, whenever an exception is taken.
933 - In BL2, whenever an exception is taken.
935 The default implementation doesn't do anything, to avoid making assumptions
936 about the way the platform displays its status information.
938 For AArch64, this function receives the exception type as its argument.
939 Possible values for exceptions types are listed in the
940 `include/common/bl_common.h`_ header file. Note that these constants are not
941 related to any architectural exception code; they are just a TF-A convention.
943 For AArch32, this function receives the exception mode as its argument.
944 Possible values for exception modes are listed in the
945 `include/lib/aarch32/arch.h`_ header file.
947 Function : plat_reset_handler()
948 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
955 A platform may need to do additional initialization after reset. This function
956 allows the platform to do the platform specific intializations. Platform
957 specific errata workarounds could also be implemented here. The API should
958 preserve the values of callee saved registers x19 to x29.
960 The default implementation doesn't do anything. If a platform needs to override
961 the default implementation, refer to the `Firmware Design`_ for general
964 Function : plat_disable_acp()
965 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
972 This API allows a platform to disable the Accelerator Coherency Port (if
973 present) during a cluster power down sequence. The default weak implementation
974 doesn't do anything. Since this API is called during the power down sequence,
975 it has restrictions for stack usage and it can use the registers x0 - x17 as
976 scratch registers. It should preserve the value in x18 register as it is used
977 by the caller to store the return address.
979 Function : plat_error_handler()
980 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
987 This API is called when the generic code encounters an error situation from
988 which it cannot continue. It allows the platform to perform error reporting or
989 recovery actions (for example, reset the system). This function must not return.
991 The parameter indicates the type of error using standard codes from ``errno.h``.
992 Possible errors reported by the generic code are:
994 - ``-EAUTH``: a certificate or image could not be authenticated (when Trusted
995 Board Boot is enabled)
996 - ``-ENOENT``: the requested image or certificate could not be found or an IO
998 - ``-ENOMEM``: resources exhausted. TF-A does not use dynamic memory, so this
999 error is usually an indication of an incorrect array size
1001 The default implementation simply spins.
1003 Function : plat_panic_handler()
1004 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1011 This API is called when the generic code encounters an unexpected error
1012 situation from which it cannot recover. This function must not return,
1013 and must be implemented in assembly because it may be called before the C
1014 environment is initialized.
1017 The address from where it was called is stored in x30 (Link Register).
1018 The default implementation simply spins.
1020 Function : plat_get_bl_image_load_info()
1021 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1026 Return : bl_load_info_t *
1028 This function returns pointer to the list of images that the platform has
1029 populated to load. This function is invoked in BL2 to load the
1032 Function : plat_get_next_bl_params()
1033 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1038 Return : bl_params_t *
1040 This function returns a pointer to the shared memory that the platform has
1041 kept aside to pass TF-A related information that next BL image needs. This
1042 function is invoked in BL2 to pass this information to the next BL
1045 Function : plat_get_stack_protector_canary()
1046 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1051 Return : u_register_t
1053 This function returns a random value that is used to initialize the canary used
1054 when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
1055 value will weaken the protection as the attacker could easily write the right
1056 value as part of the attack most of the time. Therefore, it should return a
1060 For the protection to be effective, the global data need to be placed at
1061 a lower address than the stack bases. Failure to do so would allow an
1062 attacker to overwrite the canary as part of the stack buffer overflow attack.
1064 Function : plat_flush_next_bl_params()
1065 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1072 This function flushes to main memory all the image params that are passed to
1073 next image. This function is invoked in BL2 to flush this information
1074 to the next BL image.
1076 Function : plat_log_get_prefix()
1077 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1081 Argument : unsigned int
1082 Return : const char *
1084 This function defines the prefix string corresponding to the `log_level` to be
1085 prepended to all the log output from TF-A. The `log_level` (argument) will
1086 correspond to one of the standard log levels defined in debug.h. The platform
1087 can override the common implementation to define a different prefix string for
1088 the log output. The implementation should be robust to future changes that
1089 increase the number of log levels.
1091 Modifications specific to a Boot Loader stage
1092 ---------------------------------------------
1094 Boot Loader Stage 1 (BL1)
1095 -------------------------
1097 BL1 implements the reset vector where execution starts from after a cold or
1098 warm boot. For each CPU, BL1 is responsible for the following tasks:
1100 #. Handling the reset as described in section 2.2
1102 #. In the case of a cold boot and the CPU being the primary CPU, ensuring that
1103 only this CPU executes the remaining BL1 code, including loading and passing
1104 control to the BL2 stage.
1106 #. Identifying and starting the Firmware Update process (if required).
1108 #. Loading the BL2 image from non-volatile storage into secure memory at the
1109 address specified by the platform defined constant ``BL2_BASE``.
1111 #. Populating a ``meminfo`` structure with the following information in memory,
1112 accessible by BL2 immediately upon entry.
1116 meminfo.total_base = Base address of secure RAM visible to BL2
1117 meminfo.total_size = Size of secure RAM visible to BL2
1119 By default, BL1 places this ``meminfo`` structure at the end of secure
1120 memory visible to BL2.
1122 It is possible for the platform to decide where it wants to place the
1123 ``meminfo`` structure for BL2 or restrict the amount of memory visible to
1124 BL2 by overriding the weak default implementation of
1125 ``bl1_plat_handle_post_image_load`` API.
1127 The following functions need to be implemented by the platform port to enable
1128 BL1 to perform the above tasks.
1130 Function : bl1_early_platform_setup() [mandatory]
1131 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1138 This function executes with the MMU and data caches disabled. It is only called
1141 On Arm standard platforms, this function:
1143 - Enables a secure instance of SP805 to act as the Trusted Watchdog.
1145 - Initializes a UART (PL011 console), which enables access to the ``printf``
1146 family of functions in BL1.
1148 - Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to
1149 the CCI slave interface corresponding to the cluster that includes the
1152 Function : bl1_plat_arch_setup() [mandatory]
1153 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1160 This function performs any platform-specific and architectural setup that the
1161 platform requires. Platform-specific setup might include configuration of
1162 memory controllers and the interconnect.
1164 In Arm standard platforms, this function enables the MMU.
1166 This function helps fulfill requirement 2 above.
1168 Function : bl1_platform_setup() [mandatory]
1169 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1176 This function executes with the MMU and data caches enabled. It is responsible
1177 for performing any remaining platform-specific setup that can occur after the
1178 MMU and data cache have been enabled.
1180 if support for multiple boot sources is required, it initializes the boot
1181 sequence used by plat_try_next_boot_source().
1183 In Arm standard platforms, this function initializes the storage abstraction
1184 layer used to load the next bootloader image.
1186 This function helps fulfill requirement 4 above.
1188 Function : bl1_plat_sec_mem_layout() [mandatory]
1189 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1196 This function should only be called on the cold boot path. It executes with the
1197 MMU and data caches enabled. The pointer returned by this function must point to
1198 a ``meminfo`` structure containing the extents and availability of secure RAM for
1203 meminfo.total_base = Base address of secure RAM visible to BL1
1204 meminfo.total_size = Size of secure RAM visible to BL1
1206 This information is used by BL1 to load the BL2 image in secure RAM. BL1 also
1207 populates a similar structure to tell BL2 the extents of memory available for
1210 This function helps fulfill requirements 4 and 5 above.
1212 Function : bl1_plat_prepare_exit() [optional]
1213 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1217 Argument : entry_point_info_t *
1220 This function is called prior to exiting BL1 in response to the
1221 ``BL1_SMC_RUN_IMAGE`` SMC request raised by BL2. It should be used to perform
1222 platform specific clean up or bookkeeping operations before transferring
1223 control to the next image. It receives the address of the ``entry_point_info_t``
1224 structure passed from BL2. This function runs with MMU disabled.
1226 Function : bl1_plat_set_ep_info() [optional]
1227 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1231 Argument : unsigned int image_id, entry_point_info_t *ep_info
1234 This function allows platforms to override ``ep_info`` for the given ``image_id``.
1236 The default implementation just returns.
1238 Function : bl1_plat_get_next_image_id() [optional]
1239 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1244 Return : unsigned int
1246 This and the following function must be overridden to enable the FWU feature.
1248 BL1 calls this function after platform setup to identify the next image to be
1249 loaded and executed. If the platform returns ``BL2_IMAGE_ID`` then BL1 proceeds
1250 with the normal boot sequence, which loads and executes BL2. If the platform
1251 returns a different image id, BL1 assumes that Firmware Update is required.
1253 The default implementation always returns ``BL2_IMAGE_ID``. The Arm development
1254 platforms override this function to detect if firmware update is required, and
1255 if so, return the first image in the firmware update process.
1257 Function : bl1_plat_get_image_desc() [optional]
1258 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1262 Argument : unsigned int image_id
1263 Return : image_desc_t *
1265 BL1 calls this function to get the image descriptor information ``image_desc_t``
1266 for the provided ``image_id`` from the platform.
1268 The default implementation always returns a common BL2 image descriptor. Arm
1269 standard platforms return an image descriptor corresponding to BL2 or one of
1270 the firmware update images defined in the Trusted Board Boot Requirements
1273 Function : bl1_plat_handle_pre_image_load() [optional]
1274 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1278 Argument : unsigned int image_id
1281 This function can be used by the platforms to update/use image information
1282 corresponding to ``image_id``. This function is invoked in BL1, both in cold
1283 boot and FWU code path, before loading the image.
1285 Function : bl1_plat_handle_post_image_load() [optional]
1286 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1290 Argument : unsigned int image_id
1293 This function can be used by the platforms to update/use image information
1294 corresponding to ``image_id``. This function is invoked in BL1, both in cold
1295 boot and FWU code path, after loading and authenticating the image.
1297 The default weak implementation of this function calculates the amount of
1298 Trusted SRAM that can be used by BL2 and allocates a ``meminfo_t``
1299 structure at the beginning of this free memory and populates it. The address
1300 of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
1303 Function : bl1_plat_fwu_done() [optional]
1304 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1308 Argument : unsigned int image_id, uintptr_t image_src,
1309 unsigned int image_size
1312 BL1 calls this function when the FWU process is complete. It must not return.
1313 The platform may override this function to take platform specific action, for
1314 example to initiate the normal boot flow.
1316 The default implementation spins forever.
1318 Function : bl1_plat_mem_check() [mandatory]
1319 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1323 Argument : uintptr_t mem_base, unsigned int mem_size,
1327 BL1 calls this function while handling FWU related SMCs, more specifically when
1328 copying or authenticating an image. Its responsibility is to ensure that the
1329 region of memory identified by ``mem_base`` and ``mem_size`` is mapped in BL1, and
1330 that this memory corresponds to either a secure or non-secure memory region as
1331 indicated by the security state of the ``flags`` argument.
1333 This function can safely assume that the value resulting from the addition of
1334 ``mem_base`` and ``mem_size`` fits into a ``uintptr_t`` type variable and does not
1337 This function must return 0 on success, a non-null error code otherwise.
1339 The default implementation of this function asserts therefore platforms must
1340 override it when using the FWU feature.
1342 Boot Loader Stage 2 (BL2)
1343 -------------------------
1345 The BL2 stage is executed only by the primary CPU, which is determined in BL1
1346 using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
1347 ``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
1348 ``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
1349 non-volatile storage to secure/non-secure RAM. After all the images are loaded
1350 then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
1351 images to be passed to the next BL image.
1353 The following functions must be implemented by the platform port to enable BL2
1354 to perform the above tasks.
1356 Function : bl2_early_platform_setup2() [mandatory]
1357 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1361 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1364 This function executes with the MMU and data caches disabled. It is only called
1365 by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
1366 are platform specific.
1368 On Arm standard platforms, the arguments received are :
1370 arg0 - Points to load address of HW_CONFIG if present
1372 arg1 - ``meminfo`` structure populated by BL1. The platform copies
1373 the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
1375 On Arm standard platforms, this function also:
1377 - Initializes a UART (PL011 console), which enables access to the ``printf``
1378 family of functions in BL2.
1380 - Initializes the storage abstraction layer used to load further bootloader
1381 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1382 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
1384 Function : bl2_plat_arch_setup() [mandatory]
1385 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1392 This function executes with the MMU and data caches disabled. It is only called
1395 The purpose of this function is to perform any architectural initialization
1396 that varies across platforms.
1398 On Arm standard platforms, this function enables the MMU.
1400 Function : bl2_platform_setup() [mandatory]
1401 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1408 This function may execute with the MMU and data caches enabled if the platform
1409 port does the necessary initialization in ``bl2_plat_arch_setup()``. It is only
1410 called by the primary CPU.
1412 The purpose of this function is to perform any platform initialization
1415 In Arm standard platforms, this function performs security setup, including
1416 configuration of the TrustZone controller to allow non-secure masters access
1417 to most of DRAM. Part of DRAM is reserved for secure world use.
1419 Function : bl2_plat_handle_pre_image_load() [optional]
1420 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1424 Argument : unsigned int
1427 This function can be used by the platforms to update/use image information
1428 for given ``image_id``. This function is currently invoked in BL2 before
1431 Function : bl2_plat_handle_post_image_load() [optional]
1432 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1436 Argument : unsigned int
1439 This function can be used by the platforms to update/use image information
1440 for given ``image_id``. This function is currently invoked in BL2 after
1443 Function : bl2_plat_preload_setup [optional]
1444 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1451 This optional function performs any BL2 platform initialization
1452 required before image loading, that is not done later in
1453 bl2_platform_setup(). Specifically, if support for multiple
1454 boot sources is required, it initializes the boot sequence used by
1455 plat_try_next_boot_source().
1457 Function : plat_try_next_boot_source() [optional]
1458 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1465 This optional function passes to the next boot source in the redundancy
1468 This function moves the current boot redundancy source to the next
1469 element in the boot sequence. If there are no more boot sources then it
1470 must return 0, otherwise it must return 1. The default implementation
1471 of this always returns 0.
1473 Boot Loader Stage 2 (BL2) at EL3
1474 --------------------------------
1476 When the platform has a non-TF-A Boot ROM it is desirable to jump
1477 directly to BL2 instead of TF-A BL1. In this case BL2 is expected to
1478 execute at EL3 instead of executing at EL1. Refer to the `Firmware
1479 Design`_ for more information.
1481 All mandatory functions of BL2 must be implemented, except the functions
1482 bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
1483 their work is done now by bl2_el3_early_platform_setup and
1484 bl2_el3_plat_arch_setup. These functions should generally implement
1485 the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
1488 Function : bl2_el3_early_platform_setup() [mandatory]
1489 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1493 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1496 This function executes with the MMU and data caches disabled. It is only called
1497 by the primary CPU. This function receives four parameters which can be used
1498 by the platform to pass any needed information from the Boot ROM to BL2.
1500 On Arm standard platforms, this function does the following:
1502 - Initializes a UART (PL011 console), which enables access to the ``printf``
1503 family of functions in BL2.
1505 - Initializes the storage abstraction layer used to load further bootloader
1506 images. It is necessary to do this early on platforms with a SCP_BL2 image,
1507 since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
1509 - Initializes the private variables that define the memory layout used.
1511 Function : bl2_el3_plat_arch_setup() [mandatory]
1512 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1519 This function executes with the MMU and data caches disabled. It is only called
1522 The purpose of this function is to perform any architectural initialization
1523 that varies across platforms.
1525 On Arm standard platforms, this function enables the MMU.
1527 Function : bl2_el3_plat_prepare_exit() [optional]
1528 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1535 This function is called prior to exiting BL2 and run the next image.
1536 It should be used to perform platform specific clean up or bookkeeping
1537 operations before transferring control to the next image. This function
1538 runs with MMU disabled.
1540 FWU Boot Loader Stage 2 (BL2U)
1541 ------------------------------
1543 The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU
1544 process and is executed only by the primary CPU. BL1 passes control to BL2U at
1545 ``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
1547 #. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
1548 memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
1549 ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
1550 should be copied from. Subsequent handling of the SCP_BL2U image is
1551 implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
1552 If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
1554 #. Any platform specific setup required to perform the FWU process. For
1555 example, Arm standard platforms initialize the TZC controller so that the
1556 normal world can access DDR memory.
1558 The following functions must be implemented by the platform port to enable
1559 BL2U to perform the tasks mentioned above.
1561 Function : bl2u_early_platform_setup() [mandatory]
1562 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1566 Argument : meminfo *mem_info, void *plat_info
1569 This function executes with the MMU and data caches disabled. It is only
1570 called by the primary CPU. The arguments to this function is the address
1571 of the ``meminfo`` structure and platform specific info provided by BL1.
1573 The platform may copy the contents of the ``mem_info`` and ``plat_info`` into
1574 private storage as the original memory may be subsequently overwritten by BL2U.
1576 On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
1577 to extract SCP_BL2U image information, which is then copied into a private
1580 Function : bl2u_plat_arch_setup() [mandatory]
1581 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1588 This function executes with the MMU and data caches disabled. It is only
1589 called by the primary CPU.
1591 The purpose of this function is to perform any architectural initialization
1592 that varies across platforms, for example enabling the MMU (since the memory
1593 map differs across platforms).
1595 Function : bl2u_platform_setup() [mandatory]
1596 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1603 This function may execute with the MMU and data caches enabled if the platform
1604 port does the necessary initialization in ``bl2u_plat_arch_setup()``. It is only
1605 called by the primary CPU.
1607 The purpose of this function is to perform any platform initialization
1610 In Arm standard platforms, this function performs security setup, including
1611 configuration of the TrustZone controller to allow non-secure masters access
1612 to most of DRAM. Part of DRAM is reserved for secure world use.
1614 Function : bl2u_plat_handle_scp_bl2u() [optional]
1615 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1622 This function is used to perform any platform-specific actions required to
1623 handle the SCP firmware. Typically it transfers the image into SCP memory using
1624 a platform-specific protocol and waits until SCP executes it and signals to the
1625 Application Processor (AP) for BL2U execution to continue.
1627 This function returns 0 on success, a negative error code otherwise.
1628 This function is included if SCP_BL2U_BASE is defined.
1630 Boot Loader Stage 3-1 (BL31)
1631 ----------------------------
1633 During cold boot, the BL31 stage is executed only by the primary CPU. This is
1634 determined in BL1 using the ``platform_is_primary_cpu()`` function. BL1 passes
1635 control to BL31 at ``BL31_BASE``. During warm boot, BL31 is executed by all
1636 CPUs. BL31 executes at EL3 and is responsible for:
1638 #. Re-initializing all architectural and platform state. Although BL1 performs
1639 some of this initialization, BL31 remains resident in EL3 and must ensure
1640 that EL3 architectural and platform state is completely initialized. It
1641 should make no assumptions about the system state when it receives control.
1643 #. Passing control to a normal world BL image, pre-loaded at a platform-
1644 specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
1645 populated by BL2 in memory to do this.
1647 #. Providing runtime firmware services. Currently, BL31 only implements a
1648 subset of the Power State Coordination Interface (PSCI) API as a runtime
1649 service. See Section 3.3 below for details of porting the PSCI
1652 #. Optionally passing control to the BL32 image, pre-loaded at a platform-
1653 specific address by BL2. BL31 exports a set of APIs that allow runtime
1654 services to specify the security state in which the next image should be
1655 executed and run the corresponding image. On ARM platforms, BL31 uses the
1656 ``bl_params`` list populated by BL2 in memory to do this.
1658 If BL31 is a reset vector, It also needs to handle the reset as specified in
1659 section 2.2 before the tasks described above.
1661 The following functions must be implemented by the platform port to enable BL31
1662 to perform the above tasks.
1664 Function : bl31_early_platform_setup2() [mandatory]
1665 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1669 Argument : u_register_t, u_register_t, u_register_t, u_register_t
1672 This function executes with the MMU and data caches disabled. It is only called
1673 by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
1676 In Arm standard platforms, the arguments received are :
1678 arg0 - The pointer to the head of `bl_params_t` list
1679 which is list of executable images following BL31,
1681 arg1 - Points to load address of SOC_FW_CONFIG if present
1683 arg2 - Points to load address of HW_CONFIG if present
1685 arg3 - A special value to verify platform parameters from BL2 to BL31. Not
1686 used in release builds.
1688 The function runs through the `bl_param_t` list and extracts the entry point
1689 information for BL32 and BL33. It also performs the following:
1691 - Initialize a UART (PL011 console), which enables access to the ``printf``
1692 family of functions in BL31.
1694 - Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the
1695 CCI slave interface corresponding to the cluster that includes the primary
1698 Function : bl31_plat_arch_setup() [mandatory]
1699 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1706 This function executes with the MMU and data caches disabled. It is only called
1709 The purpose of this function is to perform any architectural initialization
1710 that varies across platforms.
1712 On Arm standard platforms, this function enables the MMU.
1714 Function : bl31_platform_setup() [mandatory]
1715 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1722 This function may execute with the MMU and data caches enabled if the platform
1723 port does the necessary initialization in ``bl31_plat_arch_setup()``. It is only
1724 called by the primary CPU.
1726 The purpose of this function is to complete platform initialization so that both
1727 BL31 runtime services and normal world software can function correctly.
1729 On Arm standard platforms, this function does the following:
1731 - Initialize the generic interrupt controller.
1733 Depending on the GIC driver selected by the platform, the appropriate GICv2
1734 or GICv3 initialization will be done, which mainly consists of:
1736 - Enable secure interrupts in the GIC CPU interface.
1737 - Disable the legacy interrupt bypass mechanism.
1738 - Configure the priority mask register to allow interrupts of all priorities
1739 to be signaled to the CPU interface.
1740 - Mark SGIs 8-15 and the other secure interrupts on the platform as secure.
1741 - Target all secure SPIs to CPU0.
1742 - Enable these secure interrupts in the GIC distributor.
1743 - Configure all other interrupts as non-secure.
1744 - Enable signaling of secure interrupts in the GIC distributor.
1746 - Enable system-level implementation of the generic timer counter through the
1747 memory mapped interface.
1749 - Grant access to the system counter timer module
1751 - Initialize the power controller device.
1753 In particular, initialise the locks that prevent concurrent accesses to the
1754 power controller device.
1756 Function : bl31_plat_runtime_setup() [optional]
1757 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1764 The purpose of this function is allow the platform to perform any BL31 runtime
1765 setup just prior to BL31 exit during cold boot. The default weak
1766 implementation of this function will invoke ``console_switch_state()`` to switch
1767 console output to consoles marked for use in the ``runtime`` state.
1769 Function : bl31_plat_get_next_image_ep_info() [mandatory]
1770 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1775 Return : entry_point_info *
1777 This function may execute with the MMU and data caches enabled if the platform
1778 port does the necessary initializations in ``bl31_plat_arch_setup()``.
1780 This function is called by ``bl31_main()`` to retrieve information provided by
1781 BL2 for the next image in the security state specified by the argument. BL31
1782 uses this information to pass control to that image in the specified security
1783 state. This function must return a pointer to the ``entry_point_info`` structure
1784 (that was copied during ``bl31_early_platform_setup()``) if the image exists. It
1785 should return NULL otherwise.
1787 Function : bl31_plat_enable_mmu [optional]
1788 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1795 This function enables the MMU. The boot code calls this function with MMU and
1796 caches disabled. This function should program necessary registers to enable
1797 translation, and upon return, the MMU on the calling PE must be enabled.
1799 The function must honor flags passed in the first argument. These flags are
1800 defined by the translation library, and can be found in the file
1801 ``include/lib/xlat_tables/xlat_mmu_helpers.h``.
1803 On DynamIQ systems, this function must not use stack while enabling MMU, which
1804 is how the function in xlat table library version 2 is implemented.
1806 Function : plat_init_apkey [optional]
1807 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1814 This function returns the 128-bit value which can be used to program ARMv8.3
1815 pointer authentication keys.
1817 The value should be obtained from a reliable source of randomness.
1819 This function is only needed if ARMv8.3 pointer authentication is used in the
1820 Trusted Firmware by building with ``BRANCH_PROTECTION`` option set to non-zero.
1822 Function : plat_get_syscnt_freq2() [mandatory]
1823 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1828 Return : unsigned int
1830 This function is used by the architecture setup code to retrieve the counter
1831 frequency for the CPU's generic timer. This value will be programmed into the
1832 ``CNTFRQ_EL0`` register. In Arm standard platforms, it returns the base frequency
1833 of the system counter, which is retrieved from the first entry in the frequency
1836 #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
1837 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1839 When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
1840 bytes) aligned to the cache line boundary that should be allocated per-cpu to
1841 accommodate all the bakery locks.
1843 If this constant is not defined when ``USE_COHERENT_MEM = 0``, the linker
1844 calculates the size of the ``bakery_lock`` input section, aligns it to the
1845 nearest ``CACHE_WRITEBACK_GRANULE``, multiplies it with ``PLATFORM_CORE_COUNT``
1846 and stores the result in a linker symbol. This constant prevents a platform
1847 from relying on the linker and provide a more efficient mechanism for
1848 accessing per-cpu bakery lock information.
1850 If this constant is defined and its value is not equal to the value
1851 calculated by the linker then a link time assertion is raised. A compile time
1852 assertion is raised if the value of the constant is not aligned to the cache
1855 SDEI porting requirements
1856 ~~~~~~~~~~~~~~~~~~~~~~~~~
1858 The |SDEI| dispatcher requires the platform to provide the following macros
1859 and functions, of which some are optional, and some others mandatory.
1864 Macro: PLAT_SDEI_NORMAL_PRI [mandatory]
1865 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1867 This macro must be defined to the EL3 exception priority level associated with
1868 Normal |SDEI| events on the platform. This must have a higher value
1869 (therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
1871 Macro: PLAT_SDEI_CRITICAL_PRI [mandatory]
1872 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1874 This macro must be defined to the EL3 exception priority level associated with
1875 Critical |SDEI| events on the platform. This must have a lower value
1876 (therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
1878 **Note**: |SDEI| exception priorities must be the lowest among Secure
1879 priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
1880 be higher than Normal |SDEI| priority.
1885 Function: int plat_sdei_validate_entry_point(uintptr_t ep) [optional]
1886 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1893 This function validates the address of client entry points provided for both
1894 event registration and *Complete and Resume* |SDEI| calls. The function
1895 takes one argument, which is the address of the handler the |SDEI| client
1896 requested to register. The function must return ``0`` for successful validation,
1897 or ``-1`` upon failure.
1899 The default implementation always returns ``0``. On Arm platforms, this function
1900 is implemented to translate the entry point to physical address, and further to
1901 ensure that the address is located in Non-secure DRAM.
1903 Function: void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr) [optional]
1904 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1909 Argument: unsigned int
1912 |SDEI| specification requires that a PE comes out of reset with the events
1913 masked. The client therefore is expected to call ``PE_UNMASK`` to unmask
1914 |SDEI| events on the PE. No |SDEI| events can be dispatched until such
1917 Should a PE receive an interrupt that was bound to an |SDEI| event while the
1918 events are masked on the PE, the dispatcher implementation invokes the function
1919 ``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
1920 interrupt and the interrupt ID are passed as parameters.
1922 The default implementation only prints out a warning message.
1924 Power State Coordination Interface (in BL31)
1925 --------------------------------------------
1927 The TF-A implementation of the PSCI API is based around the concept of a
1928 *power domain*. A *power domain* is a CPU or a logical group of CPUs which
1929 share some state on which power management operations can be performed as
1930 specified by `PSCI`_. Each CPU in the system is assigned a cpu index which is
1931 a unique number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The
1932 *power domains* are arranged in a hierarchical tree structure and each
1933 *power domain* can be identified in a system by the cpu index of any CPU that
1934 is part of that domain and a *power domain level*. A processing element (for
1935 example, a CPU) is at level 0. If the *power domain* node above a CPU is a
1936 logical grouping of CPUs that share some state, then level 1 is that group of
1937 CPUs (for example, a cluster), and level 2 is a group of clusters (for
1938 example, the system). More details on the power domain topology and its
1939 organization can be found in `Power Domain Topology Design`_.
1941 BL31's platform initialization code exports a pointer to the platform-specific
1942 power management operations required for the PSCI implementation to function
1943 correctly. This information is populated in the ``plat_psci_ops`` structure. The
1944 PSCI implementation calls members of the ``plat_psci_ops`` structure for performing
1945 power management operations on the power domains. For example, the target
1946 CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
1947 handler (if present) is called for the CPU power domain.
1949 The ``power-state`` parameter of a PSCI ``CPU_SUSPEND`` call can be used to
1950 describe composite power states specific to a platform. The PSCI implementation
1951 defines a generic representation of the power-state parameter, which is an
1952 array of local power states where each index corresponds to a power domain
1953 level. Each entry contains the local power state the power domain at that power
1954 level could enter. It depends on the ``validate_power_state()`` handler to
1955 convert the power-state parameter (possibly encoding a composite power state)
1956 passed in a PSCI ``CPU_SUSPEND`` call to this representation.
1958 The following functions form part of platform port of PSCI functionality.
1960 Function : plat_psci_stat_accounting_start() [optional]
1961 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1965 Argument : const psci_power_state_t *
1968 This is an optional hook that platforms can implement for residency statistics
1969 accounting before entering a low power state. The ``pwr_domain_state`` field of
1970 ``state_info`` (first argument) can be inspected if stat accounting is done
1971 differently at CPU level versus higher levels. As an example, if the element at
1972 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1973 state, special hardware logic may be programmed in order to keep track of the
1974 residency statistics. For higher levels (array indices > 0), the residency
1975 statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1976 default implementation will use PMF to capture timestamps.
1978 Function : plat_psci_stat_accounting_stop() [optional]
1979 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1983 Argument : const psci_power_state_t *
1986 This is an optional hook that platforms can implement for residency statistics
1987 accounting after exiting from a low power state. The ``pwr_domain_state`` field
1988 of ``state_info`` (first argument) can be inspected if stat accounting is done
1989 differently at CPU level versus higher levels. As an example, if the element at
1990 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
1991 state, special hardware logic may be programmed in order to keep track of the
1992 residency statistics. For higher levels (array indices > 0), the residency
1993 statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
1994 default implementation will use PMF to capture timestamps.
1996 Function : plat_psci_stat_get_residency() [optional]
1997 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2001 Argument : unsigned int, const psci_power_state_t *, int
2002 Return : u_register_t
2004 This is an optional interface that is is invoked after resuming from a low power
2005 state and provides the time spent resident in that low power state by the power
2006 domain at a particular power domain level. When a CPU wakes up from suspend,
2007 all its parent power domain levels are also woken up. The generic PSCI code
2008 invokes this function for each parent power domain that is resumed and it
2009 identified by the ``lvl`` (first argument) parameter. The ``state_info`` (second
2010 argument) describes the low power state that the power domain has resumed from.
2011 The current CPU is the first CPU in the power domain to resume from the low
2012 power state and the ``last_cpu_idx`` (third parameter) is the index of the last
2013 CPU in the power domain to suspend and may be needed to calculate the residency
2014 for that power domain.
2016 Function : plat_get_target_pwr_state() [optional]
2017 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2021 Argument : unsigned int, const plat_local_state_t *, unsigned int
2022 Return : plat_local_state_t
2024 The PSCI generic code uses this function to let the platform participate in
2025 state coordination during a power management operation. The function is passed
2026 a pointer to an array of platform specific local power state ``states`` (second
2027 argument) which contains the requested power state for each CPU at a particular
2028 power domain level ``lvl`` (first argument) within the power domain. The function
2029 is expected to traverse this array of upto ``ncpus`` (third argument) and return
2030 a coordinated target power state by the comparing all the requested power
2031 states. The target power state should not be deeper than any of the requested
2034 A weak definition of this API is provided by default wherein it assumes
2035 that the platform assigns a local state value in order of increasing depth
2036 of the power state i.e. for two power states X & Y, if X < Y
2037 then X represents a shallower power state than Y. As a result, the
2038 coordinated target local power state for a power domain will be the minimum
2039 of the requested local power state values.
2041 Function : plat_get_power_domain_tree_desc() [mandatory]
2042 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2047 Return : const unsigned char *
2049 This function returns a pointer to the byte array containing the power domain
2050 topology tree description. The format and method to construct this array are
2051 described in `Power Domain Topology Design`_. The BL31 PSCI initialization code
2052 requires this array to be described by the platform, either statically or
2053 dynamically, to initialize the power domain topology tree. In case the array
2054 is populated dynamically, then plat_core_pos_by_mpidr() and
2055 plat_my_core_pos() should also be implemented suitably so that the topology
2056 tree description matches the CPU indices returned by these APIs. These APIs
2057 together form the platform interface for the PSCI topology framework.
2059 Function : plat_setup_psci_ops() [mandatory]
2060 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2064 Argument : uintptr_t, const plat_psci_ops **
2067 This function may execute with the MMU and data caches enabled if the platform
2068 port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
2069 called by the primary CPU.
2071 This function is called by PSCI initialization code. Its purpose is to let
2072 the platform layer know about the warm boot entrypoint through the
2073 ``sec_entrypoint`` (first argument) and to export handler routines for
2074 platform-specific psci power management actions by populating the passed
2075 pointer with a pointer to BL31's private ``plat_psci_ops`` structure.
2077 A description of each member of this structure is given below. Please refer to
2078 the Arm FVP specific implementation of these handlers in
2079 `plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the
2080 platform wants to support, the associated operation or operations in this
2081 structure must be provided and implemented (Refer section 4 of
2082 `Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI
2083 function in a platform port, the operation should be removed from this
2084 structure instead of providing an empty implementation.
2086 plat_psci_ops.cpu_standby()
2087 ...........................
2089 Perform the platform-specific actions to enter the standby state for a cpu
2090 indicated by the passed argument. This provides a fast path for CPU standby
2091 wherein overheads of PSCI state management and lock acquisition is avoided.
2092 For this handler to be invoked by the PSCI ``CPU_SUSPEND`` API implementation,
2093 the suspend state type specified in the ``power-state`` parameter should be
2094 STANDBY and the target power domain level specified should be the CPU. The
2095 handler should put the CPU into a low power retention state (usually by
2096 issuing a wfi instruction) and ensure that it can be woken up from that
2097 state by a normal interrupt. The generic code expects the handler to succeed.
2099 plat_psci_ops.pwr_domain_on()
2100 .............................
2102 Perform the platform specific actions to power on a CPU, specified
2103 by the ``MPIDR`` (first argument). The generic code expects the platform to
2104 return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
2106 plat_psci_ops.pwr_domain_off()
2107 ..............................
2109 Perform the platform specific actions to prepare to power off the calling CPU
2110 and its higher parent power domain levels as indicated by the ``target_state``
2111 (first argument). It is called by the PSCI ``CPU_OFF`` API implementation.
2113 The ``target_state`` encodes the platform coordinated target local power states
2114 for the CPU power domain and its parent power domain levels. The handler
2115 needs to perform power management operation corresponding to the local state
2116 at each power level.
2118 For this handler, the local power state for the CPU power domain will be a
2119 power down state where as it could be either power down, retention or run state
2120 for the higher power domain levels depending on the result of state
2121 coordination. The generic code expects the handler to succeed.
2123 plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
2124 ...........................................................
2126 This optional function may be used as a performance optimization to replace
2127 or complement pwr_domain_suspend() on some platforms. Its calling semantics
2128 are identical to pwr_domain_suspend(), except the PSCI implementation only
2129 calls this function when suspending to a power down state, and it guarantees
2130 that data caches are enabled.
2132 When HW_ASSISTED_COHERENCY = 0, the PSCI implementation disables data caches
2133 before calling pwr_domain_suspend(). If the target_state corresponds to a
2134 power down state and it is safe to perform some or all of the platform
2135 specific actions in that function with data caches enabled, it may be more
2136 efficient to move those actions to this function. When HW_ASSISTED_COHERENCY
2137 = 1, data caches remain enabled throughout, and so there is no advantage to
2138 moving platform specific actions to this function.
2140 plat_psci_ops.pwr_domain_suspend()
2141 ..................................
2143 Perform the platform specific actions to prepare to suspend the calling
2144 CPU and its higher parent power domain levels as indicated by the
2145 ``target_state`` (first argument). It is called by the PSCI ``CPU_SUSPEND``
2148 The ``target_state`` has a similar meaning as described in
2149 the ``pwr_domain_off()`` operation. It encodes the platform coordinated
2150 target local power states for the CPU power domain and its parent
2151 power domain levels. The handler needs to perform power management operation
2152 corresponding to the local state at each power level. The generic code
2153 expects the handler to succeed.
2155 The difference between turning a power domain off versus suspending it is that
2156 in the former case, the power domain is expected to re-initialize its state
2157 when it is next powered on (see ``pwr_domain_on_finish()``). In the latter
2158 case, the power domain is expected to save enough state so that it can resume
2159 execution by restoring this state when its powered on (see
2160 ``pwr_domain_suspend_finish()``).
2162 When suspending a core, the platform can also choose to power off the GICv3
2163 Redistributor and ITS through an implementation-defined sequence. To achieve
2164 this safely, the ITS context must be saved first. The architectural part is
2165 implemented by the ``gicv3_its_save_disable()`` helper, but most of the needed
2166 sequence is implementation defined and it is therefore the responsibility of
2167 the platform code to implement the necessary sequence. Then the GIC
2168 Redistributor context can be saved using the ``gicv3_rdistif_save()`` helper.
2169 Powering off the Redistributor requires the implementation to support it and it
2170 is the responsibility of the platform code to execute the right implementation
2173 When a system suspend is requested, the platform can also make use of the
2174 ``gicv3_distif_save()`` helper to save the context of the GIC Distributor after
2175 it has saved the context of the Redistributors and ITS of all the cores in the
2176 system. The context of the Distributor can be large and may require it to be
2177 allocated in a special area if it cannot fit in the platform's global static
2178 data, for example in DRAM. The Distributor can then be powered down using an
2179 implementation-defined sequence.
2181 plat_psci_ops.pwr_domain_pwr_down_wfi()
2182 .......................................
2184 This is an optional function and, if implemented, is expected to perform
2185 platform specific actions including the ``wfi`` invocation which allows the
2186 CPU to powerdown. Since this function is invoked outside the PSCI locks,
2187 the actions performed in this hook must be local to the CPU or the platform
2188 must ensure that races between multiple CPUs cannot occur.
2190 The ``target_state`` has a similar meaning as described in the ``pwr_domain_off()``
2191 operation and it encodes the platform coordinated target local power states for
2192 the CPU power domain and its parent power domain levels. This function must
2193 not return back to the caller.
2195 If this function is not implemented by the platform, PSCI generic
2196 implementation invokes ``psci_power_down_wfi()`` for power down.
2198 plat_psci_ops.pwr_domain_on_finish()
2199 ....................................
2201 This function is called by the PSCI implementation after the calling CPU is
2202 powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
2203 It performs the platform-specific setup required to initialize enough state for
2204 this CPU to enter the normal world and also provide secure runtime firmware
2207 The ``target_state`` (first argument) is the prior state of the power domains
2208 immediately before the CPU was turned on. It indicates which power domains
2209 above the CPU might require initialization due to having previously been in
2210 low power states. The generic code expects the handler to succeed.
2212 plat_psci_ops.pwr_domain_on_finish_late() [optional]
2213 ...........................................................
2215 This optional function is called by the PSCI implementation after the calling
2216 CPU is fully powered on with respective data caches enabled. The calling CPU and
2217 the associated cluster are guaranteed to be participating in coherency. This
2218 function gives the flexibility to perform any platform-specific actions safely,
2219 such as initialization or modification of shared data structures, without the
2220 overhead of explicit cache maintainace operations.
2222 The ``target_state`` has a similar meaning as described in the ``pwr_domain_on_finish()``
2223 operation. The generic code expects the handler to succeed.
2225 plat_psci_ops.pwr_domain_suspend_finish()
2226 .........................................
2228 This function is called by the PSCI implementation after the calling CPU is
2229 powered on and released from reset in response to an asynchronous wakeup
2230 event, for example a timer interrupt that was programmed by the CPU during the
2231 ``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
2232 setup required to restore the saved state for this CPU to resume execution
2233 in the normal world and also provide secure runtime firmware services.
2235 The ``target_state`` (first argument) has a similar meaning as described in
2236 the ``pwr_domain_on_finish()`` operation. The generic code expects the platform
2239 If the Distributor, Redistributors or ITS have been powered off as part of a
2240 suspend, their context must be restored in this function in the reverse order
2241 to how they were saved during suspend sequence.
2243 plat_psci_ops.system_off()
2244 ..........................
2246 This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
2247 call. It performs the platform-specific system poweroff sequence after
2248 notifying the Secure Payload Dispatcher.
2250 plat_psci_ops.system_reset()
2251 ............................
2253 This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
2254 call. It performs the platform-specific system reset sequence after
2255 notifying the Secure Payload Dispatcher.
2257 plat_psci_ops.validate_power_state()
2258 ....................................
2260 This function is called by the PSCI implementation during the ``CPU_SUSPEND``
2261 call to validate the ``power_state`` parameter of the PSCI API and if valid,
2262 populate it in ``req_state`` (second argument) array as power domain level
2263 specific local states. If the ``power_state`` is invalid, the platform must
2264 return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
2265 normal world PSCI client.
2267 plat_psci_ops.validate_ns_entrypoint()
2268 ......................................
2270 This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
2271 ``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
2272 parameter passed by the normal world. If the ``entry_point`` is invalid,
2273 the platform must return PSCI_E_INVALID_ADDRESS as error, which is
2274 propagated back to the normal world PSCI client.
2276 plat_psci_ops.get_sys_suspend_power_state()
2277 ...........................................
2279 This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
2280 call to get the ``req_state`` parameter from platform which encodes the power
2281 domain level specific local states to suspend to system affinity level. The
2282 ``req_state`` will be utilized to do the PSCI state coordination and
2283 ``pwr_domain_suspend()`` will be invoked with the coordinated target state to
2284 enter system suspend.
2286 plat_psci_ops.get_pwr_lvl_state_idx()
2287 .....................................
2289 This is an optional function and, if implemented, is invoked by the PSCI
2290 implementation to convert the ``local_state`` (first argument) at a specified
2291 ``pwr_lvl`` (second argument) to an index between 0 and
2292 ``PLAT_MAX_PWR_LVL_STATES`` - 1. This function is only needed if the platform
2293 supports more than two local power states at each power domain level, that is
2294 ``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
2297 plat_psci_ops.translate_power_state_by_mpidr()
2298 ..............................................
2300 This is an optional function and, if implemented, verifies the ``power_state``
2301 (second argument) parameter of the PSCI API corresponding to a target power
2302 domain. The target power domain is identified by using both ``MPIDR`` (first
2303 argument) and the power domain level encoded in ``power_state``. The power domain
2304 level specific local states are to be extracted from ``power_state`` and be
2305 populated in the ``output_state`` (third argument) array. The functionality
2306 is similar to the ``validate_power_state`` function described above and is
2307 envisaged to be used in case the validity of ``power_state`` depend on the
2308 targeted power domain. If the ``power_state`` is invalid for the targeted power
2309 domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
2310 function is not implemented, then the generic implementation relies on
2311 ``validate_power_state`` function to translate the ``power_state``.
2313 This function can also be used in case the platform wants to support local
2314 power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
2315 APIs as described in Section 5.18 of `PSCI`_.
2317 plat_psci_ops.get_node_hw_state()
2318 .................................
2320 This is an optional function. If implemented this function is intended to return
2321 the power state of a node (identified by the first parameter, the ``MPIDR``) in
2322 the power domain topology (identified by the second parameter, ``power_level``),
2323 as retrieved from a power controller or equivalent component on the platform.
2324 Upon successful completion, the implementation must map and return the final
2325 status among ``HW_ON``, ``HW_OFF`` or ``HW_STANDBY``. Upon encountering failures, it
2326 must return either ``PSCI_E_INVALID_PARAMS`` or ``PSCI_E_NOT_SUPPORTED`` as
2329 Implementations are not expected to handle ``power_levels`` greater than
2330 ``PLAT_MAX_PWR_LVL``.
2332 plat_psci_ops.system_reset2()
2333 .............................
2335 This is an optional function. If implemented this function is
2336 called during the ``SYSTEM_RESET2`` call to perform a reset
2337 based on the first parameter ``reset_type`` as specified in
2338 `PSCI`_. The parameter ``cookie`` can be used to pass additional
2339 reset information. If the ``reset_type`` is not supported, the
2340 function must return ``PSCI_E_NOT_SUPPORTED``. For architectural
2341 resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
2342 and vendor reset can return other PSCI error codes as defined
2343 in `PSCI`_. On success this function will not return.
2345 plat_psci_ops.write_mem_protect()
2346 .................................
2348 This is an optional function. If implemented it enables or disables the
2349 ``MEM_PROTECT`` functionality based on the value of ``val``.
2350 A non-zero value enables ``MEM_PROTECT`` and a value of zero
2351 disables it. Upon encountering failures it must return a negative value
2352 and on success it must return 0.
2354 plat_psci_ops.read_mem_protect()
2355 ................................
2357 This is an optional function. If implemented it returns the current
2358 state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
2359 failures it must return a negative value and on success it must
2362 plat_psci_ops.mem_protect_chk()
2363 ...............................
2365 This is an optional function. If implemented it checks if a memory
2366 region defined by a base address ``base`` and with a size of ``length``
2367 bytes is protected by ``MEM_PROTECT``. If the region is protected
2368 then it must return 0, otherwise it must return a negative number.
2370 Interrupt Management framework (in BL31)
2371 ----------------------------------------
2373 BL31 implements an Interrupt Management Framework (IMF) to manage interrupts
2374 generated in either security state and targeted to EL1 or EL2 in the non-secure
2375 state or EL3/S-EL1 in the secure state. The design of this framework is
2376 described in the `IMF Design Guide`_
2378 A platform should export the following APIs to support the IMF. The following
2379 text briefly describes each API and its implementation in Arm standard
2380 platforms. The API implementation depends upon the type of interrupt controller
2381 present in the platform. Arm standard platform layer supports both
2382 `Arm Generic Interrupt Controller version 2.0 (GICv2)`_
2383 and `3.0 (GICv3)`_. Juno builds the Arm platform layer to use GICv2 and the
2384 FVP can be configured to use either GICv2 or GICv3 depending on the build flag
2385 ``FVP_USE_GIC_DRIVER`` (See FVP platform specific build options in
2386 `User Guide`_ for more details).
2388 See also: `Interrupt Controller Abstraction APIs`__.
2390 .. __: ../design/platform-interrupt-controller-API.rst
2392 Function : plat_interrupt_type_to_line() [mandatory]
2393 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2397 Argument : uint32_t, uint32_t
2400 The Arm processor signals an interrupt exception either through the IRQ or FIQ
2401 interrupt line. The specific line that is signaled depends on how the interrupt
2402 controller (IC) reports different interrupt types from an execution context in
2403 either security state. The IMF uses this API to determine which interrupt line
2404 the platform IC uses to signal each type of interrupt supported by the framework
2405 from a given security state. This API must be invoked at EL3.
2407 The first parameter will be one of the ``INTR_TYPE_*`` values (see
2408 `IMF Design Guide`_) indicating the target type of the interrupt, the second parameter is the
2409 security state of the originating execution context. The return result is the
2410 bit position in the ``SCR_EL3`` register of the respective interrupt trap: IRQ=1,
2413 In the case of Arm standard platforms using GICv2, S-EL1 interrupts are
2414 configured as FIQs and Non-secure interrupts as IRQs from either security
2417 In the case of Arm standard platforms using GICv3, the interrupt line to be
2418 configured depends on the security state of the execution context when the
2419 interrupt is signalled and are as follows:
2421 - The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in
2423 - The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ
2424 in the NS-EL0/1/2 context.
2425 - The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
2428 Function : plat_ic_get_pending_interrupt_type() [mandatory]
2429 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2436 This API returns the type of the highest priority pending interrupt at the
2437 platform IC. The IMF uses the interrupt type to retrieve the corresponding
2438 handler function. ``INTR_TYPE_INVAL`` is returned when there is no interrupt
2439 pending. The valid interrupt types that can be returned are ``INTR_TYPE_EL3``,
2440 ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``. This API must be invoked at EL3.
2442 In the case of Arm standard platforms using GICv2, the *Highest Priority
2443 Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of
2444 the pending interrupt. The type of interrupt depends upon the id value as
2447 #. id < 1022 is reported as a S-EL1 interrupt
2448 #. id = 1022 is reported as a Non-secure interrupt.
2449 #. id = 1023 is reported as an invalid interrupt type.
2451 In the case of Arm standard platforms using GICv3, the system register
2452 ``ICC_HPPIR0_EL1``, *Highest Priority Pending group 0 Interrupt Register*,
2453 is read to determine the id of the pending interrupt. The type of interrupt
2454 depends upon the id value as follows.
2456 #. id = ``PENDING_G1S_INTID`` (1020) is reported as a S-EL1 interrupt
2457 #. id = ``PENDING_G1NS_INTID`` (1021) is reported as a Non-secure interrupt.
2458 #. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
2459 #. All other interrupt id's are reported as EL3 interrupt.
2461 Function : plat_ic_get_pending_interrupt_id() [mandatory]
2462 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2469 This API returns the id of the highest priority pending interrupt at the
2470 platform IC. ``INTR_ID_UNAVAILABLE`` is returned when there is no interrupt
2473 In the case of Arm standard platforms using GICv2, the *Highest Priority
2474 Pending Interrupt Register* (``GICC_HPPIR``) is read to determine the id of the
2475 pending interrupt. The id that is returned by API depends upon the value of
2476 the id read from the interrupt controller as follows.
2478 #. id < 1022. id is returned as is.
2479 #. id = 1022. The *Aliased Highest Priority Pending Interrupt Register*
2480 (``GICC_AHPPIR``) is read to determine the id of the non-secure interrupt.
2481 This id is returned by the API.
2482 #. id = 1023. ``INTR_ID_UNAVAILABLE`` is returned.
2484 In the case of Arm standard platforms using GICv3, if the API is invoked from
2485 EL3, the system register ``ICC_HPPIR0_EL1``, *Highest Priority Pending Interrupt
2486 group 0 Register*, is read to determine the id of the pending interrupt. The id
2487 that is returned by API depends upon the value of the id read from the
2488 interrupt controller as follows.
2490 #. id < ``PENDING_G1S_INTID`` (1020). id is returned as is.
2491 #. id = ``PENDING_G1S_INTID`` (1020) or ``PENDING_G1NS_INTID`` (1021). The system
2492 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending Interrupt group 1
2493 Register* is read to determine the id of the group 1 interrupt. This id
2494 is returned by the API as long as it is a valid interrupt id
2495 #. If the id is any of the special interrupt identifiers,
2496 ``INTR_ID_UNAVAILABLE`` is returned.
2498 When the API invoked from S-EL1 for GICv3 systems, the id read from system
2499 register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
2500 Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
2501 ``INTR_ID_UNAVAILABLE`` is returned.
2503 Function : plat_ic_acknowledge_interrupt() [mandatory]
2504 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2511 This API is used by the CPU to indicate to the platform IC that processing of
2512 the highest pending interrupt has begun. It should return the raw, unmodified
2513 value obtained from the interrupt controller when acknowledging an interrupt.
2514 The actual interrupt number shall be extracted from this raw value using the API
2515 `plat_ic_get_interrupt_id()`__.
2517 .. __: ../design/platform-interrupt-controller-API.rst#function-unsigned-int-plat-ic-get-interrupt-id-unsigned-int-raw-optional
2519 This function in Arm standard platforms using GICv2, reads the *Interrupt
2520 Acknowledge Register* (``GICC_IAR``). This changes the state of the highest
2521 priority pending interrupt from pending to active in the interrupt controller.
2522 It returns the value read from the ``GICC_IAR``, unmodified.
2524 In the case of Arm standard platforms using GICv3, if the API is invoked
2525 from EL3, the function reads the system register ``ICC_IAR0_EL1``, *Interrupt
2526 Acknowledge Register group 0*. If the API is invoked from S-EL1, the function
2527 reads the system register ``ICC_IAR1_EL1``, *Interrupt Acknowledge Register
2528 group 1*. The read changes the state of the highest pending interrupt from
2529 pending to active in the interrupt controller. The value read is returned
2532 The TSP uses this API to start processing of the secure physical timer
2535 Function : plat_ic_end_of_interrupt() [mandatory]
2536 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2543 This API is used by the CPU to indicate to the platform IC that processing of
2544 the interrupt corresponding to the id (passed as the parameter) has
2545 finished. The id should be the same as the id returned by the
2546 ``plat_ic_acknowledge_interrupt()`` API.
2548 Arm standard platforms write the id to the *End of Interrupt Register*
2549 (``GICC_EOIR``) in case of GICv2, and to ``ICC_EOIR0_EL1`` or ``ICC_EOIR1_EL1``
2550 system register in case of GICv3 depending on where the API is invoked from,
2551 EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt
2554 The TSP uses this API to finish processing of the secure physical timer
2557 Function : plat_ic_get_interrupt_type() [mandatory]
2558 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2565 This API returns the type of the interrupt id passed as the parameter.
2566 ``INTR_TYPE_INVAL`` is returned if the id is invalid. If the id is valid, a valid
2567 interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1`` and ``INTR_TYPE_NS``) is
2568 returned depending upon how the interrupt has been configured by the platform
2569 IC. This API must be invoked at EL3.
2571 Arm standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts
2572 and Non-secure interrupts as Group1 interrupts. It reads the group value
2573 corresponding to the interrupt id from the relevant *Interrupt Group Register*
2574 (``GICD_IGROUPRn``). It uses the group value to determine the type of interrupt.
2576 In the case of Arm standard platforms using GICv3, both the *Interrupt Group
2577 Register* (``GICD_IGROUPRn``) and *Interrupt Group Modifier Register*
2578 (``GICD_IGRPMODRn``) is read to figure out whether the interrupt is configured
2579 as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt.
2581 Crash Reporting mechanism (in BL31)
2582 -----------------------------------
2584 BL31 implements a crash reporting mechanism which prints the various registers
2585 of the CPU to enable quick crash analysis and debugging. This mechanism relies
2586 on the platform implementing ``plat_crash_console_init``,
2587 ``plat_crash_console_putc`` and ``plat_crash_console_flush``.
2589 The file ``plat/common/aarch64/crash_console_helpers.S`` contains sample
2590 implementation of all of them. Platforms may include this file to their
2591 makefiles in order to benefit from them. By default, they will cause the crash
2592 output to be routed over the normal console infrastructure and get printed on
2593 consoles configured to output in crash state. ``console_set_scope()`` can be
2594 used to control whether a console is used for crash output.
2597 Platforms are responsible for making sure that they only mark consoles for
2598 use in the crash scope that are able to support this, i.e. that are written
2599 in assembly and conform with the register clobber rules for putc()
2600 (x0-x2, x16-x17) and flush() (x0-x3, x16-x17) crash callbacks.
2602 In some cases (such as debugging very early crashes that happen before the
2603 normal boot console can be set up), platforms may want to control crash output
2604 more explicitly. These platforms may instead provide custom implementations for
2605 these. They are executed outside of a C environment and without a stack. Many
2606 console drivers provide functions named ``console_xxx_core_init/putc/flush``
2607 that are designed to be used by these functions. See Arm platforms (like juno)
2608 for an example of this.
2610 Function : plat_crash_console_init [mandatory]
2611 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2618 This API is used by the crash reporting mechanism to initialize the crash
2619 console. It must only use the general purpose registers x0 through x7 to do the
2620 initialization and returns 1 on success.
2622 Function : plat_crash_console_putc [mandatory]
2623 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2630 This API is used by the crash reporting mechanism to print a character on the
2631 designated crash console. It must only use general purpose registers x1 and
2632 x2 to do its work. The parameter and the return value are in general purpose
2635 Function : plat_crash_console_flush [mandatory]
2636 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2643 This API is used by the crash reporting mechanism to force write of all buffered
2644 data on the designated crash console. It should only use general purpose
2645 registers x0 through x5 to do its work. The return value is 0 on successful
2646 completion; otherwise the return value is -1.
2648 External Abort handling and RAS Support
2649 ---------------------------------------
2651 Function : plat_ea_handler
2652 ~~~~~~~~~~~~~~~~~~~~~~~~~~
2663 This function is invoked by the RAS framework for the platform to handle an
2664 External Abort received at EL3. The intention of the function is to attempt to
2665 resolve the cause of External Abort and return; if that's not possible, to
2666 initiate orderly shutdown of the system.
2668 The first parameter (``int ea_reason``) indicates the reason for External Abort.
2669 Its value is one of ``ERROR_EA_*`` constants defined in ``ea_handle.h``.
2671 The second parameter (``uint64_t syndrome``) is the respective syndrome
2672 presented to EL3 after having received the External Abort. Depending on the
2673 nature of the abort (as can be inferred from the ``ea_reason`` parameter), this
2674 can be the content of either ``ESR_EL3`` or ``DISR_EL1``.
2676 The third parameter (``void *cookie``) is unused for now. The fourth parameter
2677 (``void *handle``) is a pointer to the preempted context. The fifth parameter
2678 (``uint64_t flags``) indicates the preempted security state. These parameters
2679 are received from the top-level exception handler.
2681 If ``RAS_EXTENSION`` is set to ``1``, the default implementation of this
2682 function iterates through RAS handlers registered by the platform. If any of the
2683 RAS handlers resolve the External Abort, no further action is taken.
2685 If ``RAS_EXTENSION`` is set to ``0``, or if none of the platform RAS handlers
2686 could resolve the External Abort, the default implementation prints an error
2687 message, and panics.
2689 Function : plat_handle_uncontainable_ea
2690 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2698 This function is invoked by the RAS framework when an External Abort of
2699 Uncontainable type is received at EL3. Due to the critical nature of
2700 Uncontainable errors, the intention of this function is to initiate orderly
2701 shutdown of the system, and is not expected to return.
2703 This function must be implemented in assembly.
2705 The first and second parameters are the same as that of ``plat_ea_handler``.
2707 The default implementation of this function calls
2708 ``report_unhandled_exception``.
2710 Function : plat_handle_double_fault
2711 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2719 This function is invoked by the RAS framework when another External Abort is
2720 received at EL3 while one is already being handled. I.e., a call to
2721 ``plat_ea_handler`` is outstanding. Due to its critical nature, the intention of
2722 this function is to initiate orderly shutdown of the system, and is not expected
2725 This function must be implemented in assembly.
2727 The first and second parameters are the same as that of ``plat_ea_handler``.
2729 The default implementation of this function calls
2730 ``report_unhandled_exception``.
2732 Function : plat_handle_el3_ea
2733 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2739 This function is invoked when an External Abort is received while executing in
2740 EL3. Due to its critical nature, the intention of this function is to initiate
2741 orderly shutdown of the system, and is not expected recover or return.
2743 This function must be implemented in assembly.
2745 The default implementation of this function calls
2746 ``report_unhandled_exception``.
2751 There are some build flags which can be defined by the platform to control
2752 inclusion or exclusion of certain BL stages from the FIP image. These flags
2753 need to be defined in the platform makefile which will get included by the
2757 By default, this flag is defined ``yes`` by the build system and ``BL33``
2758 build option should be supplied as a build option. The platform has the
2759 option of excluding the BL33 image in the ``fip`` image by defining this flag
2760 to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
2761 are used, this flag will be set to ``no`` automatically.
2766 To avoid subtle toolchain behavioral dependencies, the header files provided
2767 by the compiler are not used. The software is built with the ``-nostdinc`` flag
2768 to ensure no headers are included from the toolchain inadvertently. Instead the
2769 required headers are included in the TF-A source tree. The library only
2770 contains those C library definitions required by the local implementation. If
2771 more functionality is required, the needed library functions will need to be
2772 added to the local implementation.
2774 Some C headers have been obtained from `FreeBSD`_ and `SCC`_, while others have
2775 been written specifically for TF-A. Fome implementation files have been obtained
2776 from `FreeBSD`_, others have been written specifically for TF-A as well. The
2777 files can be found in ``include/lib/libc`` and ``lib/libc``.
2779 SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
2780 can be obtained from http://github.com/freebsd/freebsd.
2782 Storage abstraction layer
2783 -------------------------
2785 In order to improve platform independence and portability a storage abstraction
2786 layer is used to load data from non-volatile platform storage. Currently
2787 storage access is only required by BL1 and BL2 phases and performed inside the
2788 ``load_image()`` function in ``bl_common.c``.
2790 .. uml:: ../resources/diagrams/plantuml/io_framework_usage_overview.puml
2792 It is mandatory to implement at least one storage driver. For the Arm
2793 development platforms the Firmware Image Package (FIP) driver is provided as
2794 the default means to load data from storage (see the "Firmware Image Package"
2795 section in the `User Guide`_). The storage layer is described in the header file
2796 ``include/drivers/io/io_storage.h``. The implementation of the common library
2797 is in ``drivers/io/io_storage.c`` and the driver files are located in
2800 .. uml:: ../resources/diagrams/plantuml/io_arm_class_diagram.puml
2802 Each IO driver must provide ``io_dev_*`` structures, as described in
2803 ``drivers/io/io_driver.h``. These are returned via a mandatory registration
2804 function that is called on platform initialization. The semi-hosting driver
2805 implementation in ``io_semihosting.c`` can be used as an example.
2807 Each platform should register devices and their drivers via the storage
2808 abstraction layer. These drivers then need to be initialized by bootloader
2809 phases as required in their respective ``blx_platform_setup()`` functions.
2811 .. uml:: ../resources/diagrams/plantuml/io_dev_registration.puml
2813 The storage abstraction layer provides mechanisms (``io_dev_init()``) to
2814 initialize storage devices before IO operations are called.
2816 .. uml:: ../resources/diagrams/plantuml/io_dev_init_and_check.puml
2818 The basic operations supported by the layer
2819 include ``open()``, ``close()``, ``read()``, ``write()``, ``size()`` and ``seek()``.
2820 Drivers do not have to implement all operations, but each platform must
2821 provide at least one driver for a device capable of supporting generic
2822 operations such as loading a bootloader image.
2824 The current implementation only allows for known images to be loaded by the
2825 firmware. These images are specified by using their identifiers, as defined in
2826 ``include/plat/common/common_def.h`` (or a separate header file included from
2827 there). The platform layer (``plat_get_image_source()``) then returns a reference
2828 to a device and a driver-specific ``spec`` which will be understood by the driver
2829 to allow access to the image data.
2831 The layer is designed in such a way that is it possible to chain drivers with
2832 other drivers. For example, file-system drivers may be implemented on top of
2833 physical block devices, both represented by IO devices with corresponding
2834 drivers. In such a case, the file-system "binding" with the block device may
2835 be deferred until the file-system device is initialised.
2837 The abstraction currently depends on structures being statically allocated
2838 by the drivers and callers, as the system does not yet provide a means of
2839 dynamically allocating memory. This may also have the affect of limiting the
2840 amount of open resources per driver.
2844 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
2846 .. _include/plat/common/platform.h: ../include/plat/common/platform.h
2847 .. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D
2848 .. _User Guide: user-guide.rst
2849 .. _include/plat/common/common_def.h: ../include/plat/common/common_def.h
2850 .. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h
2851 .. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S
2852 .. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S
2853 .. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160
2854 .. _Power Domain Topology Design: ../design/psci-pd-tree.rst
2855 .. _include/common/bl_common.h: ../include/common/bl_common.h
2856 .. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h
2857 .. _Firmware Design: ../design/firmware-design.rst
2858 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
2859 .. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c
2860 .. _Platform compatibility policy: ../process/platform-compatibility-policy.rst
2861 .. _IMF Design Guide: ../design/interrupt-framework-design.rst
2862 .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
2863 .. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
2864 .. _FreeBSD: https://www.freebsd.org
2865 .. _SCC: http://www.simple-cc.org/