4 This document describes how to build Trusted Firmware-A (TF-A) and run it with a
5 tested set of other software components using defined configurations on the Juno
6 Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
7 possible to use other software components, configurations and platforms but that
8 is outside the scope of this document.
10 This document assumes that the reader has previous experience running a fully
11 bootable Linux software stack on Juno or FVP using the prebuilt binaries and
12 filesystems provided by Linaro. Further information may be found in the
13 `Linaro instructions`_. It also assumes that the user understands the role of
14 the different software components required to boot a Linux system:
16 - Specific firmware images required by the platform (e.g. SCP firmware on Juno)
17 - Normal world bootloader (e.g. UEFI or U-Boot)
22 This document also assumes that the user is familiar with the `FVP models`_ and
23 the different command line options available to launch the model.
25 This document should be used in conjunction with the `Firmware Design`_.
27 Host machine requirements
28 -------------------------
30 The minimum recommended machine specification for building the software and
31 running the FVP models is a dual-core processor running at 2GHz with 12GB of
32 RAM. For best performance, use a machine with a quad-core processor running at
33 2.6GHz with 16GB of RAM.
35 The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
36 building the software were installed from that distribution unless otherwise
39 The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
40 Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
45 Install the required packages to build TF-A with the following command:
49 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
51 Download and install the AArch32 (arm-eabi) or AArch64 little-endian
52 (aarch64-linux-gnu) GCC 8.3-2019.03 cross compiler from `Arm Developer page`_.
54 Optionally, TF-A can be built using clang version 4.0 or newer or Arm
55 Compiler 6. See instructions below on how to switch the default compiler.
57 In addition, the following optional packages and tools may be needed:
59 - ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
60 Tree (FDT) source files (``.dts`` files) provided with this software. The
61 version of dtc must be 1.4.6 or above.
63 - For debugging, Arm `Development Studio 5 (DS-5)`_.
65 - To create and modify the diagram files included in the documentation, `Dia`_.
66 This tool can be found in most Linux distributions. Inkscape is needed to
67 generate the actual \*.png files.
69 TF-A has been tested with pre-built binaries and file systems from
70 `Linaro Release 19.06`_. Alternatively, you can build the binaries from
71 source using instructions provided at the `Arm Platforms User guide`_.
73 Getting the TF-A source code
74 ----------------------------
76 Clone the repository from the Gerrit server. The project details may be found
77 on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
78 commit-msg hook`" clone method, which will setup the git commit hook that
79 automatically generates and inserts appropriate `Change-Id:` lines in your
82 Checking source code style
83 ~~~~~~~~~~~~~~~~~~~~~~~~~~
85 Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
86 source, for submission to the project, the source must be in compliance with
89 Additional, project-specific guidelines are defined in the `Trusted Firmware-A
90 Coding Guidelines`_ document.
92 To assist with coding style compliance, the project Makefile contains two
93 targets which both utilise the `checkpatch.pl` script that ships with the Linux
94 source tree. The project also defines certain *checkpatch* options in the
95 ``.checkpatch.conf`` file in the top-level directory.
98 Checkpatch errors will gate upstream merging of pull requests.
99 Checkpatch warnings will not gate merging but should be reviewed and fixed if
102 To check the entire source tree, you must first download copies of
103 ``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
104 in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
105 environment variable to point to ``checkpatch.pl`` (with the other 2 files in
106 the same directory) and build the `checkcodebase` target:
110 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
112 To just check the style on the files that differ between your local branch and
113 the remote master, use:
117 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
119 If you wish to check your patch against something other than the remote master,
120 set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
121 is set to ``origin/master``.
126 - Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
127 to the cross compiler.
133 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
139 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
141 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
142 ``CC`` needs to point to the clang or armclang binary, which will
143 also select the clang or armclang assembler. Be aware that the
144 GNU linker is used by default. In case of being needed the linker
145 can be overridden using the ``LD`` variable. Clang linker version 6 is
146 known to work with TF-A.
148 In both cases ``CROSS_COMPILE`` should be set as described above.
150 Arm Compiler 6 will be selected when the base name of the path assigned
151 to ``CC`` matches the string 'armclang'.
153 For AArch64 using Arm Compiler 6:
157 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
158 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
160 Clang will be selected when the base name of the path assigned to ``CC``
161 contains the string 'clang'. This is to allow both clang and clang-X.Y
164 For AArch64 using clang:
168 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
169 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
171 - Change to the root directory of the TF-A source tree and build.
177 make PLAT=<platform> all
183 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
187 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
188 `Summary of build options`_ for more information on available build
191 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
193 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
194 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
195 provided by TF-A to demonstrate how PSCI Library can be integrated with
196 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
197 include other runtime services, for example Trusted OS services. A guide
198 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
201 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
202 image, is not compiled in by default. Refer to the
203 `Building the Test Secure Payload`_ section below.
205 - By default this produces a release version of the build. To produce a
206 debug version instead, refer to the "Debugging options" section below.
208 - The build process creates products in a ``build`` directory tree, building
209 the objects and binaries for each boot loader stage in separate
210 sub-directories. The following boot loader binary files are created
211 from the corresponding ELF files:
213 - ``build/<platform>/<build-type>/bl1.bin``
214 - ``build/<platform>/<build-type>/bl2.bin``
215 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
216 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
218 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
219 is either ``debug`` or ``release``. The actual number of images might differ
220 depending on the platform.
222 - Build products for a specific build variant can be removed using:
226 make DEBUG=<D> PLAT=<platform> clean
228 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
230 The build tree can be removed completely using:
236 Summary of build options
237 ~~~~~~~~~~~~~~~~~~~~~~~~
239 The TF-A build system supports the following build options. Unless mentioned
240 otherwise, these options are expected to be specified at the build command
241 line and are not to be modified in any component makefiles. Note that the
242 build system doesn't track dependency for build options. Therefore, if any of
243 the build options are changed from a previous build, a clean build must be
249 - ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
250 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
251 code having a smaller resulting size.
253 - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
254 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
255 directory containing the SP source, relative to the ``bl32/``; the directory
256 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
258 - ``ARCH`` : Choose the target build architecture for TF-A. It can take either
259 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
262 - ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
263 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
264 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
267 - ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
268 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
269 *Armv8 Architecture Extensions* in `Firmware Design`_.
271 - ``BL2``: This is an optional build option which specifies the path to BL2
272 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
275 - ``BL2U``: This is an optional build option which specifies the path to
276 BL2U image. In this case, the BL2U in TF-A will not be built.
278 - ``BL2_AT_EL3``: This is an optional build option that enables the use of
279 BL2 at EL3 execution level.
281 - ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
282 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
283 the RW sections in RAM, while leaving the RO sections in place. This option
284 enable this use-case. For now, this option is only supported when BL2_AT_EL3
287 - ``BL2_INV_DCACHE``: This is an optional build option which control dcache
288 invalidation upon BL2 entry. Some platform cannot handle cache operations
289 during entry as the coherency unit is not yet initialized. This may cause
290 crashing. Leaving this option to '1' (default) will allow the operation.
291 This option is only relevant when BL2_AT_EL3 is set to '1'.
293 - ``BL31``: This is an optional build option which specifies the path to
294 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
297 - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
298 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
299 this file name will be used to save the key.
301 - ``BL32``: This is an optional build option which specifies the path to
302 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
305 - ``BL32_EXTRA1``: This is an optional build option which specifies the path to
306 Trusted OS Extra1 image for the ``fip`` target.
308 - ``BL32_EXTRA2``: This is an optional build option which specifies the path to
309 Trusted OS Extra2 image for the ``fip`` target.
311 - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
312 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
313 this file name will be used to save the key.
315 - ``BL33``: Path to BL33 image in the host file system. This is mandatory for
316 ``fip`` target in case TF-A BL2 is used.
318 - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
319 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
320 this file name will be used to save the key.
322 - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
323 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
324 If enabled, it is needed to use a compiler (e.g GCC 9.1 and later versions) that
325 supports the option ``-mbranch-protection``.
326 Selects the branch protection features to use:
327 - 0: Default value turns off all types of branch protection
328 - 1: Enables all types of branch protection features
329 - 2: Return address signing to its standard level
330 - 3: Extend the signing to include leaf functions
332 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
333 and resulting PAuth/BTI features.
335 +-------+--------------+-------+-----+
336 | Value | GCC option | PAuth | BTI |
337 +=======+==============+=======+=====+
339 +-------+--------------+-------+-----+
340 | 1 | standard | Y | Y |
341 +-------+--------------+-------+-----+
342 | 2 | pac-ret | Y | N |
343 +-------+--------------+-------+-----+
344 | 3 | pac-ret+leaf | Y | N |
345 +-------+--------------+-------+-----+
347 This option defaults to 0 and this is an experimental feature.
348 Note that Pointer Authentication is enabled for Non-secure world
349 irrespective of the value of this option if the CPU supports it.
351 - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
352 compilation of each build. It must be set to a C string (including quotes
353 where applicable). Defaults to a string that contains the time and date of
356 - ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
357 build to be uniquely identified. Defaults to the current git commit id.
359 - ``CFLAGS``: Extra user options appended on the compiler's command line in
360 addition to the options set by the build system.
362 - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
363 release several CPUs out of reset. It can take either 0 (several CPUs may be
364 brought up) or 1 (only one CPU will ever be brought up during cold reset).
365 Default is 0. If the platform always brings up a single CPU, there is no
366 need to distinguish between primary and secondary CPUs and the boot path can
367 be optimised. The ``plat_is_my_cpu_primary()`` and
368 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
369 to be implemented in this case.
371 - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
372 register state when an unexpected exception occurs during execution of
373 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
374 this is only enabled for a debug build of the firmware.
376 - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
377 certificate generation tool to create new keys in case no valid keys are
378 present or specified. Allowed options are '0' or '1'. Default is '1'.
380 - ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
381 the AArch32 system registers to be included when saving and restoring the
382 CPU context. The option must be set to 0 for AArch64-only platforms (that
383 is on hardware that does not implement AArch32, or at least not at EL1 and
384 higher ELs). Default value is 1.
386 - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
387 registers to be included when saving and restoring the CPU context. Default
390 - ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
391 ARMv8.5 Memory Tagging Extension. A value of 0 will disable
392 saving/reloading and restrict the use of MTE to the normal world if the
393 CPU has support, while a value of 1 enables the saving/reloading, allowing
394 the use of MTE in both the secure and non-secure worlds. Default is 0
395 (disabled) and this feature is experimental.
397 - ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
398 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
399 registers to be included when saving and restoring the CPU context as
400 part of world switch. Default value is 0 and this is an experimental feature.
401 Note that Pointer Authentication is enabled for Non-secure world irrespective
402 of the value of this flag if the CPU supports it.
404 - ``DEBUG``: Chooses between a debug and release build. It can take either 0
405 (release) or 1 (debug) as values. 0 is the default.
407 - ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
408 of the binary image. If set to 1, then only the ELF image is built.
411 - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
412 Board Boot authentication at runtime. This option is meant to be enabled only
413 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
414 flag has to be enabled. 0 is the default.
416 - ``E``: Boolean option to make warnings into errors. Default is 1.
418 - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
419 the normal boot flow. It must specify the entry point address of the EL3
420 payload. Please refer to the "Booting an EL3 payload" section for more
423 - ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
424 This is an optional architectural feature available on v8.4 onwards. Some
425 v8.2 implementations also implement an AMU and this option can be used to
426 enable this feature on those systems as well. Default is 0.
428 - ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
429 are compiled out. For debug builds, this option defaults to 1, and calls to
430 ``assert()`` are left in place. For release builds, this option defaults to 0
431 and calls to ``assert()`` function are compiled out. This option can be set
432 independently of ``DEBUG``. It can also be used to hide any auxiliary code
433 that is only required for the assertion and does not fit in the assertion
436 - ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
437 dumps or not. It is supported in both AArch64 and AArch32. However, in
438 AArch32 the format of the frame records are not defined in the AAPCS and they
439 are defined by the implementation. This implementation of backtrace only
440 supports the format used by GCC when T32 interworking is disabled. For this
441 reason enabling this option in AArch32 will force the compiler to only
442 generate A32 code. This option is enabled by default only in AArch64 debug
443 builds, but this behaviour can be overridden in each platform's Makefile or
444 in the build command line.
446 - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
447 feature. MPAM is an optional Armv8.4 extension that enables various memory
448 system components and resources to define partitions; software running at
449 various ELs can assign themselves to desired partition to control their
452 When this option is set to ``1``, EL3 allows lower ELs to access their own
453 MPAM registers without trapping into EL3. This option doesn't make use of
454 partitioning in EL3, however. Platform initialisation code should configure
455 and use partitions in EL3 as required. This option defaults to ``0``.
457 - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
458 support within generic code in TF-A. This option is currently only supported
459 in BL31. Default is 0.
461 - ``ENABLE_PMF``: Boolean option to enable support for optional Performance
462 Measurement Framework(PMF). Default is 0.
464 - ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
465 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
466 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
467 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
470 - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
471 instrumentation which injects timestamp collection points into TF-A to
472 allow runtime performance to be measured. Currently, only PSCI is
473 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
474 as well. Default is 0.
476 - ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
477 extensions. This is an optional architectural feature for AArch64.
478 The default is 1 but is automatically disabled when the target architecture
481 - ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
482 Refer to the `Secure Partition Manager Design guide`_ for more details about
483 this feature. Default is 0.
485 - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
486 (SVE) for the Non-secure world only. SVE is an optional architectural feature
487 for AArch64. Note that when SVE is enabled for the Non-secure world, access
488 to SIMD and floating-point functionality from the Secure world is disabled.
489 This is to avoid corruption of the Non-secure world data in the Z-registers
490 which are aliased by the SIMD and FP registers. The build option is not
491 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
492 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
493 1. The default is 1 but is automatically disabled when the target
494 architecture is AArch32.
496 - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
497 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
498 default value is set to "none". "strong" is the recommended stack protection
499 level if this feature is desired. "none" disables the stack protection. For
500 all values other than "none", the ``plat_get_stack_protector_canary()``
501 platform hook needs to be implemented. The value is passed as the last
502 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
504 - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
505 deprecated platform APIs, helper functions or drivers within Trusted
506 Firmware as error. It can take the value 1 (flag the use of deprecated
507 APIs as error) or 0. The default is 0.
509 - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
510 targeted at EL3. When set ``0`` (default), no exceptions are expected or
511 handled at EL3, and a panic will result. This is supported only for AArch64
514 - ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
515 injection from lower ELs, and this build option enables lower ELs to use
516 Error Records accessed via System Registers to inject faults. This is
517 applicable only to AArch64 builds.
519 This feature is intended for testing purposes only, and is advisable to keep
520 disabled for production images.
522 - ``FIP_NAME``: This is an optional build option which specifies the FIP
523 filename for the ``fip`` target. Default is ``fip.bin``.
525 - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
526 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
528 - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
529 tool to create certificates as per the Chain of Trust described in
530 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
531 include the certificates in the FIP and FWU_FIP. Default value is '0'.
533 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
534 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
535 the corresponding certificates, and to include those certificates in the
538 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
539 images will not include support for Trusted Board Boot. The FIP will still
540 include the corresponding certificates. This FIP can be used to verify the
541 Chain of Trust on the host machine through other mechanisms.
543 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
544 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
545 will not include the corresponding certificates, causing a boot failure.
547 - ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
548 inherent support for specific EL3 type interrupts. Setting this build option
549 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
550 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
551 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
552 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
553 the Secure Payload interrupts needs to be synchronously handed over to Secure
554 EL1 for handling. The default value of this option is ``0``, which means the
555 Group 0 interrupts are assumed to be handled by Secure EL1.
557 .. __: `platform-interrupt-controller-API.rst`
558 .. __: `interrupt-framework-design.rst`
560 - ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
561 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
562 ``0`` (default), these exceptions will be trapped in the current exception
563 level (or in EL1 if the current exception level is EL0).
565 - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
566 software operations are required for CPUs to enter and exit coherency.
567 However, newer systems exist where CPUs' entry to and exit from coherency
568 is managed in hardware. Such systems require software to only initiate these
569 operations, and the rest is managed in hardware, minimizing active software
570 management. In such systems, this boolean option enables TF-A to carry out
571 build and run-time optimizations during boot and power management operations.
572 This option defaults to 0 and if it is enabled, then it implies
573 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
575 If this flag is disabled while the platform which TF-A is compiled for
576 includes cores that manage coherency in hardware, then a compilation error is
577 generated. This is based on the fact that a system cannot have, at the same
578 time, cores that manage coherency in hardware and cores that don't. In other
579 words, a platform cannot have, at the same time, cores that require
580 ``HW_ASSISTED_COHERENCY=1`` and cores that require
581 ``HW_ASSISTED_COHERENCY=0``.
583 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
584 translation library (xlat tables v2) must be used; version 1 of translation
585 library is not supported.
587 - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
588 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
589 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
590 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
593 - ``KEY_ALG``: This build flag enables the user to select the algorithm to be
594 used for generating the PKCS keys and subsequent signing of the certificate.
595 It accepts 2 values: ``rsa`` and ``ecdsa``. The default value of this flag
596 is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
598 - ``KEY_SIZE``: This build flag enables the user to select the key size for
599 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
600 depend on the chosen algorithm.
602 +-----------+------------------------------------+
603 | KEY_ALG | Possible key sizes |
604 +===========+====================================+
605 | rsa | 1024, 2048 (default), 3072, 4096 |
606 +-----------+------------------------------------+
607 | ecdsa | unavailable |
608 +-----------+------------------------------------+
610 - ``HASH_ALG``: This build flag enables the user to select the secure hash
611 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
612 The default value of this flag is ``sha256``.
614 - ``LDFLAGS``: Extra user options appended to the linkers' command line in
615 addition to the one set by the build system.
617 - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
618 output compiled into the build. This should be one of the following:
624 20 (LOG_LEVEL_NOTICE)
625 30 (LOG_LEVEL_WARNING)
627 50 (LOG_LEVEL_VERBOSE)
629 All log output up to and including the selected log level is compiled into
630 the build. The default value is 40 in debug builds and 20 in release builds.
632 - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
633 specifies the file that contains the Non-Trusted World private key in PEM
634 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
636 - ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
637 optional. It is only needed if the platform makefile specifies that it
638 is required in order to build the ``fwu_fip`` target.
640 - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
641 contents upon world switch. It can take either 0 (don't save and restore) or
642 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
643 wants the timer registers to be saved and restored.
645 - ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
646 for the BL image. It can be either 0 (include) or 1 (remove). The default
649 - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
650 the underlying hardware is not a full PL011 UART but a minimally compliant
651 generic UART, which is a subset of the PL011. The driver will not access
652 any register that is not part of the SBSA generic UART specification.
653 Default value is 0 (a full PL011 compliant UART is present).
655 - ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
656 must be subdirectory of any depth under ``plat/``, and must contain a
657 platform makefile named ``platform.mk``. For example, to build TF-A for the
658 Arm Juno board, select PLAT=juno.
660 - ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
661 instead of the normal boot flow. When defined, it must specify the entry
662 point address for the preloaded BL33 image. This option is incompatible with
663 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
664 over ``PRELOADED_BL33_BASE``.
666 - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
667 vector address can be programmed or is fixed on the platform. It can take
668 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
669 programmable reset address, it is expected that a CPU will start executing
670 code directly at the right address, both on a cold and warm reset. In this
671 case, there is no need to identify the entrypoint on boot and the boot path
672 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
673 does not need to be implemented in this case.
675 - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
676 possible for the PSCI power-state parameter: original and extended State-ID
677 formats. This flag if set to 1, configures the generic PSCI layer to use the
678 extended format. The default value of this flag is 0, which means by default
679 the original power-state format is used by the PSCI implementation. This flag
680 should be specified by the platform makefile and it governs the return value
681 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
682 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
685 - ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
686 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
689 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
692 This option is disabled by default.
694 - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
695 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
696 entrypoint) or 1 (CPU reset to BL31 entrypoint).
697 The default value is 0.
699 - ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
700 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
701 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
702 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
704 - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
705 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
706 file name will be used to save the key.
708 - ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It
709 can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap',
710 gcc and clang will insert calls to ``__builtin_trap`` on detected
711 undefined behaviour, which defaults to a ``brk`` instruction. When using
712 'on', undefined behaviour is translated to a call to special handlers which
713 prints the exact location of the problem and its cause and then panics.
716 Because of the space penalty of the Undefined Behaviour sanitizer,
717 this option will increase the size of the binary. Depending on the
718 memory constraints of the target platform, it may not be possible to
719 enable the sanitizer for all images (BL1 and BL2 are especially
720 likely to be memory constrained). We recommend that the
721 sanitizer is enabled only in debug builds.
723 - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
724 certificate generation tool to save the keys used to establish the Chain of
725 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
727 - ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
728 If a SCP_BL2 image is present then this option must be passed for the ``fip``
731 - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
732 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
733 this file name will be used to save the key.
735 - ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
736 optional. It is only needed if the platform makefile specifies that it
737 is required in order to build the ``fwu_fip`` target.
739 - ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
740 Delegated Exception Interface to BL31 image. This defaults to ``0``.
742 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
745 - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
746 isolated on separate memory pages. This is a trade-off between security and
747 memory usage. See "Isolating code and read-only data on separate memory
748 pages" section in `Firmware Design`_. This flag is disabled by default and
749 affects all BL images.
751 - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
752 This build option is only valid if ``ARCH=aarch64``. The value should be
753 the path to the directory containing the SPD source, relative to
754 ``services/spd/``; the directory is expected to contain a makefile called
757 - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
758 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
759 execution in BL1 just before handing over to BL31. At this point, all
760 firmware images have been loaded in memory, and the MMU and caches are
761 turned off. Refer to the "Debugging options" section for more details.
763 - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
764 secure interrupts (caught through the FIQ line). Platforms can enable
765 this directive if they need to handle such interruption. When enabled,
766 the FIQ are handled in monitor mode and non secure world is not allowed
767 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
768 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
770 - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
771 Boot feature. When set to '1', BL1 and BL2 images include support to load
772 and verify the certificates and images in a FIP, and BL1 includes support
773 for the Firmware Update. The default value is '0'. Generation and inclusion
774 of certificates in the FIP and FWU_FIP depends upon the value of the
775 ``GENERATE_COT`` option.
778 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
779 already exist in disk, they will be overwritten without further notice.
781 - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
782 specifies the file that contains the Trusted World private key in PEM
783 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
785 - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
786 synchronous, (see "Initializing a BL32 Image" section in
787 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
788 synchronous method) or 1 (BL32 is initialized using asynchronous method).
791 - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
792 routing model which routes non-secure interrupts asynchronously from TSP
793 to EL3 causing immediate preemption of TSP. The EL3 is responsible
794 for saving and restoring the TSP context in this routing model. The
795 default routing model (when the value is 0) is to route non-secure
796 interrupts to TSP allowing it to save its context and hand over
797 synchronously to EL3 via an SMC.
800 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
801 must also be set to ``1``.
803 - ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
804 linker. When the ``LINKER`` build variable points to the armlink linker,
805 this flag is enabled automatically. To enable support for armlink, platforms
806 will have to provide a scatter file for the BL image. Currently, Tegra
807 platforms use the armlink support to compile BL3-1 images.
809 - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
810 memory region in the BL memory map or not (see "Use of Coherent memory in
811 TF-A" section in `Firmware Design`_). It can take the value 1
812 (Coherent memory region is included) or 0 (Coherent memory region is
813 excluded). Default is 1.
815 - ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
816 This feature creates a library of functions to be placed in ROM and thus
817 reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default
820 - ``USE_SPINLOCK_CAS``: Setting this build flag to 1 selects the spinlock
821 implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
822 Notice this option is experimental and only available to AArch64 builds.
824 - ``V``: Verbose build. If assigned anything other than 0, the build commands
825 are printed. Default is 0.
827 - ``VERSION_STRING``: String used in the log output for each TF-A image.
828 Defaults to a string formed by concatenating the version number, build type
831 - ``W``: Warning level. Some compiler warning options of interest have been
832 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
833 each level enabling more warning options. Default is 0.
835 - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
836 the CPU after warm boot. This is applicable for platforms which do not
837 require interconnect programming to enable cache coherency (eg: single
838 cluster platforms). If this option is enabled, then warm boot path
839 enables D-caches immediately after enabling MMU. This option defaults to 0.
841 Arm development platform specific build options
842 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
844 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
845 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
846 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
847 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
850 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
851 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
852 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
853 match the frame used by the Non-Secure image (normally the Linux kernel).
854 Default is true (access to the frame is allowed).
856 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
857 By default, Arm platforms use a watchdog to trigger a system reset in case
858 an error is encountered during the boot process (for example, when an image
859 could not be loaded or authenticated). The watchdog is enabled in the early
860 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
861 Trusted Watchdog may be disabled at build time for testing or development
864 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
865 have specific values at boot. This boolean option allows the Trusted Firmware
866 to have a Linux kernel image as BL33 by preparing the registers to these
867 values before jumping to BL33. This option defaults to 0 (disabled). For
868 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
869 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
870 to the location of a device tree blob (DTB) already loaded in memory. The
871 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
874 - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
875 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
876 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
877 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
878 this flag is 0. Note that this option is not used on FVP platforms.
880 - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
881 for the construction of composite state-ID in the power-state parameter.
882 The existing PSCI clients currently do not support this encoding of
883 State-ID yet. Hence this flag is used to configure whether to use the
884 recommended State-ID encoding or not. The default value of this flag is 0,
885 in which case the platform is configured to expect NULL in the State-ID
886 field of power-state parameter.
888 - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
889 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
890 for Arm platforms. Depending on the selected option, the proper private key
891 must be specified using the ``ROT_KEY`` option when building the Trusted
892 Firmware. This private key will be used by the certificate generation tool
893 to sign the BL2 and Trusted Key certificates. Available options for
894 ``ARM_ROTPK_LOCATION`` are:
896 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
897 registers. The private key corresponding to this ROTPK hash is not
899 - ``devel_rsa`` : return a development public key hash embedded in the BL1
900 and BL2 binaries. This hash has been obtained from the RSA public key
901 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
902 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
903 creating the certificates.
904 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
905 and BL2 binaries. This hash has been obtained from the ECDSA public key
906 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
907 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
908 when creating the certificates.
910 - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
912 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
913 - ``tdram`` : Trusted DRAM (if available)
914 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
915 configured by the TrustZone controller)
917 - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
918 of the translation tables library instead of version 2. It is set to 0 by
919 default, which selects version 2.
921 - ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
922 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
923 platforms. If this option is specified, then the path to the CryptoCell
924 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
926 For a better understanding of these options, the Arm development platform memory
927 map is explained in the `Firmware Design`_.
929 Arm CSS platform specific build options
930 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
932 - ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
933 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
934 compatible change to the MTL protocol, used for AP/SCP communication.
935 TF-A no longer supports earlier SCP versions. If this option is set to 1
936 then TF-A will detect if an earlier version is in use. Default is 1.
938 - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
939 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
940 during boot. Default is 1.
942 - ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
943 instead of SCPI/BOM driver for communicating with the SCP during power
944 management operations and for SCP RAM Firmware transfer. If this option
945 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
947 Arm FVP platform specific build options
948 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
950 - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
951 build the topology tree within TF-A. By default TF-A is configured for dual
952 cluster topology and this option can be used to override the default value.
954 - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
955 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
956 explained in the options below:
958 - ``FVP_CCI`` : The CCI driver is selected. This is the default
959 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
960 - ``FVP_CCN`` : The CCN driver is selected. This is the default
961 if ``FVP_CLUSTER_COUNT`` > 2.
963 - ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
964 a single cluster. This option defaults to 4.
966 - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
967 in the system. This option defaults to 1. Note that the build option
968 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
970 - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
972 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
973 - ``FVP_GICV2`` : The GICv2 only driver is selected
974 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
976 - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
977 for functions that wait for an arbitrary time length (udelay and mdelay).
978 The default value is 0.
980 - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
981 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
982 details on HW_CONFIG. By default, this is initialized to a sensible DTS
983 file in ``fdts/`` folder depending on other build options. But some cases,
984 like shifted affinity format for MPIDR, cannot be detected at build time
985 and this option is needed to specify the appropriate DTS file.
987 - ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
988 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
989 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
990 HW_CONFIG blob instead of the DTS file. This option is useful to override
991 the default HW_CONFIG selected by the build system.
993 ARM JUNO platform specific build options
994 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
996 - ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
997 Media Protection (TZ-MP1). Default value of this flag is 0.
1002 To compile a debug version and make the build more verbose use
1006 make PLAT=<platform> DEBUG=1 V=1 all
1008 AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
1009 example DS-5) might not support this and may need an older version of DWARF
1010 symbols to be emitted by GCC. This can be achieved by using the
1011 ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
1012 version to 2 is recommended for DS-5 versions older than 5.16.
1014 When debugging logic problems it might also be useful to disable all compiler
1015 optimizations by using ``-O0``.
1018 Using ``-O0`` could cause output images to be larger and base addresses
1019 might need to be recalculated (see the **Memory layout on Arm development
1020 platforms** section in the `Firmware Design`_).
1022 Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1027 CFLAGS='-O0 -gdwarf-2' \
1028 make PLAT=<platform> DEBUG=1 V=1 all
1030 Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1031 ignored as the linker is called directly.
1033 It is also possible to introduce an infinite loop to help in debugging the
1034 post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1035 ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
1036 section. In this case, the developer may take control of the target using a
1037 debugger when indicated by the console output. When using DS-5, the following
1038 commands can be used:
1042 # Stop target execution
1046 # Prepare your debugging environment, e.g. set breakpoints
1049 # Jump over the debug loop
1050 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1055 Building the Test Secure Payload
1056 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1058 The TSP is coupled with a companion runtime service in the BL31 firmware,
1059 called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
1060 must be recompiled as well. For more information on SPs and SPDs, see the
1061 `Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
1063 First clean the TF-A build directory to get rid of any previous BL31 binary.
1064 Then to build the TSP image use:
1068 make PLAT=<platform> SPD=tspd all
1070 An additional boot loader binary file is created in the ``build`` directory:
1074 build/<platform>/<build-type>/bl32.bin
1077 Building and using the FIP tool
1078 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1080 Firmware Image Package (FIP) is a packaging format used by TF-A to package
1081 firmware images in a single binary. The number and type of images that should
1082 be packed in a FIP is platform specific and may include TF-A images and other
1083 firmware images required by the platform. For example, most platforms require
1084 a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
1087 The TF-A build system provides the make target ``fip`` to create a FIP file
1088 for the specified platform using the FIP creation tool included in the TF-A
1089 project. Examples below show how to build a FIP file for FVP, packaging TF-A
1096 make PLAT=fvp BL33=<path-to>/bl33.bin fip
1102 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
1104 The resulting FIP may be found in:
1108 build/fvp/<build-type>/fip.bin
1110 For advanced operations on FIP files, it is also possible to independently build
1111 the tool and create or modify FIPs using this tool. To do this, follow these
1114 It is recommended to remove old artifacts before building the tool:
1118 make -C tools/fiptool clean
1124 make [DEBUG=1] [V=1] fiptool
1126 The tool binary can be located in:
1130 ./tools/fiptool/fiptool
1132 Invoking the tool with ``help`` will print a help message with all available
1135 Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1139 ./tools/fiptool/fiptool create \
1140 --tb-fw build/<platform>/<build-type>/bl2.bin \
1141 --soc-fw build/<platform>/<build-type>/bl31.bin \
1144 Example 2: view the contents of an existing Firmware package:
1148 ./tools/fiptool/fiptool info <path-to>/fip.bin
1150 Example 3: update the entries of an existing Firmware package:
1154 # Change the BL2 from Debug to Release version
1155 ./tools/fiptool/fiptool update \
1156 --tb-fw build/<platform>/release/bl2.bin \
1157 build/<platform>/debug/fip.bin
1159 Example 4: unpack all entries from an existing Firmware package:
1163 # Images will be unpacked to the working directory
1164 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1166 Example 5: remove an entry from an existing Firmware package:
1170 ./tools/fiptool/fiptool remove \
1171 --tb-fw build/<platform>/debug/fip.bin
1173 Note that if the destination FIP file exists, the create, update and
1174 remove operations will automatically overwrite it.
1176 The unpack operation will fail if the images already exist at the
1177 destination. In that case, use -f or --force to continue.
1179 More information about FIP can be found in the `Firmware Design`_ document.
1181 Building FIP images with support for Trusted Board Boot
1182 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1184 Trusted Board Boot primarily consists of the following two features:
1186 - Image Authentication, described in `Trusted Board Boot`_, and
1187 - Firmware Update, described in `Firmware Update`_
1189 The following steps should be followed to build FIP and (optionally) FWU_FIP
1190 images with support for these features:
1192 #. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1193 modules by checking out a recent version of the `mbed TLS Repository`_. It
1194 is important to use a version that is compatible with TF-A and fixes any
1195 known security vulnerabilities. See `mbed TLS Security Center`_ for more
1196 information. The latest version of TF-A is tested with tag
1199 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1200 source files the modules depend upon.
1201 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1202 options required to build the mbed TLS sources.
1204 Note that the mbed TLS library is licensed under the Apache version 2.0
1205 license. Using mbed TLS source code will affect the licensing of TF-A
1206 binaries that are built using this library.
1208 #. To build the FIP image, ensure the following command line variables are set
1209 while invoking ``make`` to build TF-A:
1211 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1212 - ``TRUSTED_BOARD_BOOT=1``
1213 - ``GENERATE_COT=1``
1215 In the case of Arm platforms, the location of the ROTPK hash must also be
1216 specified at build time. Two locations are currently supported (see
1217 ``ARM_ROTPK_LOCATION`` build option):
1219 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1220 root-key storage registers present in the platform. On Juno, this
1221 registers are read-only. On FVP Base and Cortex models, the registers
1222 are read-only, but the value can be specified using the command line
1223 option ``bp.trusted_key_storage.public_key`` when launching the model.
1224 On both Juno and FVP models, the default value corresponds to an
1225 ECDSA-SECP256R1 public key hash, whose private part is not currently
1228 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1229 in the Arm platform port. The private/public RSA key pair may be
1230 found in ``plat/arm/board/common/rotpk``.
1232 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1233 in the Arm platform port. The private/public ECDSA key pair may be
1234 found in ``plat/arm/board/common/rotpk``.
1236 Example of command line using RSA development keys:
1240 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1241 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1242 ARM_ROTPK_LOCATION=devel_rsa \
1243 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1244 BL33=<path-to>/<bl33_image> \
1247 The result of this build will be the bl1.bin and the fip.bin binaries. This
1248 FIP will include the certificates corresponding to the Chain of Trust
1249 described in the TBBR-client document. These certificates can also be found
1250 in the output build directory.
1252 #. The optional FWU_FIP contains any additional images to be loaded from
1253 Non-Volatile storage during the `Firmware Update`_ process. To build the
1254 FWU_FIP, any FWU images required by the platform must be specified on the
1255 command line. On Arm development platforms like Juno, these are:
1257 - NS_BL2U. The AP non-secure Firmware Updater image.
1258 - SCP_BL2U. The SCP Firmware Update Configuration image.
1260 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1261 targets using RSA development:
1265 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1266 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1267 ARM_ROTPK_LOCATION=devel_rsa \
1268 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1269 BL33=<path-to>/<bl33_image> \
1270 SCP_BL2=<path-to>/<scp_bl2_image> \
1271 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1272 NS_BL2U=<path-to>/<ns_bl2u_image> \
1276 The BL2U image will be built by default and added to the FWU_FIP.
1277 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1278 to the command line above.
1281 Building and installing the non-secure and SCP FWU images (NS_BL1U,
1282 NS_BL2U and SCP_BL2U) is outside the scope of this document.
1284 The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
1285 Both the FIP and FWU_FIP will include the certificates corresponding to the
1286 Chain of Trust described in the TBBR-client document. These certificates
1287 can also be found in the output build directory.
1289 Building the Certificate Generation Tool
1290 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1292 The ``cert_create`` tool is built as part of the TF-A build process when the
1293 ``fip`` make target is specified and TBB is enabled (as described in the
1294 previous section), but it can also be built separately with the following
1299 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1301 For platforms that require their own IDs in certificate files, the generic
1302 'cert_create' tool can be built with the following command. Note that the target
1303 platform must define its IDs within a ``platform_oid.h`` header file for the
1308 make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
1310 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1311 verbose. The following command should be used to obtain help about the tool:
1315 ./tools/cert_create/cert_create -h
1317 Building a FIP for Juno and FVP
1318 -------------------------------
1320 This section provides Juno and FVP specific instructions to build Trusted
1321 Firmware, obtain the additional required firmware, and pack it all together in
1322 a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
1325 Pre-built binaries for AArch32 are available from Linaro Release 16.12
1326 onwards. Before that release, pre-built binaries are only available for
1330 Follow the full instructions for one platform before switching to a
1331 different one. Mixing instructions for different platforms may result in
1335 The uboot image downloaded by the Linaro workspace script does not always
1336 match the uboot image packaged as BL33 in the corresponding fip file. It is
1337 recommended to use the version that is packaged in the fip file using the
1341 For the FVP, the kernel FDT is packaged in FIP during build and loaded
1342 by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1343 section for more info on selecting the right FDT to use.
1345 #. Clean the working directory
1351 #. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
1353 Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
1354 package included in the Linaro release:
1359 make [DEBUG=1] [V=1] fiptool
1361 # Unpack firmware images from Linaro FIP
1362 ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
1364 The unpack operation will result in a set of binary images extracted to the
1365 current working directory. The SCP_BL2 image corresponds to
1366 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
1369 The fiptool will complain if the images to be unpacked already
1370 exist in the current directory. If that is the case, either delete those
1371 files or use the ``--force`` option to overwrite.
1374 For AArch32, the instructions below assume that nt-fw.bin is a
1375 normal world boot loader that supports AArch32.
1377 #. Build TF-A images and create a new FIP for FVP
1382 make PLAT=fvp BL33=nt-fw.bin all fip
1385 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1387 #. Build TF-A images and create a new FIP for Juno
1391 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1392 as a build parameter.
1396 make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
1400 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1401 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1402 separately for AArch32.
1404 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1405 to the AArch32 cross compiler.
1409 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1411 - Build BL32 in AArch32.
1415 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1416 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1418 - Save ``bl32.bin`` to a temporary location and clean the build products.
1422 cp <path-to-build>/bl32.bin <path-to-temporary>
1425 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1426 must point to the AArch64 cross compiler.
1430 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1432 - The following parameters should be used to build BL1 and BL2 in AArch64
1433 and point to the BL32 file.
1437 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
1438 BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
1439 BL32=<path-to-temporary>/bl32.bin all fip
1441 The resulting BL1 and FIP images may be found in:
1446 ./build/juno/release/bl1.bin
1447 ./build/juno/release/fip.bin
1450 ./build/fvp/release/bl1.bin
1451 ./build/fvp/release/fip.bin
1454 Booting Firmware Update images
1455 -------------------------------------
1457 When Firmware Update (FWU) is enabled there are at least 2 new images
1458 that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1464 The new images must be programmed in flash memory by adding
1465 an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1466 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1467 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1468 programming" for more information. User should ensure these do not
1469 overlap with any other entries in the file.
1473 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1474 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1475 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1476 NOR10LOAD: 00000000 ;Image Load Address
1477 NOR10ENTRY: 00000000 ;Image Entry Point
1479 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1480 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1481 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1482 NOR11LOAD: 00000000 ;Image Load Address
1484 The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1485 In the same way, the address ns_bl2u_base_address is the value of
1486 NS_BL2U_BASE - 0x8000000.
1491 The additional fip images must be loaded with:
1495 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1496 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1498 The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1499 In the same way, the address ns_bl2u_base_address is the value of
1503 EL3 payloads alternative boot flow
1504 ----------------------------------
1506 On a pre-production system, the ability to execute arbitrary, bare-metal code at
1507 the highest exception level is required. It allows full, direct access to the
1508 hardware, for example to run silicon soak tests.
1510 Although it is possible to implement some baremetal secure firmware from
1511 scratch, this is a complex task on some platforms, depending on the level of
1512 configuration required to put the system in the expected state.
1514 Rather than booting a baremetal application, a possible compromise is to boot
1515 ``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1516 boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1517 other BL images and passing control to BL31. It reduces the complexity of
1518 developing EL3 baremetal code by:
1520 - putting the system into a known architectural state;
1521 - taking care of platform secure world initialization;
1522 - loading the SCP_BL2 image if required by the platform.
1524 When booting an EL3 payload on Arm standard platforms, the configuration of the
1525 TrustZone controller is simplified such that only region 0 is enabled and is
1526 configured to permit secure access only. This gives full access to the whole
1527 DRAM to the EL3 payload.
1529 The system is left in the same state as when entering BL31 in the default boot
1530 flow. In particular:
1533 - Current state is AArch64;
1534 - Little-endian data access;
1535 - All exceptions disabled;
1539 Booting an EL3 payload
1540 ~~~~~~~~~~~~~~~~~~~~~~
1542 The EL3 payload image is a standalone image and is not part of the FIP. It is
1543 not loaded by TF-A. Therefore, there are 2 possible scenarios:
1545 - The EL3 payload may reside in non-volatile memory (NVM) and execute in
1546 place. In this case, booting it is just a matter of specifying the right
1547 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
1549 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1552 To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1553 used. The infinite loop that it introduces in BL1 stops execution at the right
1554 moment for a debugger to take control of the target and load the payload (for
1555 example, over JTAG).
1557 It is expected that this loading method will work in most cases, as a debugger
1558 connection is usually available in a pre-production system. The user is free to
1559 use any other platform-specific mechanism to load the EL3 payload, though.
1561 Booting an EL3 payload on FVP
1562 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1564 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1565 the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1566 is undefined on the FVP platform and the FVP platform code doesn't clear it.
1567 Therefore, one must modify the way the model is normally invoked in order to
1568 clear the mailbox at start-up.
1570 One way to do that is to create an 8-byte file containing all zero bytes using
1571 the following command:
1575 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1577 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1578 using the following model parameters:
1582 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1583 --data=mailbox.dat@0x04000000 [Foundation FVP]
1585 To provide the model with the EL3 payload image, the following methods may be
1588 #. If the EL3 payload is able to execute in place, it may be programmed into
1589 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1590 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1595 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
1597 On Foundation FVP, there is no flash loader component and the EL3 payload
1598 may be programmed anywhere in flash using method 3 below.
1600 #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1601 command may be used to load the EL3 payload ELF image over JTAG:
1605 load <path-to>/el3-payload.elf
1607 #. The EL3 payload may be pre-loaded in volatile memory using the following
1612 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
1613 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
1615 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1616 used when building TF-A.
1618 Booting an EL3 payload on Juno
1619 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1621 If the EL3 payload is able to execute in place, it may be programmed in flash
1622 memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1623 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1624 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1625 programming" for more information.
1627 Alternatively, the same DS-5 command mentioned in the FVP section above can
1628 be used to load the EL3 payload's ELF file over JTAG on Juno.
1630 Preloaded BL33 alternative boot flow
1631 ------------------------------------
1633 Some platforms have the ability to preload BL33 into memory instead of relying
1634 on TF-A to load it. This may simplify packaging of the normal world code and
1635 improve performance in a development environment. When secure world cold boot
1636 is complete, TF-A simply jumps to a BL33 base address provided at build time.
1638 For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1639 used when compiling TF-A. For example, the following command will create a FIP
1640 without a BL33 and prepare to jump to a BL33 image loaded at address
1645 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1647 Boot of a preloaded kernel image on Base FVP
1648 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1650 The following example uses a simplified boot flow by directly jumping from the
1651 TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1652 useful if both the kernel and the device tree blob (DTB) are already present in
1653 memory (like in FVP).
1655 For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1656 address ``0x82000000``, the firmware can be built like this:
1660 CROSS_COMPILE=aarch64-linux-gnu- \
1661 make PLAT=fvp DEBUG=1 \
1663 ARM_LINUX_KERNEL_AS_BL33=1 \
1664 PRELOADED_BL33_BASE=0x80080000 \
1665 ARM_PRELOADED_DTB_BASE=0x82000000 \
1668 Now, it is needed to modify the DTB so that the kernel knows the address of the
1669 ramdisk. The following script generates a patched DTB from the provided one,
1670 assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1671 script assumes that the user is using a ramdisk image prepared for U-Boot, like
1672 the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1673 offset in ``INITRD_START`` has to be removed.
1679 # Path to the input DTB
1680 KERNEL_DTB=<path-to>/<fdt>
1681 # Path to the output DTB
1682 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1683 # Base address of the ramdisk
1684 INITRD_BASE=0x84000000
1685 # Path to the ramdisk
1686 INITRD=<path-to>/<ramdisk.img>
1688 # Skip uboot header (64 bytes)
1689 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1690 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1691 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1693 CHOSEN_NODE=$(echo \
1696 linux,initrd-start = <${INITRD_START}>; \
1697 linux,initrd-end = <${INITRD_END}>; \
1701 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1702 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
1704 And the FVP binary can be run with the following command:
1708 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1709 -C pctl.startup=0.0.0.0 \
1710 -C bp.secure_memory=1 \
1711 -C cluster0.NUM_CORES=4 \
1712 -C cluster1.NUM_CORES=4 \
1713 -C cache_state_modelled=1 \
1714 -C cluster0.cpu0.RVBAR=0x04020000 \
1715 -C cluster0.cpu1.RVBAR=0x04020000 \
1716 -C cluster0.cpu2.RVBAR=0x04020000 \
1717 -C cluster0.cpu3.RVBAR=0x04020000 \
1718 -C cluster1.cpu0.RVBAR=0x04020000 \
1719 -C cluster1.cpu1.RVBAR=0x04020000 \
1720 -C cluster1.cpu2.RVBAR=0x04020000 \
1721 -C cluster1.cpu3.RVBAR=0x04020000 \
1722 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1723 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1724 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1725 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1727 Boot of a preloaded kernel image on Juno
1728 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1730 The Trusted Firmware must be compiled in a similar way as for FVP explained
1731 above. The process to load binaries to memory is the one explained in
1732 `Booting an EL3 payload on Juno`_.
1734 Running the software on FVP
1735 ---------------------------
1737 The latest version of the AArch64 build of TF-A has been tested on the following
1738 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1739 (64-bit host machine only).
1742 The FVP models used are Version 11.6 Build 45, unless otherwise stated.
1744 - ``FVP_Base_AEMv8A-AEMv8A``
1745 - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
1746 - ``FVP_Base_RevC-2xAEMv8A``
1747 - ``FVP_Base_Cortex-A32x4``
1748 - ``FVP_Base_Cortex-A35x4``
1749 - ``FVP_Base_Cortex-A53x4``
1750 - ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1751 - ``FVP_Base_Cortex-A55x4``
1752 - ``FVP_Base_Cortex-A57x1-A53x1``
1753 - ``FVP_Base_Cortex-A57x2-A53x4``
1754 - ``FVP_Base_Cortex-A57x4-A53x4``
1755 - ``FVP_Base_Cortex-A57x4``
1756 - ``FVP_Base_Cortex-A72x4-A53x4``
1757 - ``FVP_Base_Cortex-A72x4``
1758 - ``FVP_Base_Cortex-A73x4-A53x4``
1759 - ``FVP_Base_Cortex-A73x4``
1760 - ``FVP_Base_Cortex-A75x4``
1761 - ``FVP_Base_Cortex-A76x4``
1762 - ``FVP_Base_Cortex-A76AEx4``
1763 - ``FVP_Base_Cortex-A76AEx8``
1764 - ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
1765 - ``FVP_Base_Neoverse-N1x4``
1766 - ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
1767 - ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
1768 - ``FVP_RD_E1Edge`` (Version 11.3 build 42)
1770 - ``Foundation_Platform``
1772 The latest version of the AArch32 build of TF-A has been tested on the following
1773 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1774 (64-bit host machine only).
1776 - ``FVP_Base_AEMv8A-AEMv8A``
1777 - ``FVP_Base_Cortex-A32x4``
1780 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1781 is not compatible with legacy GIC configurations. Therefore this FVP does not
1782 support these legacy GIC configurations.
1785 The build numbers quoted above are those reported by launching the FVP
1786 with the ``--version`` parameter.
1789 Linaro provides a ramdisk image in prebuilt FVP configurations and full
1790 file systems that can be downloaded separately. To run an FVP with a virtio
1791 file system image an additional FVP configuration option
1792 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1796 The software will not work on Version 1.0 of the Foundation FVP.
1797 The commands below would report an ``unhandled argument`` error in this case.
1800 FVPs can be launched with ``--cadi-server`` option such that a
1801 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
1805 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
1806 the internal synchronisation timings changed compared to older versions of
1807 the models. The models can be launched with ``-Q 100`` option if they are
1808 required to match the run time characteristics of the older versions.
1810 The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1811 downloaded for free from `Arm's website`_.
1813 The Cortex-A models listed above are also available to download from
1816 Please refer to the FVP documentation for a detailed description of the model
1817 parameter options. A brief description of the important ones that affect TF-A
1818 and normal world software behavior is provided below.
1820 Obtaining the Flattened Device Trees
1821 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1823 Depending on the FVP configuration and Linux configuration used, different
1824 FDT files are required. FDT source files for the Foundation and Base FVPs can
1825 be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1826 a subset of the Base FVP components. For example, the Foundation FVP lacks
1827 CLCD and MMC support, and has only one CPU cluster.
1830 It is not recommended to use the FDTs built along the kernel because not
1831 all FDTs are available from there.
1833 The dynamic configuration capability is enabled in the firmware for FVPs.
1834 This means that the firmware can authenticate and load the FDT if present in
1835 FIP. A default FDT is packaged into FIP during the build based on
1836 the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1837 or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1838 `Arm FVP platform specific build options`_ section for detail on the options).
1840 - ``fvp-base-gicv2-psci.dts``
1842 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1843 affinities and with Base memory map configuration.
1845 - ``fvp-base-gicv2-psci-aarch32.dts``
1847 For use with models such as the Cortex-A32 Base FVPs without shifted
1848 affinities and running Linux in AArch32 state with Base memory map
1851 - ``fvp-base-gicv3-psci.dts``
1853 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1854 affinities and with Base memory map configuration and Linux GICv3 support.
1856 - ``fvp-base-gicv3-psci-1t.dts``
1858 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1859 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1861 - ``fvp-base-gicv3-psci-dynamiq.dts``
1863 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1864 single cluster, single threaded CPUs, Base memory map configuration and Linux
1867 - ``fvp-base-gicv3-psci-aarch32.dts``
1869 For use with models such as the Cortex-A32 Base FVPs without shifted
1870 affinities and running Linux in AArch32 state with Base memory map
1871 configuration and Linux GICv3 support.
1873 - ``fvp-foundation-gicv2-psci.dts``
1875 For use with Foundation FVP with Base memory map configuration.
1877 - ``fvp-foundation-gicv3-psci.dts``
1879 (Default) For use with Foundation FVP with Base memory map configuration
1880 and Linux GICv3 support.
1882 Running on the Foundation FVP with reset to BL1 entrypoint
1883 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1885 The following ``Foundation_Platform`` parameters should be used to boot Linux with
1886 4 CPUs using the AArch64 build of TF-A.
1890 <path-to>/Foundation_Platform \
1896 --data="<path-to>/<bl1-binary>"@0x0 \
1897 --data="<path-to>/<FIP-binary>"@0x08000000 \
1898 --data="<path-to>/<kernel-binary>"@0x80080000 \
1899 --data="<path-to>/<ramdisk-binary>"@0x84000000
1903 - BL1 is loaded at the start of the Trusted ROM.
1904 - The Firmware Image Package is loaded at the start of NOR FLASH0.
1905 - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1906 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
1907 - The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1908 and enable the GICv3 device in the model. Note that without this option,
1909 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1910 is not supported by TF-A.
1911 - In order for TF-A to run correctly on the Foundation FVP, the architecture
1912 versions must match. The Foundation FVP defaults to the highest v8.x
1913 version it supports but the default build for TF-A is for v8.0. To avoid
1914 issues either start the Foundation FVP to use v8.0 architecture using the
1915 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1918 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1919 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1921 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
1922 with 8 CPUs using the AArch64 build of TF-A.
1926 <path-to>/FVP_Base_RevC-2xAEMv8A \
1927 -C pctl.startup=0.0.0.0 \
1928 -C bp.secure_memory=1 \
1929 -C bp.tzc_400.diagnostics=1 \
1930 -C cluster0.NUM_CORES=4 \
1931 -C cluster1.NUM_CORES=4 \
1932 -C cache_state_modelled=1 \
1933 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1934 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1935 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1936 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1939 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
1940 a specific DTS for all the CPUs to be loaded.
1942 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1943 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1945 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1946 with 8 CPUs using the AArch32 build of TF-A.
1950 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1951 -C pctl.startup=0.0.0.0 \
1952 -C bp.secure_memory=1 \
1953 -C bp.tzc_400.diagnostics=1 \
1954 -C cluster0.NUM_CORES=4 \
1955 -C cluster1.NUM_CORES=4 \
1956 -C cache_state_modelled=1 \
1957 -C cluster0.cpu0.CONFIG64=0 \
1958 -C cluster0.cpu1.CONFIG64=0 \
1959 -C cluster0.cpu2.CONFIG64=0 \
1960 -C cluster0.cpu3.CONFIG64=0 \
1961 -C cluster1.cpu0.CONFIG64=0 \
1962 -C cluster1.cpu1.CONFIG64=0 \
1963 -C cluster1.cpu2.CONFIG64=0 \
1964 -C cluster1.cpu3.CONFIG64=0 \
1965 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1966 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1967 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1968 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1970 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1971 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1973 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1974 boot Linux with 8 CPUs using the AArch64 build of TF-A.
1978 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1979 -C pctl.startup=0.0.0.0 \
1980 -C bp.secure_memory=1 \
1981 -C bp.tzc_400.diagnostics=1 \
1982 -C cache_state_modelled=1 \
1983 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1984 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1985 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1986 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1988 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1989 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1991 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1992 boot Linux with 4 CPUs using the AArch32 build of TF-A.
1996 <path-to>/FVP_Base_Cortex-A32x4 \
1997 -C pctl.startup=0.0.0.0 \
1998 -C bp.secure_memory=1 \
1999 -C bp.tzc_400.diagnostics=1 \
2000 -C cache_state_modelled=1 \
2001 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
2002 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
2003 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2004 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2006 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
2007 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2009 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
2010 with 8 CPUs using the AArch64 build of TF-A.
2014 <path-to>/FVP_Base_RevC-2xAEMv8A \
2015 -C pctl.startup=0.0.0.0 \
2016 -C bp.secure_memory=1 \
2017 -C bp.tzc_400.diagnostics=1 \
2018 -C cluster0.NUM_CORES=4 \
2019 -C cluster1.NUM_CORES=4 \
2020 -C cache_state_modelled=1 \
2021 -C cluster0.cpu0.RVBAR=0x04010000 \
2022 -C cluster0.cpu1.RVBAR=0x04010000 \
2023 -C cluster0.cpu2.RVBAR=0x04010000 \
2024 -C cluster0.cpu3.RVBAR=0x04010000 \
2025 -C cluster1.cpu0.RVBAR=0x04010000 \
2026 -C cluster1.cpu1.RVBAR=0x04010000 \
2027 -C cluster1.cpu2.RVBAR=0x04010000 \
2028 -C cluster1.cpu3.RVBAR=0x04010000 \
2029 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2030 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
2031 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2032 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2033 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2034 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2038 - If Position Independent Executable (PIE) support is enabled for BL31
2039 in this config, it can be loaded at any valid address for execution.
2041 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
2042 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
2043 parameter is needed to load the individual bootloader images in memory.
2044 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
2045 Payload. For the same reason, the FDT needs to be compiled from the DT source
2046 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
2049 - The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
2050 specific DTS for all the CPUs to be loaded.
2052 - The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
2053 X and Y are the cluster and CPU numbers respectively, is used to set the
2054 reset vector for each core.
2056 - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
2057 changing the value of
2058 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
2061 Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
2062 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2064 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
2065 with 8 CPUs using the AArch32 build of TF-A.
2069 <path-to>/FVP_Base_AEMv8A-AEMv8A \
2070 -C pctl.startup=0.0.0.0 \
2071 -C bp.secure_memory=1 \
2072 -C bp.tzc_400.diagnostics=1 \
2073 -C cluster0.NUM_CORES=4 \
2074 -C cluster1.NUM_CORES=4 \
2075 -C cache_state_modelled=1 \
2076 -C cluster0.cpu0.CONFIG64=0 \
2077 -C cluster0.cpu1.CONFIG64=0 \
2078 -C cluster0.cpu2.CONFIG64=0 \
2079 -C cluster0.cpu3.CONFIG64=0 \
2080 -C cluster1.cpu0.CONFIG64=0 \
2081 -C cluster1.cpu1.CONFIG64=0 \
2082 -C cluster1.cpu2.CONFIG64=0 \
2083 -C cluster1.cpu3.CONFIG64=0 \
2084 -C cluster0.cpu0.RVBAR=0x04002000 \
2085 -C cluster0.cpu1.RVBAR=0x04002000 \
2086 -C cluster0.cpu2.RVBAR=0x04002000 \
2087 -C cluster0.cpu3.RVBAR=0x04002000 \
2088 -C cluster1.cpu0.RVBAR=0x04002000 \
2089 -C cluster1.cpu1.RVBAR=0x04002000 \
2090 -C cluster1.cpu2.RVBAR=0x04002000 \
2091 -C cluster1.cpu3.RVBAR=0x04002000 \
2092 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2093 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2094 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2095 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2096 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2099 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
2100 It should match the address programmed into the RVBAR register as well.
2102 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
2103 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2105 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
2106 boot Linux with 8 CPUs using the AArch64 build of TF-A.
2110 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
2111 -C pctl.startup=0.0.0.0 \
2112 -C bp.secure_memory=1 \
2113 -C bp.tzc_400.diagnostics=1 \
2114 -C cache_state_modelled=1 \
2115 -C cluster0.cpu0.RVBARADDR=0x04010000 \
2116 -C cluster0.cpu1.RVBARADDR=0x04010000 \
2117 -C cluster0.cpu2.RVBARADDR=0x04010000 \
2118 -C cluster0.cpu3.RVBARADDR=0x04010000 \
2119 -C cluster1.cpu0.RVBARADDR=0x04010000 \
2120 -C cluster1.cpu1.RVBARADDR=0x04010000 \
2121 -C cluster1.cpu2.RVBARADDR=0x04010000 \
2122 -C cluster1.cpu3.RVBARADDR=0x04010000 \
2123 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2124 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
2125 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2126 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2127 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2128 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2130 Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
2131 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2133 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
2134 boot Linux with 4 CPUs using the AArch32 build of TF-A.
2138 <path-to>/FVP_Base_Cortex-A32x4 \
2139 -C pctl.startup=0.0.0.0 \
2140 -C bp.secure_memory=1 \
2141 -C bp.tzc_400.diagnostics=1 \
2142 -C cache_state_modelled=1 \
2143 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2144 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2145 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2146 -C cluster0.cpu3.RVBARADDR=0x04002000 \
2147 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2148 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2149 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2150 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2151 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2153 Running the software on Juno
2154 ----------------------------
2156 This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
2158 To execute the software stack on Juno, installing the latest Arm Platforms
2159 software deliverables is recommended. Please install the deliverables by
2160 following the `Instructions for using Linaro's deliverables on Juno`_.
2162 Preparing TF-A images
2163 ~~~~~~~~~~~~~~~~~~~~~
2165 After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2166 ``SOFTWARE/`` directory of the Juno SD card.
2168 Other Juno software information
2169 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2171 Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
2172 software information. Please also refer to the `Juno Getting Started Guide`_ to
2173 get more detailed information about the Juno Arm development platform and how to
2176 Testing SYSTEM SUSPEND on Juno
2177 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2179 The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2180 to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2181 on Juno, at the linux shell prompt, issue the following command:
2185 echo +10 > /sys/class/rtc/rtc0/wakealarm
2186 echo -n mem > /sys/power/state
2188 The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2189 wakeup interrupt from RTC.
2193 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
2195 .. _Arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
2196 .. _Linaro Release: http://releases.linaro.org/members/arm/platforms
2197 .. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
2198 .. _Linaro instructions: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about
2199 .. _Arm Platforms User guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/user-guide.rst
2200 .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
2201 .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
2202 .. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
2203 .. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
2204 .. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
2205 .. _Linux master tree: https://github.com/torvalds/linux/tree/master/
2206 .. _Dia: https://wiki.gnome.org/Apps/Dia/Download
2207 .. _here: psci-lib-integration-guide.rst
2208 .. _Trusted Board Boot: ../design/trusted-board-boot.rst
2209 .. _TB_FW_CONFIG for FVP: ../../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
2210 .. _Secure-EL1 Payloads and Dispatchers: ../design/firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
2211 .. _Firmware Update: ../components/firmware-update.rst
2212 .. _Firmware Design: ../design/firmware-design.rst
2213 .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2214 .. _mbed TLS Security Center: https://tls.mbed.org/security
2215 .. _Arm's website: `FVP models`_
2216 .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
2217 .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
2218 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2219 .. _Secure Partition Manager Design guide: ../components/secure-partition-manager-design.rst
2220 .. _`Trusted Firmware-A Coding Guidelines`: ../process/coding-guidelines.rst
2221 .. _Library at ROM: ../components/romlib-design.rst