4 This document describes how to build Trusted Firmware-A (TF-A) and run it with a
5 tested set of other software components using defined configurations on the Juno
6 Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
7 possible to use other software components, configurations and platforms but that
8 is outside the scope of this document.
10 This document assumes that the reader has previous experience running a fully
11 bootable Linux software stack on Juno or FVP using the prebuilt binaries and
12 filesystems provided by `Linaro`_. Further information may be found in the
13 `Linaro instructions`_. It also assumes that the user understands the role of
14 the different software components required to boot a Linux system:
16 - Specific firmware images required by the platform (e.g. SCP firmware on Juno)
17 - Normal world bootloader (e.g. UEFI or U-Boot)
22 This document also assumes that the user is familiar with the `FVP models`_ and
23 the different command line options available to launch the model.
25 This document should be used in conjunction with the `Firmware Design`_.
27 Host machine requirements
28 -------------------------
30 The minimum recommended machine specification for building the software and
31 running the FVP models is a dual-core processor running at 2GHz with 12GB of
32 RAM. For best performance, use a machine with a quad-core processor running at
33 2.6GHz with 16GB of RAM.
35 The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
36 building the software were installed from that distribution unless otherwise
39 The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
40 Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
45 Install the required packages to build TF-A with the following command:
49 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
51 TF-A has been tested with Linaro Release 18.04.
53 Download and install the AArch32 or AArch64 little-endian GCC cross compiler. If
54 you would like to use the latest features available, download GCC 8.2-2019.01
55 compiler from `arm Developer page`_. Otherwise, the `Linaro Release Notes`_
56 documents which version of the compiler to use for a given Linaro Release. Also,
57 these `Linaro instructions`_ provide further guidance and a script, which can be
58 used to download Linaro deliverables automatically.
60 Optionally, TF-A can be built using clang version 4.0 or newer or Arm
61 Compiler 6. See instructions below on how to switch the default compiler.
63 In addition, the following optional packages and tools may be needed:
65 - ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
66 Tree (FDT) source files (``.dts`` files) provided with this software. The
67 version of dtc must be 1.4.6 or above.
69 - For debugging, Arm `Development Studio 5 (DS-5)`_.
71 - To create and modify the diagram files included in the documentation, `Dia`_.
72 This tool can be found in most Linux distributions. Inkscape is needed to
73 generate the actual \*.png files.
75 Getting the TF-A source code
76 ----------------------------
78 Clone the repository from the Gerrit server. The project details may be found
79 on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
80 commit-msg hook`" clone method, which will setup the git commit hook that
81 automatically generates and inserts appropriate `Change-Id:` lines in your
84 Checking source code style
85 ~~~~~~~~~~~~~~~~~~~~~~~~~~
87 Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
88 source, for submission to the project, the source must be in compliance with
91 Additional, project-specific guidelines are defined in the `Trusted Firmware-A
92 Coding Guidelines`_ document.
94 To assist with coding style compliance, the project Makefile contains two
95 targets which both utilise the `checkpatch.pl` script that ships with the Linux
96 source tree. The project also defines certain *checkpatch* options in the
97 ``.checkpatch.conf`` file in the top-level directory.
100 Checkpatch errors will gate upstream merging of pull requests.
101 Checkpatch warnings will not gate merging but should be reviewed and fixed if
104 To check the entire source tree, you must first download copies of
105 ``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
106 in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
107 environment variable to point to ``checkpatch.pl`` (with the other 2 files in
108 the same directory) and build the `checkcodebase` target:
112 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
114 To just check the style on the files that differ between your local branch and
115 the remote master, use:
119 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
121 If you wish to check your patch against something other than the remote master,
122 set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
123 is set to ``origin/master``.
128 - Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
129 to the Linaro cross compiler.
135 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
141 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
143 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
144 ``CC`` needs to point to the clang or armclang binary, which will
145 also select the clang or armclang assembler. Be aware that the
146 GNU linker is used by default. In case of being needed the linker
147 can be overridden using the ``LD`` variable. Clang linker version 6 is
148 known to work with TF-A.
150 In both cases ``CROSS_COMPILE`` should be set as described above.
152 Arm Compiler 6 will be selected when the base name of the path assigned
153 to ``CC`` matches the string 'armclang'.
155 For AArch64 using Arm Compiler 6:
159 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
160 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
162 Clang will be selected when the base name of the path assigned to ``CC``
163 contains the string 'clang'. This is to allow both clang and clang-X.Y
166 For AArch64 using clang:
170 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
171 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
173 - Change to the root directory of the TF-A source tree and build.
179 make PLAT=<platform> all
185 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
189 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
190 `Summary of build options`_ for more information on available build
193 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
195 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
196 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
197 provided by TF-A to demonstrate how PSCI Library can be integrated with
198 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
199 include other runtime services, for example Trusted OS services. A guide
200 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
203 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
204 image, is not compiled in by default. Refer to the
205 `Building the Test Secure Payload`_ section below.
207 - By default this produces a release version of the build. To produce a
208 debug version instead, refer to the "Debugging options" section below.
210 - The build process creates products in a ``build`` directory tree, building
211 the objects and binaries for each boot loader stage in separate
212 sub-directories. The following boot loader binary files are created
213 from the corresponding ELF files:
215 - ``build/<platform>/<build-type>/bl1.bin``
216 - ``build/<platform>/<build-type>/bl2.bin``
217 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
218 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
220 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
221 is either ``debug`` or ``release``. The actual number of images might differ
222 depending on the platform.
224 - Build products for a specific build variant can be removed using:
228 make DEBUG=<D> PLAT=<platform> clean
230 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
232 The build tree can be removed completely using:
238 Summary of build options
239 ~~~~~~~~~~~~~~~~~~~~~~~~
241 The TF-A build system supports the following build options. Unless mentioned
242 otherwise, these options are expected to be specified at the build command
243 line and are not to be modified in any component makefiles. Note that the
244 build system doesn't track dependency for build options. Therefore, if any of
245 the build options are changed from a previous build, a clean build must be
251 - ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
252 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
253 code having a smaller resulting size.
255 - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
256 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
257 directory containing the SP source, relative to the ``bl32/``; the directory
258 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
260 - ``ARCH`` : Choose the target build architecture for TF-A. It can take either
261 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
264 - ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
265 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
266 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
269 - ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
270 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
271 *Armv8 Architecture Extensions* in `Firmware Design`_.
273 - ``BL2``: This is an optional build option which specifies the path to BL2
274 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
277 - ``BL2U``: This is an optional build option which specifies the path to
278 BL2U image. In this case, the BL2U in TF-A will not be built.
280 - ``BL2_AT_EL3``: This is an optional build option that enables the use of
281 BL2 at EL3 execution level.
283 - ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
284 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
285 the RW sections in RAM, while leaving the RO sections in place. This option
286 enable this use-case. For now, this option is only supported when BL2_AT_EL3
289 - ``BL31``: This is an optional build option which specifies the path to
290 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
293 - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
294 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
295 this file name will be used to save the key.
297 - ``BL32``: This is an optional build option which specifies the path to
298 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
301 - ``BL32_EXTRA1``: This is an optional build option which specifies the path to
302 Trusted OS Extra1 image for the ``fip`` target.
304 - ``BL32_EXTRA2``: This is an optional build option which specifies the path to
305 Trusted OS Extra2 image for the ``fip`` target.
307 - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
308 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
309 this file name will be used to save the key.
311 - ``BL33``: Path to BL33 image in the host file system. This is mandatory for
312 ``fip`` target in case TF-A BL2 is used.
314 - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
315 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
316 this file name will be used to save the key.
318 - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
319 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
320 If enabled, it is needed to use a compiler that supports the option
321 ``-mbranch-protection``. Selects the branch protection features to use:
322 - 0: Default value turns off all types of branch protection
323 - 1: Enables all types of branch protection features
324 - 2: Return address signing to its standard level
325 - 3: Extend the signing to include leaf functions
327 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
328 and resulting PAuth/BTI features.
330 +-------+--------------+-------+-----+
331 | Value | GCC option | PAuth | BTI |
332 +=======+==============+=======+=====+
334 +-------+--------------+-------+-----+
335 | 1 | standard | Y | Y |
336 +-------+--------------+-------+-----+
337 | 2 | pac-ret | Y | N |
338 +-------+--------------+-------+-----+
339 | 3 | pac-ret+leaf | Y | N |
340 +-------+--------------+-------+-----+
342 This option defaults to 0 and this is an experimental feature.
343 Note that Pointer Authentication is enabled for Non-secure world
344 irrespective of the value of this option if the CPU supports it.
346 - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
347 compilation of each build. It must be set to a C string (including quotes
348 where applicable). Defaults to a string that contains the time and date of
351 - ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
352 build to be uniquely identified. Defaults to the current git commit id.
354 - ``CFLAGS``: Extra user options appended on the compiler's command line in
355 addition to the options set by the build system.
357 - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
358 release several CPUs out of reset. It can take either 0 (several CPUs may be
359 brought up) or 1 (only one CPU will ever be brought up during cold reset).
360 Default is 0. If the platform always brings up a single CPU, there is no
361 need to distinguish between primary and secondary CPUs and the boot path can
362 be optimised. The ``plat_is_my_cpu_primary()`` and
363 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
364 to be implemented in this case.
366 - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
367 register state when an unexpected exception occurs during execution of
368 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
369 this is only enabled for a debug build of the firmware.
371 - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
372 certificate generation tool to create new keys in case no valid keys are
373 present or specified. Allowed options are '0' or '1'. Default is '1'.
375 - ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
376 the AArch32 system registers to be included when saving and restoring the
377 CPU context. The option must be set to 0 for AArch64-only platforms (that
378 is on hardware that does not implement AArch32, or at least not at EL1 and
379 higher ELs). Default value is 1.
381 - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
382 registers to be included when saving and restoring the CPU context. Default
385 - ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
386 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
387 registers to be included when saving and restoring the CPU context as
388 part of world switch. Default value is 0 and this is an experimental feature.
389 Note that Pointer Authentication is enabled for Non-secure world irrespective
390 of the value of this flag if the CPU supports it.
392 - ``DEBUG``: Chooses between a debug and release build. It can take either 0
393 (release) or 1 (debug) as values. 0 is the default.
395 - ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
396 of the binary image. If set to 1, then only the ELF image is built.
399 - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
400 Board Boot authentication at runtime. This option is meant to be enabled only
401 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
402 flag has to be enabled. 0 is the default.
404 - ``E``: Boolean option to make warnings into errors. Default is 1.
406 - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
407 the normal boot flow. It must specify the entry point address of the EL3
408 payload. Please refer to the "Booting an EL3 payload" section for more
411 - ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
412 This is an optional architectural feature available on v8.4 onwards. Some
413 v8.2 implementations also implement an AMU and this option can be used to
414 enable this feature on those systems as well. Default is 0.
416 - ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
417 are compiled out. For debug builds, this option defaults to 1, and calls to
418 ``assert()`` are left in place. For release builds, this option defaults to 0
419 and calls to ``assert()`` function are compiled out. This option can be set
420 independently of ``DEBUG``. It can also be used to hide any auxiliary code
421 that is only required for the assertion and does not fit in the assertion
424 - ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
425 dumps or not. It is supported in both AArch64 and AArch32. However, in
426 AArch32 the format of the frame records are not defined in the AAPCS and they
427 are defined by the implementation. This implementation of backtrace only
428 supports the format used by GCC when T32 interworking is disabled. For this
429 reason enabling this option in AArch32 will force the compiler to only
430 generate A32 code. This option is enabled by default only in AArch64 debug
431 builds, but this behaviour can be overridden in each platform's Makefile or
432 in the build command line.
434 - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
435 feature. MPAM is an optional Armv8.4 extension that enables various memory
436 system components and resources to define partitions; software running at
437 various ELs can assign themselves to desired partition to control their
440 When this option is set to ``1``, EL3 allows lower ELs to access their own
441 MPAM registers without trapping into EL3. This option doesn't make use of
442 partitioning in EL3, however. Platform initialisation code should configure
443 and use partitions in EL3 as required. This option defaults to ``0``.
445 - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
446 support within generic code in TF-A. This option is currently only supported
447 in BL31. Default is 0.
449 - ``ENABLE_PMF``: Boolean option to enable support for optional Performance
450 Measurement Framework(PMF). Default is 0.
452 - ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
453 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
454 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
455 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
458 - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
459 instrumentation which injects timestamp collection points into TF-A to
460 allow runtime performance to be measured. Currently, only PSCI is
461 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
462 as well. Default is 0.
464 - ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
465 extensions. This is an optional architectural feature for AArch64.
466 The default is 1 but is automatically disabled when the target architecture
469 - ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
470 Refer to the `Secure Partition Manager Design guide`_ for more details about
471 this feature. Default is 0.
473 - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
474 (SVE) for the Non-secure world only. SVE is an optional architectural feature
475 for AArch64. Note that when SVE is enabled for the Non-secure world, access
476 to SIMD and floating-point functionality from the Secure world is disabled.
477 This is to avoid corruption of the Non-secure world data in the Z-registers
478 which are aliased by the SIMD and FP registers. The build option is not
479 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
480 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
481 1. The default is 1 but is automatically disabled when the target
482 architecture is AArch32.
484 - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
485 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
486 default value is set to "none". "strong" is the recommended stack protection
487 level if this feature is desired. "none" disables the stack protection. For
488 all values other than "none", the ``plat_get_stack_protector_canary()``
489 platform hook needs to be implemented. The value is passed as the last
490 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
492 - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
493 deprecated platform APIs, helper functions or drivers within Trusted
494 Firmware as error. It can take the value 1 (flag the use of deprecated
495 APIs as error) or 0. The default is 0.
497 - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
498 targeted at EL3. When set ``0`` (default), no exceptions are expected or
499 handled at EL3, and a panic will result. This is supported only for AArch64
502 - ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
503 injection from lower ELs, and this build option enables lower ELs to use
504 Error Records accessed via System Registers to inject faults. This is
505 applicable only to AArch64 builds.
507 This feature is intended for testing purposes only, and is advisable to keep
508 disabled for production images.
510 - ``FIP_NAME``: This is an optional build option which specifies the FIP
511 filename for the ``fip`` target. Default is ``fip.bin``.
513 - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
514 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
516 - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
517 tool to create certificates as per the Chain of Trust described in
518 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
519 include the certificates in the FIP and FWU_FIP. Default value is '0'.
521 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
522 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
523 the corresponding certificates, and to include those certificates in the
526 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
527 images will not include support for Trusted Board Boot. The FIP will still
528 include the corresponding certificates. This FIP can be used to verify the
529 Chain of Trust on the host machine through other mechanisms.
531 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
532 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
533 will not include the corresponding certificates, causing a boot failure.
535 - ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
536 inherent support for specific EL3 type interrupts. Setting this build option
537 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
538 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
539 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
540 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
541 the Secure Payload interrupts needs to be synchronously handed over to Secure
542 EL1 for handling. The default value of this option is ``0``, which means the
543 Group 0 interrupts are assumed to be handled by Secure EL1.
545 .. __: `platform-interrupt-controller-API.rst`
546 .. __: `interrupt-framework-design.rst`
548 - ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
549 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
550 ``0`` (default), these exceptions will be trapped in the current exception
551 level (or in EL1 if the current exception level is EL0).
553 - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
554 software operations are required for CPUs to enter and exit coherency.
555 However, newer systems exist where CPUs' entry to and exit from coherency
556 is managed in hardware. Such systems require software to only initiate these
557 operations, and the rest is managed in hardware, minimizing active software
558 management. In such systems, this boolean option enables TF-A to carry out
559 build and run-time optimizations during boot and power management operations.
560 This option defaults to 0 and if it is enabled, then it implies
561 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
563 If this flag is disabled while the platform which TF-A is compiled for
564 includes cores that manage coherency in hardware, then a compilation error is
565 generated. This is based on the fact that a system cannot have, at the same
566 time, cores that manage coherency in hardware and cores that don't. In other
567 words, a platform cannot have, at the same time, cores that require
568 ``HW_ASSISTED_COHERENCY=1`` and cores that require
569 ``HW_ASSISTED_COHERENCY=0``.
571 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
572 translation library (xlat tables v2) must be used; version 1 of translation
573 library is not supported.
575 - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
576 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
577 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
578 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
581 - ``KEY_ALG``: This build flag enables the user to select the algorithm to be
582 used for generating the PKCS keys and subsequent signing of the certificate.
583 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
584 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
585 compliant and is retained only for compatibility. The default value of this
586 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
588 - ``HASH_ALG``: This build flag enables the user to select the secure hash
589 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
590 The default value of this flag is ``sha256``.
592 - ``LDFLAGS``: Extra user options appended to the linkers' command line in
593 addition to the one set by the build system.
595 - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
596 output compiled into the build. This should be one of the following:
602 20 (LOG_LEVEL_NOTICE)
603 30 (LOG_LEVEL_WARNING)
605 50 (LOG_LEVEL_VERBOSE)
607 All log output up to and including the selected log level is compiled into
608 the build. The default value is 40 in debug builds and 20 in release builds.
610 - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
611 specifies the file that contains the Non-Trusted World private key in PEM
612 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
614 - ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
615 optional. It is only needed if the platform makefile specifies that it
616 is required in order to build the ``fwu_fip`` target.
618 - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
619 contents upon world switch. It can take either 0 (don't save and restore) or
620 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
621 wants the timer registers to be saved and restored.
623 - ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
624 for the BL image. It can be either 0 (include) or 1 (remove). The default
627 - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
628 the underlying hardware is not a full PL011 UART but a minimally compliant
629 generic UART, which is a subset of the PL011. The driver will not access
630 any register that is not part of the SBSA generic UART specification.
631 Default value is 0 (a full PL011 compliant UART is present).
633 - ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
634 must be subdirectory of any depth under ``plat/``, and must contain a
635 platform makefile named ``platform.mk``. For example, to build TF-A for the
636 Arm Juno board, select PLAT=juno.
638 - ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
639 instead of the normal boot flow. When defined, it must specify the entry
640 point address for the preloaded BL33 image. This option is incompatible with
641 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
642 over ``PRELOADED_BL33_BASE``.
644 - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
645 vector address can be programmed or is fixed on the platform. It can take
646 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
647 programmable reset address, it is expected that a CPU will start executing
648 code directly at the right address, both on a cold and warm reset. In this
649 case, there is no need to identify the entrypoint on boot and the boot path
650 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
651 does not need to be implemented in this case.
653 - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
654 possible for the PSCI power-state parameter: original and extended State-ID
655 formats. This flag if set to 1, configures the generic PSCI layer to use the
656 extended format. The default value of this flag is 0, which means by default
657 the original power-state format is used by the PSCI implementation. This flag
658 should be specified by the platform makefile and it governs the return value
659 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
660 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
663 - ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
664 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
667 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
670 This option is disabled by default.
672 - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
673 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
674 entrypoint) or 1 (CPU reset to BL31 entrypoint).
675 The default value is 0.
677 - ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
678 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
679 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
680 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
682 - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
683 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
684 file name will be used to save the key.
686 - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
687 certificate generation tool to save the keys used to establish the Chain of
688 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
690 - ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
691 If a SCP_BL2 image is present then this option must be passed for the ``fip``
694 - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
695 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
696 this file name will be used to save the key.
698 - ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
699 optional. It is only needed if the platform makefile specifies that it
700 is required in order to build the ``fwu_fip`` target.
702 - ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
703 Delegated Exception Interface to BL31 image. This defaults to ``0``.
705 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
708 - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
709 isolated on separate memory pages. This is a trade-off between security and
710 memory usage. See "Isolating code and read-only data on separate memory
711 pages" section in `Firmware Design`_. This flag is disabled by default and
712 affects all BL images.
714 - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
715 This build option is only valid if ``ARCH=aarch64``. The value should be
716 the path to the directory containing the SPD source, relative to
717 ``services/spd/``; the directory is expected to contain a makefile called
720 - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
721 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
722 execution in BL1 just before handing over to BL31. At this point, all
723 firmware images have been loaded in memory, and the MMU and caches are
724 turned off. Refer to the "Debugging options" section for more details.
726 - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
727 secure interrupts (caught through the FIQ line). Platforms can enable
728 this directive if they need to handle such interruption. When enabled,
729 the FIQ are handled in monitor mode and non secure world is not allowed
730 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
731 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
733 - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
734 Boot feature. When set to '1', BL1 and BL2 images include support to load
735 and verify the certificates and images in a FIP, and BL1 includes support
736 for the Firmware Update. The default value is '0'. Generation and inclusion
737 of certificates in the FIP and FWU_FIP depends upon the value of the
738 ``GENERATE_COT`` option.
741 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
742 already exist in disk, they will be overwritten without further notice.
744 - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
745 specifies the file that contains the Trusted World private key in PEM
746 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
748 - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
749 synchronous, (see "Initializing a BL32 Image" section in
750 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
751 synchronous method) or 1 (BL32 is initialized using asynchronous method).
754 - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
755 routing model which routes non-secure interrupts asynchronously from TSP
756 to EL3 causing immediate preemption of TSP. The EL3 is responsible
757 for saving and restoring the TSP context in this routing model. The
758 default routing model (when the value is 0) is to route non-secure
759 interrupts to TSP allowing it to save its context and hand over
760 synchronously to EL3 via an SMC.
763 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
764 must also be set to ``1``.
766 - ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
767 linker. When the ``LINKER`` build variable points to the armlink linker,
768 this flag is enabled automatically. To enable support for armlink, platforms
769 will have to provide a scatter file for the BL image. Currently, Tegra
770 platforms use the armlink support to compile BL3-1 images.
772 - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
773 memory region in the BL memory map or not (see "Use of Coherent memory in
774 TF-A" section in `Firmware Design`_). It can take the value 1
775 (Coherent memory region is included) or 0 (Coherent memory region is
776 excluded). Default is 1.
778 - ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
779 This feature creates a library of functions to be placed in ROM and thus
780 reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default
783 - ``V``: Verbose build. If assigned anything other than 0, the build commands
784 are printed. Default is 0.
786 - ``VERSION_STRING``: String used in the log output for each TF-A image.
787 Defaults to a string formed by concatenating the version number, build type
790 - ``W``: Warning level. Some compiler warning options of interest have been
791 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
792 each level enabling more warning options. Default is 0.
794 - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
795 the CPU after warm boot. This is applicable for platforms which do not
796 require interconnect programming to enable cache coherency (eg: single
797 cluster platforms). If this option is enabled, then warm boot path
798 enables D-caches immediately after enabling MMU. This option defaults to 0.
800 Arm development platform specific build options
801 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
803 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
804 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
805 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
806 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
809 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
810 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
811 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
812 match the frame used by the Non-Secure image (normally the Linux kernel).
813 Default is true (access to the frame is allowed).
815 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
816 By default, Arm platforms use a watchdog to trigger a system reset in case
817 an error is encountered during the boot process (for example, when an image
818 could not be loaded or authenticated). The watchdog is enabled in the early
819 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
820 Trusted Watchdog may be disabled at build time for testing or development
823 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
824 have specific values at boot. This boolean option allows the Trusted Firmware
825 to have a Linux kernel image as BL33 by preparing the registers to these
826 values before jumping to BL33. This option defaults to 0 (disabled). For
827 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
828 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
829 to the location of a device tree blob (DTB) already loaded in memory. The
830 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
833 - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
834 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
835 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
836 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
837 this flag is 0. Note that this option is not used on FVP platforms.
839 - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
840 for the construction of composite state-ID in the power-state parameter.
841 The existing PSCI clients currently do not support this encoding of
842 State-ID yet. Hence this flag is used to configure whether to use the
843 recommended State-ID encoding or not. The default value of this flag is 0,
844 in which case the platform is configured to expect NULL in the State-ID
845 field of power-state parameter.
847 - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
848 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
849 for Arm platforms. Depending on the selected option, the proper private key
850 must be specified using the ``ROT_KEY`` option when building the Trusted
851 Firmware. This private key will be used by the certificate generation tool
852 to sign the BL2 and Trusted Key certificates. Available options for
853 ``ARM_ROTPK_LOCATION`` are:
855 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
856 registers. The private key corresponding to this ROTPK hash is not
858 - ``devel_rsa`` : return a development public key hash embedded in the BL1
859 and BL2 binaries. This hash has been obtained from the RSA public key
860 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
861 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
862 creating the certificates.
863 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
864 and BL2 binaries. This hash has been obtained from the ECDSA public key
865 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
866 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
867 when creating the certificates.
869 - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
871 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
872 - ``tdram`` : Trusted DRAM (if available)
873 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
874 configured by the TrustZone controller)
876 - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
877 of the translation tables library instead of version 2. It is set to 0 by
878 default, which selects version 2.
880 - ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
881 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
882 platforms. If this option is specified, then the path to the CryptoCell
883 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
885 For a better understanding of these options, the Arm development platform memory
886 map is explained in the `Firmware Design`_.
888 Arm CSS platform specific build options
889 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
891 - ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
892 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
893 compatible change to the MTL protocol, used for AP/SCP communication.
894 TF-A no longer supports earlier SCP versions. If this option is set to 1
895 then TF-A will detect if an earlier version is in use. Default is 1.
897 - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
898 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
899 during boot. Default is 1.
901 - ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
902 instead of SCPI/BOM driver for communicating with the SCP during power
903 management operations and for SCP RAM Firmware transfer. If this option
904 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
906 Arm FVP platform specific build options
907 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
909 - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
910 build the topology tree within TF-A. By default TF-A is configured for dual
911 cluster topology and this option can be used to override the default value.
913 - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
914 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
915 explained in the options below:
917 - ``FVP_CCI`` : The CCI driver is selected. This is the default
918 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
919 - ``FVP_CCN`` : The CCN driver is selected. This is the default
920 if ``FVP_CLUSTER_COUNT`` > 2.
922 - ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
923 a single cluster. This option defaults to 4.
925 - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
926 in the system. This option defaults to 1. Note that the build option
927 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
929 - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
931 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
932 - ``FVP_GICV2`` : The GICv2 only driver is selected
933 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
935 - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
936 for functions that wait for an arbitrary time length (udelay and mdelay).
937 The default value is 0.
939 - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
940 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
941 details on HW_CONFIG. By default, this is initialized to a sensible DTS
942 file in ``fdts/`` folder depending on other build options. But some cases,
943 like shifted affinity format for MPIDR, cannot be detected at build time
944 and this option is needed to specify the appropriate DTS file.
946 - ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
947 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
948 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
949 HW_CONFIG blob instead of the DTS file. This option is useful to override
950 the default HW_CONFIG selected by the build system.
952 ARM JUNO platform specific build options
953 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
955 - ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
956 Media Protection (TZ-MP1). Default value of this flag is 0.
961 To compile a debug version and make the build more verbose use
965 make PLAT=<platform> DEBUG=1 V=1 all
967 AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
968 example DS-5) might not support this and may need an older version of DWARF
969 symbols to be emitted by GCC. This can be achieved by using the
970 ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
971 version to 2 is recommended for DS-5 versions older than 5.16.
973 When debugging logic problems it might also be useful to disable all compiler
974 optimizations by using ``-O0``.
977 Using ``-O0`` could cause output images to be larger and base addresses
978 might need to be recalculated (see the **Memory layout on Arm development
979 platforms** section in the `Firmware Design`_).
981 Extra debug options can be passed to the build system by setting ``CFLAGS`` or
986 CFLAGS='-O0 -gdwarf-2' \
987 make PLAT=<platform> DEBUG=1 V=1 all
989 Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
990 ignored as the linker is called directly.
992 It is also possible to introduce an infinite loop to help in debugging the
993 post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
994 ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
995 section. In this case, the developer may take control of the target using a
996 debugger when indicated by the console output. When using DS-5, the following
997 commands can be used:
1001 # Stop target execution
1005 # Prepare your debugging environment, e.g. set breakpoints
1008 # Jump over the debug loop
1009 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1014 Building the Test Secure Payload
1015 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1017 The TSP is coupled with a companion runtime service in the BL31 firmware,
1018 called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
1019 must be recompiled as well. For more information on SPs and SPDs, see the
1020 `Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
1022 First clean the TF-A build directory to get rid of any previous BL31 binary.
1023 Then to build the TSP image use:
1027 make PLAT=<platform> SPD=tspd all
1029 An additional boot loader binary file is created in the ``build`` directory:
1033 build/<platform>/<build-type>/bl32.bin
1036 Building and using the FIP tool
1037 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1039 Firmware Image Package (FIP) is a packaging format used by TF-A to package
1040 firmware images in a single binary. The number and type of images that should
1041 be packed in a FIP is platform specific and may include TF-A images and other
1042 firmware images required by the platform. For example, most platforms require
1043 a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
1046 The TF-A build system provides the make target ``fip`` to create a FIP file
1047 for the specified platform using the FIP creation tool included in the TF-A
1048 project. Examples below show how to build a FIP file for FVP, packaging TF-A
1055 make PLAT=fvp BL33=<path-to>/bl33.bin fip
1061 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
1063 The resulting FIP may be found in:
1067 build/fvp/<build-type>/fip.bin
1069 For advanced operations on FIP files, it is also possible to independently build
1070 the tool and create or modify FIPs using this tool. To do this, follow these
1073 It is recommended to remove old artifacts before building the tool:
1077 make -C tools/fiptool clean
1083 make [DEBUG=1] [V=1] fiptool
1085 The tool binary can be located in:
1089 ./tools/fiptool/fiptool
1091 Invoking the tool with ``help`` will print a help message with all available
1094 Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1098 ./tools/fiptool/fiptool create \
1099 --tb-fw build/<platform>/<build-type>/bl2.bin \
1100 --soc-fw build/<platform>/<build-type>/bl31.bin \
1103 Example 2: view the contents of an existing Firmware package:
1107 ./tools/fiptool/fiptool info <path-to>/fip.bin
1109 Example 3: update the entries of an existing Firmware package:
1113 # Change the BL2 from Debug to Release version
1114 ./tools/fiptool/fiptool update \
1115 --tb-fw build/<platform>/release/bl2.bin \
1116 build/<platform>/debug/fip.bin
1118 Example 4: unpack all entries from an existing Firmware package:
1122 # Images will be unpacked to the working directory
1123 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1125 Example 5: remove an entry from an existing Firmware package:
1129 ./tools/fiptool/fiptool remove \
1130 --tb-fw build/<platform>/debug/fip.bin
1132 Note that if the destination FIP file exists, the create, update and
1133 remove operations will automatically overwrite it.
1135 The unpack operation will fail if the images already exist at the
1136 destination. In that case, use -f or --force to continue.
1138 More information about FIP can be found in the `Firmware Design`_ document.
1140 Building FIP images with support for Trusted Board Boot
1141 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1143 Trusted Board Boot primarily consists of the following two features:
1145 - Image Authentication, described in `Trusted Board Boot`_, and
1146 - Firmware Update, described in `Firmware Update`_
1148 The following steps should be followed to build FIP and (optionally) FWU_FIP
1149 images with support for these features:
1151 #. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1152 modules by checking out a recent version of the `mbed TLS Repository`_. It
1153 is important to use a version that is compatible with TF-A and fixes any
1154 known security vulnerabilities. See `mbed TLS Security Center`_ for more
1155 information. The latest version of TF-A is tested with tag
1158 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1159 source files the modules depend upon.
1160 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1161 options required to build the mbed TLS sources.
1163 Note that the mbed TLS library is licensed under the Apache version 2.0
1164 license. Using mbed TLS source code will affect the licensing of TF-A
1165 binaries that are built using this library.
1167 #. To build the FIP image, ensure the following command line variables are set
1168 while invoking ``make`` to build TF-A:
1170 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1171 - ``TRUSTED_BOARD_BOOT=1``
1172 - ``GENERATE_COT=1``
1174 In the case of Arm platforms, the location of the ROTPK hash must also be
1175 specified at build time. Two locations are currently supported (see
1176 ``ARM_ROTPK_LOCATION`` build option):
1178 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1179 root-key storage registers present in the platform. On Juno, this
1180 registers are read-only. On FVP Base and Cortex models, the registers
1181 are read-only, but the value can be specified using the command line
1182 option ``bp.trusted_key_storage.public_key`` when launching the model.
1183 On both Juno and FVP models, the default value corresponds to an
1184 ECDSA-SECP256R1 public key hash, whose private part is not currently
1187 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1188 in the Arm platform port. The private/public RSA key pair may be
1189 found in ``plat/arm/board/common/rotpk``.
1191 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1192 in the Arm platform port. The private/public ECDSA key pair may be
1193 found in ``plat/arm/board/common/rotpk``.
1195 Example of command line using RSA development keys:
1199 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1200 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1201 ARM_ROTPK_LOCATION=devel_rsa \
1202 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1203 BL33=<path-to>/<bl33_image> \
1206 The result of this build will be the bl1.bin and the fip.bin binaries. This
1207 FIP will include the certificates corresponding to the Chain of Trust
1208 described in the TBBR-client document. These certificates can also be found
1209 in the output build directory.
1211 #. The optional FWU_FIP contains any additional images to be loaded from
1212 Non-Volatile storage during the `Firmware Update`_ process. To build the
1213 FWU_FIP, any FWU images required by the platform must be specified on the
1214 command line. On Arm development platforms like Juno, these are:
1216 - NS_BL2U. The AP non-secure Firmware Updater image.
1217 - SCP_BL2U. The SCP Firmware Update Configuration image.
1219 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1220 targets using RSA development:
1224 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1225 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1226 ARM_ROTPK_LOCATION=devel_rsa \
1227 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1228 BL33=<path-to>/<bl33_image> \
1229 SCP_BL2=<path-to>/<scp_bl2_image> \
1230 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1231 NS_BL2U=<path-to>/<ns_bl2u_image> \
1235 The BL2U image will be built by default and added to the FWU_FIP.
1236 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1237 to the command line above.
1240 Building and installing the non-secure and SCP FWU images (NS_BL1U,
1241 NS_BL2U and SCP_BL2U) is outside the scope of this document.
1243 The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
1244 Both the FIP and FWU_FIP will include the certificates corresponding to the
1245 Chain of Trust described in the TBBR-client document. These certificates
1246 can also be found in the output build directory.
1248 Building the Certificate Generation Tool
1249 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1251 The ``cert_create`` tool is built as part of the TF-A build process when the
1252 ``fip`` make target is specified and TBB is enabled (as described in the
1253 previous section), but it can also be built separately with the following
1258 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1260 For platforms that require their own IDs in certificate files, the generic
1261 'cert_create' tool can be built with the following command. Note that the target
1262 platform must define its IDs within a ``platform_oid.h`` header file for the
1267 make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
1269 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1270 verbose. The following command should be used to obtain help about the tool:
1274 ./tools/cert_create/cert_create -h
1276 Building a FIP for Juno and FVP
1277 -------------------------------
1279 This section provides Juno and FVP specific instructions to build Trusted
1280 Firmware, obtain the additional required firmware, and pack it all together in
1281 a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
1284 Pre-built binaries for AArch32 are available from Linaro Release 16.12
1285 onwards. Before that release, pre-built binaries are only available for
1289 Follow the full instructions for one platform before switching to a
1290 different one. Mixing instructions for different platforms may result in
1294 The uboot image downloaded by the Linaro workspace script does not always
1295 match the uboot image packaged as BL33 in the corresponding fip file. It is
1296 recommended to use the version that is packaged in the fip file using the
1300 For the FVP, the kernel FDT is packaged in FIP during build and loaded
1301 by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1302 section for more info on selecting the right FDT to use.
1304 #. Clean the working directory
1310 #. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
1312 Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
1313 package included in the Linaro release:
1318 make [DEBUG=1] [V=1] fiptool
1320 # Unpack firmware images from Linaro FIP
1321 ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
1323 The unpack operation will result in a set of binary images extracted to the
1324 current working directory. The SCP_BL2 image corresponds to
1325 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
1328 The fiptool will complain if the images to be unpacked already
1329 exist in the current directory. If that is the case, either delete those
1330 files or use the ``--force`` option to overwrite.
1333 For AArch32, the instructions below assume that nt-fw.bin is a
1334 normal world boot loader that supports AArch32.
1336 #. Build TF-A images and create a new FIP for FVP
1341 make PLAT=fvp BL33=nt-fw.bin all fip
1344 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1346 #. Build TF-A images and create a new FIP for Juno
1350 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1351 as a build parameter.
1355 make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
1359 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1360 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1361 separately for AArch32.
1363 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1364 to the AArch32 Linaro cross compiler.
1368 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1370 - Build BL32 in AArch32.
1374 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1375 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1377 - Save ``bl32.bin`` to a temporary location and clean the build products.
1381 cp <path-to-build>/bl32.bin <path-to-temporary>
1384 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1385 must point to the AArch64 Linaro cross compiler.
1389 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1391 - The following parameters should be used to build BL1 and BL2 in AArch64
1392 and point to the BL32 file.
1396 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
1397 BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
1398 BL32=<path-to-temporary>/bl32.bin all fip
1400 The resulting BL1 and FIP images may be found in:
1405 ./build/juno/release/bl1.bin
1406 ./build/juno/release/fip.bin
1409 ./build/fvp/release/bl1.bin
1410 ./build/fvp/release/fip.bin
1413 Booting Firmware Update images
1414 -------------------------------------
1416 When Firmware Update (FWU) is enabled there are at least 2 new images
1417 that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1423 The new images must be programmed in flash memory by adding
1424 an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1425 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1426 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1427 programming" for more information. User should ensure these do not
1428 overlap with any other entries in the file.
1432 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1433 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1434 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1435 NOR10LOAD: 00000000 ;Image Load Address
1436 NOR10ENTRY: 00000000 ;Image Entry Point
1438 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1439 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1440 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1441 NOR11LOAD: 00000000 ;Image Load Address
1443 The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1444 In the same way, the address ns_bl2u_base_address is the value of
1445 NS_BL2U_BASE - 0x8000000.
1450 The additional fip images must be loaded with:
1454 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1455 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1457 The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1458 In the same way, the address ns_bl2u_base_address is the value of
1462 EL3 payloads alternative boot flow
1463 ----------------------------------
1465 On a pre-production system, the ability to execute arbitrary, bare-metal code at
1466 the highest exception level is required. It allows full, direct access to the
1467 hardware, for example to run silicon soak tests.
1469 Although it is possible to implement some baremetal secure firmware from
1470 scratch, this is a complex task on some platforms, depending on the level of
1471 configuration required to put the system in the expected state.
1473 Rather than booting a baremetal application, a possible compromise is to boot
1474 ``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1475 boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1476 other BL images and passing control to BL31. It reduces the complexity of
1477 developing EL3 baremetal code by:
1479 - putting the system into a known architectural state;
1480 - taking care of platform secure world initialization;
1481 - loading the SCP_BL2 image if required by the platform.
1483 When booting an EL3 payload on Arm standard platforms, the configuration of the
1484 TrustZone controller is simplified such that only region 0 is enabled and is
1485 configured to permit secure access only. This gives full access to the whole
1486 DRAM to the EL3 payload.
1488 The system is left in the same state as when entering BL31 in the default boot
1489 flow. In particular:
1492 - Current state is AArch64;
1493 - Little-endian data access;
1494 - All exceptions disabled;
1498 Booting an EL3 payload
1499 ~~~~~~~~~~~~~~~~~~~~~~
1501 The EL3 payload image is a standalone image and is not part of the FIP. It is
1502 not loaded by TF-A. Therefore, there are 2 possible scenarios:
1504 - The EL3 payload may reside in non-volatile memory (NVM) and execute in
1505 place. In this case, booting it is just a matter of specifying the right
1506 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
1508 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1511 To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1512 used. The infinite loop that it introduces in BL1 stops execution at the right
1513 moment for a debugger to take control of the target and load the payload (for
1514 example, over JTAG).
1516 It is expected that this loading method will work in most cases, as a debugger
1517 connection is usually available in a pre-production system. The user is free to
1518 use any other platform-specific mechanism to load the EL3 payload, though.
1520 Booting an EL3 payload on FVP
1521 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1523 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1524 the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1525 is undefined on the FVP platform and the FVP platform code doesn't clear it.
1526 Therefore, one must modify the way the model is normally invoked in order to
1527 clear the mailbox at start-up.
1529 One way to do that is to create an 8-byte file containing all zero bytes using
1530 the following command:
1534 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1536 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1537 using the following model parameters:
1541 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1542 --data=mailbox.dat@0x04000000 [Foundation FVP]
1544 To provide the model with the EL3 payload image, the following methods may be
1547 #. If the EL3 payload is able to execute in place, it may be programmed into
1548 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1549 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1554 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
1556 On Foundation FVP, there is no flash loader component and the EL3 payload
1557 may be programmed anywhere in flash using method 3 below.
1559 #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1560 command may be used to load the EL3 payload ELF image over JTAG:
1564 load <path-to>/el3-payload.elf
1566 #. The EL3 payload may be pre-loaded in volatile memory using the following
1571 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
1572 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
1574 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1575 used when building TF-A.
1577 Booting an EL3 payload on Juno
1578 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1580 If the EL3 payload is able to execute in place, it may be programmed in flash
1581 memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1582 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1583 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1584 programming" for more information.
1586 Alternatively, the same DS-5 command mentioned in the FVP section above can
1587 be used to load the EL3 payload's ELF file over JTAG on Juno.
1589 Preloaded BL33 alternative boot flow
1590 ------------------------------------
1592 Some platforms have the ability to preload BL33 into memory instead of relying
1593 on TF-A to load it. This may simplify packaging of the normal world code and
1594 improve performance in a development environment. When secure world cold boot
1595 is complete, TF-A simply jumps to a BL33 base address provided at build time.
1597 For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1598 used when compiling TF-A. For example, the following command will create a FIP
1599 without a BL33 and prepare to jump to a BL33 image loaded at address
1604 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1606 Boot of a preloaded kernel image on Base FVP
1607 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1609 The following example uses a simplified boot flow by directly jumping from the
1610 TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1611 useful if both the kernel and the device tree blob (DTB) are already present in
1612 memory (like in FVP).
1614 For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1615 address ``0x82000000``, the firmware can be built like this:
1619 CROSS_COMPILE=aarch64-linux-gnu- \
1620 make PLAT=fvp DEBUG=1 \
1622 ARM_LINUX_KERNEL_AS_BL33=1 \
1623 PRELOADED_BL33_BASE=0x80080000 \
1624 ARM_PRELOADED_DTB_BASE=0x82000000 \
1627 Now, it is needed to modify the DTB so that the kernel knows the address of the
1628 ramdisk. The following script generates a patched DTB from the provided one,
1629 assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1630 script assumes that the user is using a ramdisk image prepared for U-Boot, like
1631 the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1632 offset in ``INITRD_START`` has to be removed.
1638 # Path to the input DTB
1639 KERNEL_DTB=<path-to>/<fdt>
1640 # Path to the output DTB
1641 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1642 # Base address of the ramdisk
1643 INITRD_BASE=0x84000000
1644 # Path to the ramdisk
1645 INITRD=<path-to>/<ramdisk.img>
1647 # Skip uboot header (64 bytes)
1648 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1649 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1650 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1652 CHOSEN_NODE=$(echo \
1655 linux,initrd-start = <${INITRD_START}>; \
1656 linux,initrd-end = <${INITRD_END}>; \
1660 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1661 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
1663 And the FVP binary can be run with the following command:
1667 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1668 -C pctl.startup=0.0.0.0 \
1669 -C bp.secure_memory=1 \
1670 -C cluster0.NUM_CORES=4 \
1671 -C cluster1.NUM_CORES=4 \
1672 -C cache_state_modelled=1 \
1673 -C cluster0.cpu0.RVBAR=0x04020000 \
1674 -C cluster0.cpu1.RVBAR=0x04020000 \
1675 -C cluster0.cpu2.RVBAR=0x04020000 \
1676 -C cluster0.cpu3.RVBAR=0x04020000 \
1677 -C cluster1.cpu0.RVBAR=0x04020000 \
1678 -C cluster1.cpu1.RVBAR=0x04020000 \
1679 -C cluster1.cpu2.RVBAR=0x04020000 \
1680 -C cluster1.cpu3.RVBAR=0x04020000 \
1681 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1682 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1683 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1684 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1686 Boot of a preloaded kernel image on Juno
1687 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1689 The Trusted Firmware must be compiled in a similar way as for FVP explained
1690 above. The process to load binaries to memory is the one explained in
1691 `Booting an EL3 payload on Juno`_.
1693 Running the software on FVP
1694 ---------------------------
1696 The latest version of the AArch64 build of TF-A has been tested on the following
1697 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1698 (64-bit host machine only).
1701 The FVP models used are Version 11.6 Build 45, unless otherwise stated.
1703 - ``FVP_Base_AEMv8A-AEMv8A``
1704 - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
1705 - ``FVP_Base_RevC-2xAEMv8A``
1706 - ``FVP_Base_Cortex-A32x4``
1707 - ``FVP_Base_Cortex-A35x4``
1708 - ``FVP_Base_Cortex-A53x4``
1709 - ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1710 - ``FVP_Base_Cortex-A55x4``
1711 - ``FVP_Base_Cortex-A57x1-A53x1``
1712 - ``FVP_Base_Cortex-A57x2-A53x4``
1713 - ``FVP_Base_Cortex-A57x4-A53x4``
1714 - ``FVP_Base_Cortex-A57x4``
1715 - ``FVP_Base_Cortex-A72x4-A53x4``
1716 - ``FVP_Base_Cortex-A72x4``
1717 - ``FVP_Base_Cortex-A73x4-A53x4``
1718 - ``FVP_Base_Cortex-A73x4``
1719 - ``FVP_Base_Cortex-A75x4``
1720 - ``FVP_Base_Cortex-A76x4``
1721 - ``FVP_Base_Cortex-A76AEx4``
1722 - ``FVP_Base_Cortex-A76AEx8``
1723 - ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
1724 - ``FVP_Base_Neoverse-N1x4``
1725 - ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
1726 - ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
1727 - ``FVP_RD_E1Edge`` (Version 11.3 build 42)
1729 - ``Foundation_Platform``
1731 The latest version of the AArch32 build of TF-A has been tested on the following
1732 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1733 (64-bit host machine only).
1735 - ``FVP_Base_AEMv8A-AEMv8A``
1736 - ``FVP_Base_Cortex-A32x4``
1739 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1740 is not compatible with legacy GIC configurations. Therefore this FVP does not
1741 support these legacy GIC configurations.
1744 The build numbers quoted above are those reported by launching the FVP
1745 with the ``--version`` parameter.
1748 Linaro provides a ramdisk image in prebuilt FVP configurations and full
1749 file systems that can be downloaded separately. To run an FVP with a virtio
1750 file system image an additional FVP configuration option
1751 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1755 The software will not work on Version 1.0 of the Foundation FVP.
1756 The commands below would report an ``unhandled argument`` error in this case.
1759 FVPs can be launched with ``--cadi-server`` option such that a
1760 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
1764 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
1765 the internal synchronisation timings changed compared to older versions of
1766 the models. The models can be launched with ``-Q 100`` option if they are
1767 required to match the run time characteristics of the older versions.
1769 The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1770 downloaded for free from `Arm's website`_.
1772 The Cortex-A models listed above are also available to download from
1775 Please refer to the FVP documentation for a detailed description of the model
1776 parameter options. A brief description of the important ones that affect TF-A
1777 and normal world software behavior is provided below.
1779 Obtaining the Flattened Device Trees
1780 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1782 Depending on the FVP configuration and Linux configuration used, different
1783 FDT files are required. FDT source files for the Foundation and Base FVPs can
1784 be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1785 a subset of the Base FVP components. For example, the Foundation FVP lacks
1786 CLCD and MMC support, and has only one CPU cluster.
1789 It is not recommended to use the FDTs built along the kernel because not
1790 all FDTs are available from there.
1792 The dynamic configuration capability is enabled in the firmware for FVPs.
1793 This means that the firmware can authenticate and load the FDT if present in
1794 FIP. A default FDT is packaged into FIP during the build based on
1795 the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1796 or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1797 `Arm FVP platform specific build options`_ section for detail on the options).
1799 - ``fvp-base-gicv2-psci.dts``
1801 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1802 affinities and with Base memory map configuration.
1804 - ``fvp-base-gicv2-psci-aarch32.dts``
1806 For use with models such as the Cortex-A32 Base FVPs without shifted
1807 affinities and running Linux in AArch32 state with Base memory map
1810 - ``fvp-base-gicv3-psci.dts``
1812 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1813 affinities and with Base memory map configuration and Linux GICv3 support.
1815 - ``fvp-base-gicv3-psci-1t.dts``
1817 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1818 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1820 - ``fvp-base-gicv3-psci-dynamiq.dts``
1822 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1823 single cluster, single threaded CPUs, Base memory map configuration and Linux
1826 - ``fvp-base-gicv3-psci-aarch32.dts``
1828 For use with models such as the Cortex-A32 Base FVPs without shifted
1829 affinities and running Linux in AArch32 state with Base memory map
1830 configuration and Linux GICv3 support.
1832 - ``fvp-foundation-gicv2-psci.dts``
1834 For use with Foundation FVP with Base memory map configuration.
1836 - ``fvp-foundation-gicv3-psci.dts``
1838 (Default) For use with Foundation FVP with Base memory map configuration
1839 and Linux GICv3 support.
1841 Running on the Foundation FVP with reset to BL1 entrypoint
1842 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1844 The following ``Foundation_Platform`` parameters should be used to boot Linux with
1845 4 CPUs using the AArch64 build of TF-A.
1849 <path-to>/Foundation_Platform \
1855 --data="<path-to>/<bl1-binary>"@0x0 \
1856 --data="<path-to>/<FIP-binary>"@0x08000000 \
1857 --data="<path-to>/<kernel-binary>"@0x80080000 \
1858 --data="<path-to>/<ramdisk-binary>"@0x84000000
1862 - BL1 is loaded at the start of the Trusted ROM.
1863 - The Firmware Image Package is loaded at the start of NOR FLASH0.
1864 - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1865 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
1866 - The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1867 and enable the GICv3 device in the model. Note that without this option,
1868 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1869 is not supported by TF-A.
1870 - In order for TF-A to run correctly on the Foundation FVP, the architecture
1871 versions must match. The Foundation FVP defaults to the highest v8.x
1872 version it supports but the default build for TF-A is for v8.0. To avoid
1873 issues either start the Foundation FVP to use v8.0 architecture using the
1874 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1877 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1878 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1880 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
1881 with 8 CPUs using the AArch64 build of TF-A.
1885 <path-to>/FVP_Base_RevC-2xAEMv8A \
1886 -C pctl.startup=0.0.0.0 \
1887 -C bp.secure_memory=1 \
1888 -C bp.tzc_400.diagnostics=1 \
1889 -C cluster0.NUM_CORES=4 \
1890 -C cluster1.NUM_CORES=4 \
1891 -C cache_state_modelled=1 \
1892 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1893 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1894 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1895 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1898 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
1899 a specific DTS for all the CPUs to be loaded.
1901 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1902 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1904 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1905 with 8 CPUs using the AArch32 build of TF-A.
1909 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1910 -C pctl.startup=0.0.0.0 \
1911 -C bp.secure_memory=1 \
1912 -C bp.tzc_400.diagnostics=1 \
1913 -C cluster0.NUM_CORES=4 \
1914 -C cluster1.NUM_CORES=4 \
1915 -C cache_state_modelled=1 \
1916 -C cluster0.cpu0.CONFIG64=0 \
1917 -C cluster0.cpu1.CONFIG64=0 \
1918 -C cluster0.cpu2.CONFIG64=0 \
1919 -C cluster0.cpu3.CONFIG64=0 \
1920 -C cluster1.cpu0.CONFIG64=0 \
1921 -C cluster1.cpu1.CONFIG64=0 \
1922 -C cluster1.cpu2.CONFIG64=0 \
1923 -C cluster1.cpu3.CONFIG64=0 \
1924 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1925 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1926 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1927 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1929 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1930 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1932 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1933 boot Linux with 8 CPUs using the AArch64 build of TF-A.
1937 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1938 -C pctl.startup=0.0.0.0 \
1939 -C bp.secure_memory=1 \
1940 -C bp.tzc_400.diagnostics=1 \
1941 -C cache_state_modelled=1 \
1942 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1943 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1944 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1945 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1947 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1948 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1950 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1951 boot Linux with 4 CPUs using the AArch32 build of TF-A.
1955 <path-to>/FVP_Base_Cortex-A32x4 \
1956 -C pctl.startup=0.0.0.0 \
1957 -C bp.secure_memory=1 \
1958 -C bp.tzc_400.diagnostics=1 \
1959 -C cache_state_modelled=1 \
1960 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1961 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1962 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1963 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1965 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1966 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1968 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
1969 with 8 CPUs using the AArch64 build of TF-A.
1973 <path-to>/FVP_Base_RevC-2xAEMv8A \
1974 -C pctl.startup=0.0.0.0 \
1975 -C bp.secure_memory=1 \
1976 -C bp.tzc_400.diagnostics=1 \
1977 -C cluster0.NUM_CORES=4 \
1978 -C cluster1.NUM_CORES=4 \
1979 -C cache_state_modelled=1 \
1980 -C cluster0.cpu0.RVBAR=0x04010000 \
1981 -C cluster0.cpu1.RVBAR=0x04010000 \
1982 -C cluster0.cpu2.RVBAR=0x04010000 \
1983 -C cluster0.cpu3.RVBAR=0x04010000 \
1984 -C cluster1.cpu0.RVBAR=0x04010000 \
1985 -C cluster1.cpu1.RVBAR=0x04010000 \
1986 -C cluster1.cpu2.RVBAR=0x04010000 \
1987 -C cluster1.cpu3.RVBAR=0x04010000 \
1988 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
1989 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
1990 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
1991 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
1992 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1993 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1997 - If Position Independent Executable (PIE) support is enabled for BL31
1998 in this config, it can be loaded at any valid address for execution.
2000 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
2001 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
2002 parameter is needed to load the individual bootloader images in memory.
2003 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
2004 Payload. For the same reason, the FDT needs to be compiled from the DT source
2005 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
2008 - The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
2009 specific DTS for all the CPUs to be loaded.
2011 - The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
2012 X and Y are the cluster and CPU numbers respectively, is used to set the
2013 reset vector for each core.
2015 - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
2016 changing the value of
2017 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
2020 Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
2021 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2023 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
2024 with 8 CPUs using the AArch32 build of TF-A.
2028 <path-to>/FVP_Base_AEMv8A-AEMv8A \
2029 -C pctl.startup=0.0.0.0 \
2030 -C bp.secure_memory=1 \
2031 -C bp.tzc_400.diagnostics=1 \
2032 -C cluster0.NUM_CORES=4 \
2033 -C cluster1.NUM_CORES=4 \
2034 -C cache_state_modelled=1 \
2035 -C cluster0.cpu0.CONFIG64=0 \
2036 -C cluster0.cpu1.CONFIG64=0 \
2037 -C cluster0.cpu2.CONFIG64=0 \
2038 -C cluster0.cpu3.CONFIG64=0 \
2039 -C cluster1.cpu0.CONFIG64=0 \
2040 -C cluster1.cpu1.CONFIG64=0 \
2041 -C cluster1.cpu2.CONFIG64=0 \
2042 -C cluster1.cpu3.CONFIG64=0 \
2043 -C cluster0.cpu0.RVBAR=0x04002000 \
2044 -C cluster0.cpu1.RVBAR=0x04002000 \
2045 -C cluster0.cpu2.RVBAR=0x04002000 \
2046 -C cluster0.cpu3.RVBAR=0x04002000 \
2047 -C cluster1.cpu0.RVBAR=0x04002000 \
2048 -C cluster1.cpu1.RVBAR=0x04002000 \
2049 -C cluster1.cpu2.RVBAR=0x04002000 \
2050 -C cluster1.cpu3.RVBAR=0x04002000 \
2051 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2052 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2053 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2054 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2055 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2058 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
2059 It should match the address programmed into the RVBAR register as well.
2061 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
2062 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2064 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
2065 boot Linux with 8 CPUs using the AArch64 build of TF-A.
2069 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
2070 -C pctl.startup=0.0.0.0 \
2071 -C bp.secure_memory=1 \
2072 -C bp.tzc_400.diagnostics=1 \
2073 -C cache_state_modelled=1 \
2074 -C cluster0.cpu0.RVBARADDR=0x04010000 \
2075 -C cluster0.cpu1.RVBARADDR=0x04010000 \
2076 -C cluster0.cpu2.RVBARADDR=0x04010000 \
2077 -C cluster0.cpu3.RVBARADDR=0x04010000 \
2078 -C cluster1.cpu0.RVBARADDR=0x04010000 \
2079 -C cluster1.cpu1.RVBARADDR=0x04010000 \
2080 -C cluster1.cpu2.RVBARADDR=0x04010000 \
2081 -C cluster1.cpu3.RVBARADDR=0x04010000 \
2082 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2083 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
2084 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2085 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2086 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2087 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2089 Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
2090 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2092 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
2093 boot Linux with 4 CPUs using the AArch32 build of TF-A.
2097 <path-to>/FVP_Base_Cortex-A32x4 \
2098 -C pctl.startup=0.0.0.0 \
2099 -C bp.secure_memory=1 \
2100 -C bp.tzc_400.diagnostics=1 \
2101 -C cache_state_modelled=1 \
2102 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2103 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2104 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2105 -C cluster0.cpu3.RVBARADDR=0x04002000 \
2106 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2107 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2108 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2109 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2110 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2112 Running the software on Juno
2113 ----------------------------
2115 This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
2117 To execute the software stack on Juno, the version of the Juno board recovery
2118 image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2119 earlier version installed or are unsure which version is installed, please
2120 re-install the recovery image by following the
2121 `Instructions for using Linaro's deliverables on Juno`_.
2123 Preparing TF-A images
2124 ~~~~~~~~~~~~~~~~~~~~~
2126 After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2127 ``SOFTWARE/`` directory of the Juno SD card.
2129 Other Juno software information
2130 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2132 Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
2133 software information. Please also refer to the `Juno Getting Started Guide`_ to
2134 get more detailed information about the Juno Arm development platform and how to
2137 Testing SYSTEM SUSPEND on Juno
2138 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2140 The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2141 to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2142 on Juno, at the linux shell prompt, issue the following command:
2146 echo +10 > /sys/class/rtc/rtc0/wakealarm
2147 echo -n mem > /sys/power/state
2149 The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2150 wakeup interrupt from RTC.
2154 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
2156 .. _arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
2157 .. _Linaro: `Linaro Release Notes`_
2158 .. _Linaro Release: `Linaro Release Notes`_
2159 .. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
2160 .. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
2161 .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
2162 .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
2163 .. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
2164 .. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
2165 .. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
2166 .. _Linux master tree: https://github.com/torvalds/linux/tree/master/
2167 .. _Dia: https://wiki.gnome.org/Apps/Dia/Download
2168 .. _here: psci-lib-integration-guide.rst
2169 .. _Trusted Board Boot: ../design/trusted-board-boot.rst
2170 .. _TB_FW_CONFIG for FVP: ../../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
2171 .. _Secure-EL1 Payloads and Dispatchers: ../design/firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
2172 .. _Firmware Update: ../components/firmware-update.rst
2173 .. _Firmware Design: ../design/firmware-design.rst
2174 .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2175 .. _mbed TLS Security Center: https://tls.mbed.org/security
2176 .. _Arm's website: `FVP models`_
2177 .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
2178 .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
2179 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2180 .. _Secure Partition Manager Design guide: ../components/secure-partition-manager-design.rst
2181 .. _`Trusted Firmware-A Coding Guidelines`: ../process/coding-guidelines.rst
2182 .. _Library at ROM: ../components/romlib-design.rst