4 This document describes how to build Trusted Firmware-A (TF-A) and run it with a
5 tested set of other software components using defined configurations on the Juno
6 Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
7 possible to use other software components, configurations and platforms but that
8 is outside the scope of this document.
10 This document assumes that the reader has previous experience running a fully
11 bootable Linux software stack on Juno or FVP using the prebuilt binaries and
12 filesystems provided by `Linaro`_. Further information may be found in the
13 `Linaro instructions`_. It also assumes that the user understands the role of
14 the different software components required to boot a Linux system:
16 - Specific firmware images required by the platform (e.g. SCP firmware on Juno)
17 - Normal world bootloader (e.g. UEFI or U-Boot)
22 This document also assumes that the user is familiar with the `FVP models`_ and
23 the different command line options available to launch the model.
25 This document should be used in conjunction with the `Firmware Design`_.
27 Host machine requirements
28 -------------------------
30 The minimum recommended machine specification for building the software and
31 running the FVP models is a dual-core processor running at 2GHz with 12GB of
32 RAM. For best performance, use a machine with a quad-core processor running at
33 2.6GHz with 16GB of RAM.
35 The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
36 building the software were installed from that distribution unless otherwise
39 The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
40 Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
45 Install the required packages to build TF-A with the following command:
49 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
51 TF-A has been tested with Linaro Release 18.04.
53 Download and install the AArch32 (arm-eabi) or AArch64 little-endian
54 (aarch64-linux-gnu) GCC cross compiler. If you would like to use the latest
55 features available, download GCC 8.3-2019.03 compiler from
56 `arm Developer page`_. Otherwise, the `Linaro Release Notes`_ documents which
57 version of the compiler to use for a given Linaro Release. Also, these
58 `Linaro instructions`_ provide further guidance and a script, which can be used
59 to download Linaro deliverables automatically.
61 Optionally, TF-A can be built using clang version 4.0 or newer or Arm
62 Compiler 6. See instructions below on how to switch the default compiler.
64 In addition, the following optional packages and tools may be needed:
66 - ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
67 Tree (FDT) source files (``.dts`` files) provided with this software. The
68 version of dtc must be 1.4.6 or above.
70 - For debugging, Arm `Development Studio 5 (DS-5)`_.
72 - To create and modify the diagram files included in the documentation, `Dia`_.
73 This tool can be found in most Linux distributions. Inkscape is needed to
74 generate the actual \*.png files.
76 Getting the TF-A source code
77 ----------------------------
79 Clone the repository from the Gerrit server. The project details may be found
80 on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
81 commit-msg hook`" clone method, which will setup the git commit hook that
82 automatically generates and inserts appropriate `Change-Id:` lines in your
85 Checking source code style
86 ~~~~~~~~~~~~~~~~~~~~~~~~~~
88 Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
89 source, for submission to the project, the source must be in compliance with
92 Additional, project-specific guidelines are defined in the `Trusted Firmware-A
93 Coding Guidelines`_ document.
95 To assist with coding style compliance, the project Makefile contains two
96 targets which both utilise the `checkpatch.pl` script that ships with the Linux
97 source tree. The project also defines certain *checkpatch* options in the
98 ``.checkpatch.conf`` file in the top-level directory.
101 Checkpatch errors will gate upstream merging of pull requests.
102 Checkpatch warnings will not gate merging but should be reviewed and fixed if
105 To check the entire source tree, you must first download copies of
106 ``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
107 in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
108 environment variable to point to ``checkpatch.pl`` (with the other 2 files in
109 the same directory) and build the `checkcodebase` target:
113 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
115 To just check the style on the files that differ between your local branch and
116 the remote master, use:
120 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
122 If you wish to check your patch against something other than the remote master,
123 set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
124 is set to ``origin/master``.
129 - Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
130 to the Linaro cross compiler.
136 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
142 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
144 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
145 ``CC`` needs to point to the clang or armclang binary, which will
146 also select the clang or armclang assembler. Be aware that the
147 GNU linker is used by default. In case of being needed the linker
148 can be overridden using the ``LD`` variable. Clang linker version 6 is
149 known to work with TF-A.
151 In both cases ``CROSS_COMPILE`` should be set as described above.
153 Arm Compiler 6 will be selected when the base name of the path assigned
154 to ``CC`` matches the string 'armclang'.
156 For AArch64 using Arm Compiler 6:
160 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
161 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
163 Clang will be selected when the base name of the path assigned to ``CC``
164 contains the string 'clang'. This is to allow both clang and clang-X.Y
167 For AArch64 using clang:
171 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
172 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
174 - Change to the root directory of the TF-A source tree and build.
180 make PLAT=<platform> all
186 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
190 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
191 `Summary of build options`_ for more information on available build
194 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
196 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
197 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
198 provided by TF-A to demonstrate how PSCI Library can be integrated with
199 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
200 include other runtime services, for example Trusted OS services. A guide
201 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
204 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
205 image, is not compiled in by default. Refer to the
206 `Building the Test Secure Payload`_ section below.
208 - By default this produces a release version of the build. To produce a
209 debug version instead, refer to the "Debugging options" section below.
211 - The build process creates products in a ``build`` directory tree, building
212 the objects and binaries for each boot loader stage in separate
213 sub-directories. The following boot loader binary files are created
214 from the corresponding ELF files:
216 - ``build/<platform>/<build-type>/bl1.bin``
217 - ``build/<platform>/<build-type>/bl2.bin``
218 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
219 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
221 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
222 is either ``debug`` or ``release``. The actual number of images might differ
223 depending on the platform.
225 - Build products for a specific build variant can be removed using:
229 make DEBUG=<D> PLAT=<platform> clean
231 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
233 The build tree can be removed completely using:
239 Summary of build options
240 ~~~~~~~~~~~~~~~~~~~~~~~~
242 The TF-A build system supports the following build options. Unless mentioned
243 otherwise, these options are expected to be specified at the build command
244 line and are not to be modified in any component makefiles. Note that the
245 build system doesn't track dependency for build options. Therefore, if any of
246 the build options are changed from a previous build, a clean build must be
252 - ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
253 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
254 code having a smaller resulting size.
256 - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
257 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
258 directory containing the SP source, relative to the ``bl32/``; the directory
259 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
261 - ``ARCH`` : Choose the target build architecture for TF-A. It can take either
262 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
265 - ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
266 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
267 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
270 - ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
271 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
272 *Armv8 Architecture Extensions* in `Firmware Design`_.
274 - ``BL2``: This is an optional build option which specifies the path to BL2
275 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
278 - ``BL2U``: This is an optional build option which specifies the path to
279 BL2U image. In this case, the BL2U in TF-A will not be built.
281 - ``BL2_AT_EL3``: This is an optional build option that enables the use of
282 BL2 at EL3 execution level.
284 - ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
285 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
286 the RW sections in RAM, while leaving the RO sections in place. This option
287 enable this use-case. For now, this option is only supported when BL2_AT_EL3
290 - ``BL2_INV_DCACHE``: This is an optional build option which control dcache
291 invalidation upon BL2 entry. Some platform cannot handle cache operations
292 during entry as the coherency unit is not yet initialized. This may cause
293 crashing. Leaving this option to '1' (default) will allow the operation.
294 This option is only relevant when BL2_AT_EL3 is set to '1'.
296 - ``BL31``: This is an optional build option which specifies the path to
297 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
300 - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
301 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
302 this file name will be used to save the key.
304 - ``BL32``: This is an optional build option which specifies the path to
305 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
308 - ``BL32_EXTRA1``: This is an optional build option which specifies the path to
309 Trusted OS Extra1 image for the ``fip`` target.
311 - ``BL32_EXTRA2``: This is an optional build option which specifies the path to
312 Trusted OS Extra2 image for the ``fip`` target.
314 - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
315 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
316 this file name will be used to save the key.
318 - ``BL33``: Path to BL33 image in the host file system. This is mandatory for
319 ``fip`` target in case TF-A BL2 is used.
321 - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
322 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
323 this file name will be used to save the key.
325 - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
326 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
327 If enabled, it is needed to use a compiler (e.g GCC 9.1 and later versions) that
328 supports the option ``-mbranch-protection``.
329 Selects the branch protection features to use:
330 - 0: Default value turns off all types of branch protection
331 - 1: Enables all types of branch protection features
332 - 2: Return address signing to its standard level
333 - 3: Extend the signing to include leaf functions
335 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
336 and resulting PAuth/BTI features.
338 +-------+--------------+-------+-----+
339 | Value | GCC option | PAuth | BTI |
340 +=======+==============+=======+=====+
342 +-------+--------------+-------+-----+
343 | 1 | standard | Y | Y |
344 +-------+--------------+-------+-----+
345 | 2 | pac-ret | Y | N |
346 +-------+--------------+-------+-----+
347 | 3 | pac-ret+leaf | Y | N |
348 +-------+--------------+-------+-----+
350 This option defaults to 0 and this is an experimental feature.
351 Note that Pointer Authentication is enabled for Non-secure world
352 irrespective of the value of this option if the CPU supports it.
354 - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
355 compilation of each build. It must be set to a C string (including quotes
356 where applicable). Defaults to a string that contains the time and date of
359 - ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
360 build to be uniquely identified. Defaults to the current git commit id.
362 - ``CFLAGS``: Extra user options appended on the compiler's command line in
363 addition to the options set by the build system.
365 - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
366 release several CPUs out of reset. It can take either 0 (several CPUs may be
367 brought up) or 1 (only one CPU will ever be brought up during cold reset).
368 Default is 0. If the platform always brings up a single CPU, there is no
369 need to distinguish between primary and secondary CPUs and the boot path can
370 be optimised. The ``plat_is_my_cpu_primary()`` and
371 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
372 to be implemented in this case.
374 - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
375 register state when an unexpected exception occurs during execution of
376 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
377 this is only enabled for a debug build of the firmware.
379 - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
380 certificate generation tool to create new keys in case no valid keys are
381 present or specified. Allowed options are '0' or '1'. Default is '1'.
383 - ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
384 the AArch32 system registers to be included when saving and restoring the
385 CPU context. The option must be set to 0 for AArch64-only platforms (that
386 is on hardware that does not implement AArch32, or at least not at EL1 and
387 higher ELs). Default value is 1.
389 - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
390 registers to be included when saving and restoring the CPU context. Default
393 - ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
394 ARMv8.5 Memory Tagging Extension. A value of 0 will disable
395 saving/reloading and restrict the use of MTE to the normal world if the
396 CPU has support, while a value of 1 enables the saving/reloading, allowing
397 the use of MTE in both the secure and non-secure worlds. Default is 0
398 (disabled) and this feature is experimental.
400 - ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
401 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
402 registers to be included when saving and restoring the CPU context as
403 part of world switch. Default value is 0 and this is an experimental feature.
404 Note that Pointer Authentication is enabled for Non-secure world irrespective
405 of the value of this flag if the CPU supports it.
407 - ``DEBUG``: Chooses between a debug and release build. It can take either 0
408 (release) or 1 (debug) as values. 0 is the default.
410 - ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
411 of the binary image. If set to 1, then only the ELF image is built.
414 - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
415 Board Boot authentication at runtime. This option is meant to be enabled only
416 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
417 flag has to be enabled. 0 is the default.
419 - ``E``: Boolean option to make warnings into errors. Default is 1.
421 - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
422 the normal boot flow. It must specify the entry point address of the EL3
423 payload. Please refer to the "Booting an EL3 payload" section for more
426 - ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
427 This is an optional architectural feature available on v8.4 onwards. Some
428 v8.2 implementations also implement an AMU and this option can be used to
429 enable this feature on those systems as well. Default is 0.
431 - ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
432 are compiled out. For debug builds, this option defaults to 1, and calls to
433 ``assert()`` are left in place. For release builds, this option defaults to 0
434 and calls to ``assert()`` function are compiled out. This option can be set
435 independently of ``DEBUG``. It can also be used to hide any auxiliary code
436 that is only required for the assertion and does not fit in the assertion
439 - ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
440 dumps or not. It is supported in both AArch64 and AArch32. However, in
441 AArch32 the format of the frame records are not defined in the AAPCS and they
442 are defined by the implementation. This implementation of backtrace only
443 supports the format used by GCC when T32 interworking is disabled. For this
444 reason enabling this option in AArch32 will force the compiler to only
445 generate A32 code. This option is enabled by default only in AArch64 debug
446 builds, but this behaviour can be overridden in each platform's Makefile or
447 in the build command line.
449 - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
450 feature. MPAM is an optional Armv8.4 extension that enables various memory
451 system components and resources to define partitions; software running at
452 various ELs can assign themselves to desired partition to control their
455 When this option is set to ``1``, EL3 allows lower ELs to access their own
456 MPAM registers without trapping into EL3. This option doesn't make use of
457 partitioning in EL3, however. Platform initialisation code should configure
458 and use partitions in EL3 as required. This option defaults to ``0``.
460 - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
461 support within generic code in TF-A. This option is currently only supported
462 in BL31. Default is 0.
464 - ``ENABLE_PMF``: Boolean option to enable support for optional Performance
465 Measurement Framework(PMF). Default is 0.
467 - ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
468 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
469 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
470 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
473 - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
474 instrumentation which injects timestamp collection points into TF-A to
475 allow runtime performance to be measured. Currently, only PSCI is
476 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
477 as well. Default is 0.
479 - ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
480 extensions. This is an optional architectural feature for AArch64.
481 The default is 1 but is automatically disabled when the target architecture
484 - ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
485 Refer to the `Secure Partition Manager Design guide`_ for more details about
486 this feature. Default is 0.
488 - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
489 (SVE) for the Non-secure world only. SVE is an optional architectural feature
490 for AArch64. Note that when SVE is enabled for the Non-secure world, access
491 to SIMD and floating-point functionality from the Secure world is disabled.
492 This is to avoid corruption of the Non-secure world data in the Z-registers
493 which are aliased by the SIMD and FP registers. The build option is not
494 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
495 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
496 1. The default is 1 but is automatically disabled when the target
497 architecture is AArch32.
499 - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
500 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
501 default value is set to "none". "strong" is the recommended stack protection
502 level if this feature is desired. "none" disables the stack protection. For
503 all values other than "none", the ``plat_get_stack_protector_canary()``
504 platform hook needs to be implemented. The value is passed as the last
505 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
507 - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
508 deprecated platform APIs, helper functions or drivers within Trusted
509 Firmware as error. It can take the value 1 (flag the use of deprecated
510 APIs as error) or 0. The default is 0.
512 - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
513 targeted at EL3. When set ``0`` (default), no exceptions are expected or
514 handled at EL3, and a panic will result. This is supported only for AArch64
517 - ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
518 injection from lower ELs, and this build option enables lower ELs to use
519 Error Records accessed via System Registers to inject faults. This is
520 applicable only to AArch64 builds.
522 This feature is intended for testing purposes only, and is advisable to keep
523 disabled for production images.
525 - ``FIP_NAME``: This is an optional build option which specifies the FIP
526 filename for the ``fip`` target. Default is ``fip.bin``.
528 - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
529 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
531 - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
532 tool to create certificates as per the Chain of Trust described in
533 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
534 include the certificates in the FIP and FWU_FIP. Default value is '0'.
536 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
537 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
538 the corresponding certificates, and to include those certificates in the
541 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
542 images will not include support for Trusted Board Boot. The FIP will still
543 include the corresponding certificates. This FIP can be used to verify the
544 Chain of Trust on the host machine through other mechanisms.
546 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
547 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
548 will not include the corresponding certificates, causing a boot failure.
550 - ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
551 inherent support for specific EL3 type interrupts. Setting this build option
552 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
553 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
554 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
555 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
556 the Secure Payload interrupts needs to be synchronously handed over to Secure
557 EL1 for handling. The default value of this option is ``0``, which means the
558 Group 0 interrupts are assumed to be handled by Secure EL1.
560 .. __: `platform-interrupt-controller-API.rst`
561 .. __: `interrupt-framework-design.rst`
563 - ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
564 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
565 ``0`` (default), these exceptions will be trapped in the current exception
566 level (or in EL1 if the current exception level is EL0).
568 - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
569 software operations are required for CPUs to enter and exit coherency.
570 However, newer systems exist where CPUs' entry to and exit from coherency
571 is managed in hardware. Such systems require software to only initiate these
572 operations, and the rest is managed in hardware, minimizing active software
573 management. In such systems, this boolean option enables TF-A to carry out
574 build and run-time optimizations during boot and power management operations.
575 This option defaults to 0 and if it is enabled, then it implies
576 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
578 If this flag is disabled while the platform which TF-A is compiled for
579 includes cores that manage coherency in hardware, then a compilation error is
580 generated. This is based on the fact that a system cannot have, at the same
581 time, cores that manage coherency in hardware and cores that don't. In other
582 words, a platform cannot have, at the same time, cores that require
583 ``HW_ASSISTED_COHERENCY=1`` and cores that require
584 ``HW_ASSISTED_COHERENCY=0``.
586 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
587 translation library (xlat tables v2) must be used; version 1 of translation
588 library is not supported.
590 - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
591 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
592 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
593 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
596 - ``KEY_ALG``: This build flag enables the user to select the algorithm to be
597 used for generating the PKCS keys and subsequent signing of the certificate.
598 It accepts 2 values: ``rsa`` and ``ecdsa``. The default value of this flag
599 is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
601 - ``KEY_SIZE``: This build flag enables the user to select the key size for
602 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE``
603 depend on the chosen algorithm.
605 +-----------+------------------------------------+
606 | KEY_ALG | Possible key sizes |
607 +===========+====================================+
608 | rsa | 1024, 2048 (default), 3072, 4096 |
609 +-----------+------------------------------------+
610 | ecdsa | unavailable |
611 +-----------+------------------------------------+
613 - ``HASH_ALG``: This build flag enables the user to select the secure hash
614 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
615 The default value of this flag is ``sha256``.
617 - ``LDFLAGS``: Extra user options appended to the linkers' command line in
618 addition to the one set by the build system.
620 - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
621 output compiled into the build. This should be one of the following:
627 20 (LOG_LEVEL_NOTICE)
628 30 (LOG_LEVEL_WARNING)
630 50 (LOG_LEVEL_VERBOSE)
632 All log output up to and including the selected log level is compiled into
633 the build. The default value is 40 in debug builds and 20 in release builds.
635 - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
636 specifies the file that contains the Non-Trusted World private key in PEM
637 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
639 - ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
640 optional. It is only needed if the platform makefile specifies that it
641 is required in order to build the ``fwu_fip`` target.
643 - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
644 contents upon world switch. It can take either 0 (don't save and restore) or
645 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
646 wants the timer registers to be saved and restored.
648 - ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
649 for the BL image. It can be either 0 (include) or 1 (remove). The default
652 - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
653 the underlying hardware is not a full PL011 UART but a minimally compliant
654 generic UART, which is a subset of the PL011. The driver will not access
655 any register that is not part of the SBSA generic UART specification.
656 Default value is 0 (a full PL011 compliant UART is present).
658 - ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
659 must be subdirectory of any depth under ``plat/``, and must contain a
660 platform makefile named ``platform.mk``. For example, to build TF-A for the
661 Arm Juno board, select PLAT=juno.
663 - ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
664 instead of the normal boot flow. When defined, it must specify the entry
665 point address for the preloaded BL33 image. This option is incompatible with
666 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
667 over ``PRELOADED_BL33_BASE``.
669 - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
670 vector address can be programmed or is fixed on the platform. It can take
671 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
672 programmable reset address, it is expected that a CPU will start executing
673 code directly at the right address, both on a cold and warm reset. In this
674 case, there is no need to identify the entrypoint on boot and the boot path
675 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
676 does not need to be implemented in this case.
678 - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
679 possible for the PSCI power-state parameter: original and extended State-ID
680 formats. This flag if set to 1, configures the generic PSCI layer to use the
681 extended format. The default value of this flag is 0, which means by default
682 the original power-state format is used by the PSCI implementation. This flag
683 should be specified by the platform makefile and it governs the return value
684 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
685 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
688 - ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
689 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
692 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
695 This option is disabled by default.
697 - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
698 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
699 entrypoint) or 1 (CPU reset to BL31 entrypoint).
700 The default value is 0.
702 - ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
703 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
704 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
705 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
707 - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
708 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
709 file name will be used to save the key.
711 - ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It
712 can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap',
713 gcc and clang will insert calls to ``__builtin_trap`` on detected
714 undefined behaviour, which defaults to a ``brk`` instruction. When using
715 'on', undefined behaviour is translated to a call to special handlers which
716 prints the exact location of the problem and its cause and then panics.
719 Because of the space penalty of the Undefined Behaviour sanitizer,
720 this option will increase the size of the binary. Depending on the
721 memory constraints of the target platform, it may not be possible to
722 enable the sanitizer for all images (BL1 and BL2 are especially
723 likely to be memory constrained). We recommend that the
724 sanitizer is enabled only in debug builds.
726 - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
727 certificate generation tool to save the keys used to establish the Chain of
728 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
730 - ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
731 If a SCP_BL2 image is present then this option must be passed for the ``fip``
734 - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
735 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
736 this file name will be used to save the key.
738 - ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
739 optional. It is only needed if the platform makefile specifies that it
740 is required in order to build the ``fwu_fip`` target.
742 - ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
743 Delegated Exception Interface to BL31 image. This defaults to ``0``.
745 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
748 - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
749 isolated on separate memory pages. This is a trade-off between security and
750 memory usage. See "Isolating code and read-only data on separate memory
751 pages" section in `Firmware Design`_. This flag is disabled by default and
752 affects all BL images.
754 - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
755 This build option is only valid if ``ARCH=aarch64``. The value should be
756 the path to the directory containing the SPD source, relative to
757 ``services/spd/``; the directory is expected to contain a makefile called
760 - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
761 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
762 execution in BL1 just before handing over to BL31. At this point, all
763 firmware images have been loaded in memory, and the MMU and caches are
764 turned off. Refer to the "Debugging options" section for more details.
766 - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
767 secure interrupts (caught through the FIQ line). Platforms can enable
768 this directive if they need to handle such interruption. When enabled,
769 the FIQ are handled in monitor mode and non secure world is not allowed
770 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
771 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
773 - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
774 Boot feature. When set to '1', BL1 and BL2 images include support to load
775 and verify the certificates and images in a FIP, and BL1 includes support
776 for the Firmware Update. The default value is '0'. Generation and inclusion
777 of certificates in the FIP and FWU_FIP depends upon the value of the
778 ``GENERATE_COT`` option.
781 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
782 already exist in disk, they will be overwritten without further notice.
784 - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
785 specifies the file that contains the Trusted World private key in PEM
786 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
788 - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
789 synchronous, (see "Initializing a BL32 Image" section in
790 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
791 synchronous method) or 1 (BL32 is initialized using asynchronous method).
794 - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
795 routing model which routes non-secure interrupts asynchronously from TSP
796 to EL3 causing immediate preemption of TSP. The EL3 is responsible
797 for saving and restoring the TSP context in this routing model. The
798 default routing model (when the value is 0) is to route non-secure
799 interrupts to TSP allowing it to save its context and hand over
800 synchronously to EL3 via an SMC.
803 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
804 must also be set to ``1``.
806 - ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
807 linker. When the ``LINKER`` build variable points to the armlink linker,
808 this flag is enabled automatically. To enable support for armlink, platforms
809 will have to provide a scatter file for the BL image. Currently, Tegra
810 platforms use the armlink support to compile BL3-1 images.
812 - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
813 memory region in the BL memory map or not (see "Use of Coherent memory in
814 TF-A" section in `Firmware Design`_). It can take the value 1
815 (Coherent memory region is included) or 0 (Coherent memory region is
816 excluded). Default is 1.
818 - ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
819 This feature creates a library of functions to be placed in ROM and thus
820 reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default
823 - ``V``: Verbose build. If assigned anything other than 0, the build commands
824 are printed. Default is 0.
826 - ``VERSION_STRING``: String used in the log output for each TF-A image.
827 Defaults to a string formed by concatenating the version number, build type
830 - ``W``: Warning level. Some compiler warning options of interest have been
831 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
832 each level enabling more warning options. Default is 0.
834 - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
835 the CPU after warm boot. This is applicable for platforms which do not
836 require interconnect programming to enable cache coherency (eg: single
837 cluster platforms). If this option is enabled, then warm boot path
838 enables D-caches immediately after enabling MMU. This option defaults to 0.
840 Arm development platform specific build options
841 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
843 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
844 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
845 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
846 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
849 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
850 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
851 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
852 match the frame used by the Non-Secure image (normally the Linux kernel).
853 Default is true (access to the frame is allowed).
855 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
856 By default, Arm platforms use a watchdog to trigger a system reset in case
857 an error is encountered during the boot process (for example, when an image
858 could not be loaded or authenticated). The watchdog is enabled in the early
859 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
860 Trusted Watchdog may be disabled at build time for testing or development
863 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
864 have specific values at boot. This boolean option allows the Trusted Firmware
865 to have a Linux kernel image as BL33 by preparing the registers to these
866 values before jumping to BL33. This option defaults to 0 (disabled). For
867 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
868 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
869 to the location of a device tree blob (DTB) already loaded in memory. The
870 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
873 - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
874 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
875 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
876 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
877 this flag is 0. Note that this option is not used on FVP platforms.
879 - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
880 for the construction of composite state-ID in the power-state parameter.
881 The existing PSCI clients currently do not support this encoding of
882 State-ID yet. Hence this flag is used to configure whether to use the
883 recommended State-ID encoding or not. The default value of this flag is 0,
884 in which case the platform is configured to expect NULL in the State-ID
885 field of power-state parameter.
887 - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
888 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
889 for Arm platforms. Depending on the selected option, the proper private key
890 must be specified using the ``ROT_KEY`` option when building the Trusted
891 Firmware. This private key will be used by the certificate generation tool
892 to sign the BL2 and Trusted Key certificates. Available options for
893 ``ARM_ROTPK_LOCATION`` are:
895 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
896 registers. The private key corresponding to this ROTPK hash is not
898 - ``devel_rsa`` : return a development public key hash embedded in the BL1
899 and BL2 binaries. This hash has been obtained from the RSA public key
900 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
901 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
902 creating the certificates.
903 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
904 and BL2 binaries. This hash has been obtained from the ECDSA public key
905 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
906 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
907 when creating the certificates.
909 - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
911 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
912 - ``tdram`` : Trusted DRAM (if available)
913 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
914 configured by the TrustZone controller)
916 - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
917 of the translation tables library instead of version 2. It is set to 0 by
918 default, which selects version 2.
920 - ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
921 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
922 platforms. If this option is specified, then the path to the CryptoCell
923 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
925 For a better understanding of these options, the Arm development platform memory
926 map is explained in the `Firmware Design`_.
928 Arm CSS platform specific build options
929 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
931 - ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
932 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
933 compatible change to the MTL protocol, used for AP/SCP communication.
934 TF-A no longer supports earlier SCP versions. If this option is set to 1
935 then TF-A will detect if an earlier version is in use. Default is 1.
937 - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
938 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
939 during boot. Default is 1.
941 - ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
942 instead of SCPI/BOM driver for communicating with the SCP during power
943 management operations and for SCP RAM Firmware transfer. If this option
944 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
946 Arm FVP platform specific build options
947 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
949 - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
950 build the topology tree within TF-A. By default TF-A is configured for dual
951 cluster topology and this option can be used to override the default value.
953 - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
954 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
955 explained in the options below:
957 - ``FVP_CCI`` : The CCI driver is selected. This is the default
958 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
959 - ``FVP_CCN`` : The CCN driver is selected. This is the default
960 if ``FVP_CLUSTER_COUNT`` > 2.
962 - ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
963 a single cluster. This option defaults to 4.
965 - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
966 in the system. This option defaults to 1. Note that the build option
967 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
969 - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
971 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
972 - ``FVP_GICV2`` : The GICv2 only driver is selected
973 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
975 - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
976 for functions that wait for an arbitrary time length (udelay and mdelay).
977 The default value is 0.
979 - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
980 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
981 details on HW_CONFIG. By default, this is initialized to a sensible DTS
982 file in ``fdts/`` folder depending on other build options. But some cases,
983 like shifted affinity format for MPIDR, cannot be detected at build time
984 and this option is needed to specify the appropriate DTS file.
986 - ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
987 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
988 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
989 HW_CONFIG blob instead of the DTS file. This option is useful to override
990 the default HW_CONFIG selected by the build system.
992 ARM JUNO platform specific build options
993 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
995 - ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
996 Media Protection (TZ-MP1). Default value of this flag is 0.
1001 To compile a debug version and make the build more verbose use
1005 make PLAT=<platform> DEBUG=1 V=1 all
1007 AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
1008 example DS-5) might not support this and may need an older version of DWARF
1009 symbols to be emitted by GCC. This can be achieved by using the
1010 ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
1011 version to 2 is recommended for DS-5 versions older than 5.16.
1013 When debugging logic problems it might also be useful to disable all compiler
1014 optimizations by using ``-O0``.
1017 Using ``-O0`` could cause output images to be larger and base addresses
1018 might need to be recalculated (see the **Memory layout on Arm development
1019 platforms** section in the `Firmware Design`_).
1021 Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1026 CFLAGS='-O0 -gdwarf-2' \
1027 make PLAT=<platform> DEBUG=1 V=1 all
1029 Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1030 ignored as the linker is called directly.
1032 It is also possible to introduce an infinite loop to help in debugging the
1033 post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1034 ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
1035 section. In this case, the developer may take control of the target using a
1036 debugger when indicated by the console output. When using DS-5, the following
1037 commands can be used:
1041 # Stop target execution
1045 # Prepare your debugging environment, e.g. set breakpoints
1048 # Jump over the debug loop
1049 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1054 Building the Test Secure Payload
1055 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1057 The TSP is coupled with a companion runtime service in the BL31 firmware,
1058 called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
1059 must be recompiled as well. For more information on SPs and SPDs, see the
1060 `Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
1062 First clean the TF-A build directory to get rid of any previous BL31 binary.
1063 Then to build the TSP image use:
1067 make PLAT=<platform> SPD=tspd all
1069 An additional boot loader binary file is created in the ``build`` directory:
1073 build/<platform>/<build-type>/bl32.bin
1076 Building and using the FIP tool
1077 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1079 Firmware Image Package (FIP) is a packaging format used by TF-A to package
1080 firmware images in a single binary. The number and type of images that should
1081 be packed in a FIP is platform specific and may include TF-A images and other
1082 firmware images required by the platform. For example, most platforms require
1083 a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
1086 The TF-A build system provides the make target ``fip`` to create a FIP file
1087 for the specified platform using the FIP creation tool included in the TF-A
1088 project. Examples below show how to build a FIP file for FVP, packaging TF-A
1095 make PLAT=fvp BL33=<path-to>/bl33.bin fip
1101 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
1103 The resulting FIP may be found in:
1107 build/fvp/<build-type>/fip.bin
1109 For advanced operations on FIP files, it is also possible to independently build
1110 the tool and create or modify FIPs using this tool. To do this, follow these
1113 It is recommended to remove old artifacts before building the tool:
1117 make -C tools/fiptool clean
1123 make [DEBUG=1] [V=1] fiptool
1125 The tool binary can be located in:
1129 ./tools/fiptool/fiptool
1131 Invoking the tool with ``help`` will print a help message with all available
1134 Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1138 ./tools/fiptool/fiptool create \
1139 --tb-fw build/<platform>/<build-type>/bl2.bin \
1140 --soc-fw build/<platform>/<build-type>/bl31.bin \
1143 Example 2: view the contents of an existing Firmware package:
1147 ./tools/fiptool/fiptool info <path-to>/fip.bin
1149 Example 3: update the entries of an existing Firmware package:
1153 # Change the BL2 from Debug to Release version
1154 ./tools/fiptool/fiptool update \
1155 --tb-fw build/<platform>/release/bl2.bin \
1156 build/<platform>/debug/fip.bin
1158 Example 4: unpack all entries from an existing Firmware package:
1162 # Images will be unpacked to the working directory
1163 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1165 Example 5: remove an entry from an existing Firmware package:
1169 ./tools/fiptool/fiptool remove \
1170 --tb-fw build/<platform>/debug/fip.bin
1172 Note that if the destination FIP file exists, the create, update and
1173 remove operations will automatically overwrite it.
1175 The unpack operation will fail if the images already exist at the
1176 destination. In that case, use -f or --force to continue.
1178 More information about FIP can be found in the `Firmware Design`_ document.
1180 Building FIP images with support for Trusted Board Boot
1181 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1183 Trusted Board Boot primarily consists of the following two features:
1185 - Image Authentication, described in `Trusted Board Boot`_, and
1186 - Firmware Update, described in `Firmware Update`_
1188 The following steps should be followed to build FIP and (optionally) FWU_FIP
1189 images with support for these features:
1191 #. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1192 modules by checking out a recent version of the `mbed TLS Repository`_. It
1193 is important to use a version that is compatible with TF-A and fixes any
1194 known security vulnerabilities. See `mbed TLS Security Center`_ for more
1195 information. The latest version of TF-A is tested with tag
1198 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1199 source files the modules depend upon.
1200 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1201 options required to build the mbed TLS sources.
1203 Note that the mbed TLS library is licensed under the Apache version 2.0
1204 license. Using mbed TLS source code will affect the licensing of TF-A
1205 binaries that are built using this library.
1207 #. To build the FIP image, ensure the following command line variables are set
1208 while invoking ``make`` to build TF-A:
1210 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1211 - ``TRUSTED_BOARD_BOOT=1``
1212 - ``GENERATE_COT=1``
1214 In the case of Arm platforms, the location of the ROTPK hash must also be
1215 specified at build time. Two locations are currently supported (see
1216 ``ARM_ROTPK_LOCATION`` build option):
1218 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1219 root-key storage registers present in the platform. On Juno, this
1220 registers are read-only. On FVP Base and Cortex models, the registers
1221 are read-only, but the value can be specified using the command line
1222 option ``bp.trusted_key_storage.public_key`` when launching the model.
1223 On both Juno and FVP models, the default value corresponds to an
1224 ECDSA-SECP256R1 public key hash, whose private part is not currently
1227 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1228 in the Arm platform port. The private/public RSA key pair may be
1229 found in ``plat/arm/board/common/rotpk``.
1231 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1232 in the Arm platform port. The private/public ECDSA key pair may be
1233 found in ``plat/arm/board/common/rotpk``.
1235 Example of command line using RSA development keys:
1239 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1240 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1241 ARM_ROTPK_LOCATION=devel_rsa \
1242 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1243 BL33=<path-to>/<bl33_image> \
1246 The result of this build will be the bl1.bin and the fip.bin binaries. This
1247 FIP will include the certificates corresponding to the Chain of Trust
1248 described in the TBBR-client document. These certificates can also be found
1249 in the output build directory.
1251 #. The optional FWU_FIP contains any additional images to be loaded from
1252 Non-Volatile storage during the `Firmware Update`_ process. To build the
1253 FWU_FIP, any FWU images required by the platform must be specified on the
1254 command line. On Arm development platforms like Juno, these are:
1256 - NS_BL2U. The AP non-secure Firmware Updater image.
1257 - SCP_BL2U. The SCP Firmware Update Configuration image.
1259 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1260 targets using RSA development:
1264 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1265 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1266 ARM_ROTPK_LOCATION=devel_rsa \
1267 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1268 BL33=<path-to>/<bl33_image> \
1269 SCP_BL2=<path-to>/<scp_bl2_image> \
1270 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1271 NS_BL2U=<path-to>/<ns_bl2u_image> \
1275 The BL2U image will be built by default and added to the FWU_FIP.
1276 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1277 to the command line above.
1280 Building and installing the non-secure and SCP FWU images (NS_BL1U,
1281 NS_BL2U and SCP_BL2U) is outside the scope of this document.
1283 The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
1284 Both the FIP and FWU_FIP will include the certificates corresponding to the
1285 Chain of Trust described in the TBBR-client document. These certificates
1286 can also be found in the output build directory.
1288 Building the Certificate Generation Tool
1289 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1291 The ``cert_create`` tool is built as part of the TF-A build process when the
1292 ``fip`` make target is specified and TBB is enabled (as described in the
1293 previous section), but it can also be built separately with the following
1298 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1300 For platforms that require their own IDs in certificate files, the generic
1301 'cert_create' tool can be built with the following command. Note that the target
1302 platform must define its IDs within a ``platform_oid.h`` header file for the
1307 make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
1309 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1310 verbose. The following command should be used to obtain help about the tool:
1314 ./tools/cert_create/cert_create -h
1316 Building a FIP for Juno and FVP
1317 -------------------------------
1319 This section provides Juno and FVP specific instructions to build Trusted
1320 Firmware, obtain the additional required firmware, and pack it all together in
1321 a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
1324 Pre-built binaries for AArch32 are available from Linaro Release 16.12
1325 onwards. Before that release, pre-built binaries are only available for
1329 Follow the full instructions for one platform before switching to a
1330 different one. Mixing instructions for different platforms may result in
1334 The uboot image downloaded by the Linaro workspace script does not always
1335 match the uboot image packaged as BL33 in the corresponding fip file. It is
1336 recommended to use the version that is packaged in the fip file using the
1340 For the FVP, the kernel FDT is packaged in FIP during build and loaded
1341 by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1342 section for more info on selecting the right FDT to use.
1344 #. Clean the working directory
1350 #. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
1352 Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
1353 package included in the Linaro release:
1358 make [DEBUG=1] [V=1] fiptool
1360 # Unpack firmware images from Linaro FIP
1361 ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
1363 The unpack operation will result in a set of binary images extracted to the
1364 current working directory. The SCP_BL2 image corresponds to
1365 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
1368 The fiptool will complain if the images to be unpacked already
1369 exist in the current directory. If that is the case, either delete those
1370 files or use the ``--force`` option to overwrite.
1373 For AArch32, the instructions below assume that nt-fw.bin is a
1374 normal world boot loader that supports AArch32.
1376 #. Build TF-A images and create a new FIP for FVP
1381 make PLAT=fvp BL33=nt-fw.bin all fip
1384 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1386 #. Build TF-A images and create a new FIP for Juno
1390 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1391 as a build parameter.
1395 make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
1399 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1400 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1401 separately for AArch32.
1403 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1404 to the AArch32 Linaro cross compiler.
1408 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1410 - Build BL32 in AArch32.
1414 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1415 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1417 - Save ``bl32.bin`` to a temporary location and clean the build products.
1421 cp <path-to-build>/bl32.bin <path-to-temporary>
1424 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1425 must point to the AArch64 Linaro cross compiler.
1429 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1431 - The following parameters should be used to build BL1 and BL2 in AArch64
1432 and point to the BL32 file.
1436 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
1437 BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
1438 BL32=<path-to-temporary>/bl32.bin all fip
1440 The resulting BL1 and FIP images may be found in:
1445 ./build/juno/release/bl1.bin
1446 ./build/juno/release/fip.bin
1449 ./build/fvp/release/bl1.bin
1450 ./build/fvp/release/fip.bin
1453 Booting Firmware Update images
1454 -------------------------------------
1456 When Firmware Update (FWU) is enabled there are at least 2 new images
1457 that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1463 The new images must be programmed in flash memory by adding
1464 an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1465 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1466 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1467 programming" for more information. User should ensure these do not
1468 overlap with any other entries in the file.
1472 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1473 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1474 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1475 NOR10LOAD: 00000000 ;Image Load Address
1476 NOR10ENTRY: 00000000 ;Image Entry Point
1478 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1479 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1480 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1481 NOR11LOAD: 00000000 ;Image Load Address
1483 The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1484 In the same way, the address ns_bl2u_base_address is the value of
1485 NS_BL2U_BASE - 0x8000000.
1490 The additional fip images must be loaded with:
1494 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1495 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1497 The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1498 In the same way, the address ns_bl2u_base_address is the value of
1502 EL3 payloads alternative boot flow
1503 ----------------------------------
1505 On a pre-production system, the ability to execute arbitrary, bare-metal code at
1506 the highest exception level is required. It allows full, direct access to the
1507 hardware, for example to run silicon soak tests.
1509 Although it is possible to implement some baremetal secure firmware from
1510 scratch, this is a complex task on some platforms, depending on the level of
1511 configuration required to put the system in the expected state.
1513 Rather than booting a baremetal application, a possible compromise is to boot
1514 ``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1515 boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1516 other BL images and passing control to BL31. It reduces the complexity of
1517 developing EL3 baremetal code by:
1519 - putting the system into a known architectural state;
1520 - taking care of platform secure world initialization;
1521 - loading the SCP_BL2 image if required by the platform.
1523 When booting an EL3 payload on Arm standard platforms, the configuration of the
1524 TrustZone controller is simplified such that only region 0 is enabled and is
1525 configured to permit secure access only. This gives full access to the whole
1526 DRAM to the EL3 payload.
1528 The system is left in the same state as when entering BL31 in the default boot
1529 flow. In particular:
1532 - Current state is AArch64;
1533 - Little-endian data access;
1534 - All exceptions disabled;
1538 Booting an EL3 payload
1539 ~~~~~~~~~~~~~~~~~~~~~~
1541 The EL3 payload image is a standalone image and is not part of the FIP. It is
1542 not loaded by TF-A. Therefore, there are 2 possible scenarios:
1544 - The EL3 payload may reside in non-volatile memory (NVM) and execute in
1545 place. In this case, booting it is just a matter of specifying the right
1546 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
1548 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1551 To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1552 used. The infinite loop that it introduces in BL1 stops execution at the right
1553 moment for a debugger to take control of the target and load the payload (for
1554 example, over JTAG).
1556 It is expected that this loading method will work in most cases, as a debugger
1557 connection is usually available in a pre-production system. The user is free to
1558 use any other platform-specific mechanism to load the EL3 payload, though.
1560 Booting an EL3 payload on FVP
1561 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1563 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1564 the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1565 is undefined on the FVP platform and the FVP platform code doesn't clear it.
1566 Therefore, one must modify the way the model is normally invoked in order to
1567 clear the mailbox at start-up.
1569 One way to do that is to create an 8-byte file containing all zero bytes using
1570 the following command:
1574 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1576 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1577 using the following model parameters:
1581 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1582 --data=mailbox.dat@0x04000000 [Foundation FVP]
1584 To provide the model with the EL3 payload image, the following methods may be
1587 #. If the EL3 payload is able to execute in place, it may be programmed into
1588 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1589 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1594 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
1596 On Foundation FVP, there is no flash loader component and the EL3 payload
1597 may be programmed anywhere in flash using method 3 below.
1599 #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1600 command may be used to load the EL3 payload ELF image over JTAG:
1604 load <path-to>/el3-payload.elf
1606 #. The EL3 payload may be pre-loaded in volatile memory using the following
1611 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
1612 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
1614 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1615 used when building TF-A.
1617 Booting an EL3 payload on Juno
1618 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1620 If the EL3 payload is able to execute in place, it may be programmed in flash
1621 memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1622 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1623 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1624 programming" for more information.
1626 Alternatively, the same DS-5 command mentioned in the FVP section above can
1627 be used to load the EL3 payload's ELF file over JTAG on Juno.
1629 Preloaded BL33 alternative boot flow
1630 ------------------------------------
1632 Some platforms have the ability to preload BL33 into memory instead of relying
1633 on TF-A to load it. This may simplify packaging of the normal world code and
1634 improve performance in a development environment. When secure world cold boot
1635 is complete, TF-A simply jumps to a BL33 base address provided at build time.
1637 For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1638 used when compiling TF-A. For example, the following command will create a FIP
1639 without a BL33 and prepare to jump to a BL33 image loaded at address
1644 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1646 Boot of a preloaded kernel image on Base FVP
1647 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1649 The following example uses a simplified boot flow by directly jumping from the
1650 TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1651 useful if both the kernel and the device tree blob (DTB) are already present in
1652 memory (like in FVP).
1654 For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1655 address ``0x82000000``, the firmware can be built like this:
1659 CROSS_COMPILE=aarch64-linux-gnu- \
1660 make PLAT=fvp DEBUG=1 \
1662 ARM_LINUX_KERNEL_AS_BL33=1 \
1663 PRELOADED_BL33_BASE=0x80080000 \
1664 ARM_PRELOADED_DTB_BASE=0x82000000 \
1667 Now, it is needed to modify the DTB so that the kernel knows the address of the
1668 ramdisk. The following script generates a patched DTB from the provided one,
1669 assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1670 script assumes that the user is using a ramdisk image prepared for U-Boot, like
1671 the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1672 offset in ``INITRD_START`` has to be removed.
1678 # Path to the input DTB
1679 KERNEL_DTB=<path-to>/<fdt>
1680 # Path to the output DTB
1681 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1682 # Base address of the ramdisk
1683 INITRD_BASE=0x84000000
1684 # Path to the ramdisk
1685 INITRD=<path-to>/<ramdisk.img>
1687 # Skip uboot header (64 bytes)
1688 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1689 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1690 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1692 CHOSEN_NODE=$(echo \
1695 linux,initrd-start = <${INITRD_START}>; \
1696 linux,initrd-end = <${INITRD_END}>; \
1700 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1701 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
1703 And the FVP binary can be run with the following command:
1707 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1708 -C pctl.startup=0.0.0.0 \
1709 -C bp.secure_memory=1 \
1710 -C cluster0.NUM_CORES=4 \
1711 -C cluster1.NUM_CORES=4 \
1712 -C cache_state_modelled=1 \
1713 -C cluster0.cpu0.RVBAR=0x04020000 \
1714 -C cluster0.cpu1.RVBAR=0x04020000 \
1715 -C cluster0.cpu2.RVBAR=0x04020000 \
1716 -C cluster0.cpu3.RVBAR=0x04020000 \
1717 -C cluster1.cpu0.RVBAR=0x04020000 \
1718 -C cluster1.cpu1.RVBAR=0x04020000 \
1719 -C cluster1.cpu2.RVBAR=0x04020000 \
1720 -C cluster1.cpu3.RVBAR=0x04020000 \
1721 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1722 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1723 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1724 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1726 Boot of a preloaded kernel image on Juno
1727 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1729 The Trusted Firmware must be compiled in a similar way as for FVP explained
1730 above. The process to load binaries to memory is the one explained in
1731 `Booting an EL3 payload on Juno`_.
1733 Running the software on FVP
1734 ---------------------------
1736 The latest version of the AArch64 build of TF-A has been tested on the following
1737 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1738 (64-bit host machine only).
1741 The FVP models used are Version 11.6 Build 45, unless otherwise stated.
1743 - ``FVP_Base_AEMv8A-AEMv8A``
1744 - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
1745 - ``FVP_Base_RevC-2xAEMv8A``
1746 - ``FVP_Base_Cortex-A32x4``
1747 - ``FVP_Base_Cortex-A35x4``
1748 - ``FVP_Base_Cortex-A53x4``
1749 - ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1750 - ``FVP_Base_Cortex-A55x4``
1751 - ``FVP_Base_Cortex-A57x1-A53x1``
1752 - ``FVP_Base_Cortex-A57x2-A53x4``
1753 - ``FVP_Base_Cortex-A57x4-A53x4``
1754 - ``FVP_Base_Cortex-A57x4``
1755 - ``FVP_Base_Cortex-A72x4-A53x4``
1756 - ``FVP_Base_Cortex-A72x4``
1757 - ``FVP_Base_Cortex-A73x4-A53x4``
1758 - ``FVP_Base_Cortex-A73x4``
1759 - ``FVP_Base_Cortex-A75x4``
1760 - ``FVP_Base_Cortex-A76x4``
1761 - ``FVP_Base_Cortex-A76AEx4``
1762 - ``FVP_Base_Cortex-A76AEx8``
1763 - ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
1764 - ``FVP_Base_Neoverse-N1x4``
1765 - ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
1766 - ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
1767 - ``FVP_RD_E1Edge`` (Version 11.3 build 42)
1769 - ``Foundation_Platform``
1771 The latest version of the AArch32 build of TF-A has been tested on the following
1772 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1773 (64-bit host machine only).
1775 - ``FVP_Base_AEMv8A-AEMv8A``
1776 - ``FVP_Base_Cortex-A32x4``
1779 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1780 is not compatible with legacy GIC configurations. Therefore this FVP does not
1781 support these legacy GIC configurations.
1784 The build numbers quoted above are those reported by launching the FVP
1785 with the ``--version`` parameter.
1788 Linaro provides a ramdisk image in prebuilt FVP configurations and full
1789 file systems that can be downloaded separately. To run an FVP with a virtio
1790 file system image an additional FVP configuration option
1791 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1795 The software will not work on Version 1.0 of the Foundation FVP.
1796 The commands below would report an ``unhandled argument`` error in this case.
1799 FVPs can be launched with ``--cadi-server`` option such that a
1800 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
1804 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
1805 the internal synchronisation timings changed compared to older versions of
1806 the models. The models can be launched with ``-Q 100`` option if they are
1807 required to match the run time characteristics of the older versions.
1809 The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1810 downloaded for free from `Arm's website`_.
1812 The Cortex-A models listed above are also available to download from
1815 Please refer to the FVP documentation for a detailed description of the model
1816 parameter options. A brief description of the important ones that affect TF-A
1817 and normal world software behavior is provided below.
1819 Obtaining the Flattened Device Trees
1820 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1822 Depending on the FVP configuration and Linux configuration used, different
1823 FDT files are required. FDT source files for the Foundation and Base FVPs can
1824 be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1825 a subset of the Base FVP components. For example, the Foundation FVP lacks
1826 CLCD and MMC support, and has only one CPU cluster.
1829 It is not recommended to use the FDTs built along the kernel because not
1830 all FDTs are available from there.
1832 The dynamic configuration capability is enabled in the firmware for FVPs.
1833 This means that the firmware can authenticate and load the FDT if present in
1834 FIP. A default FDT is packaged into FIP during the build based on
1835 the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1836 or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1837 `Arm FVP platform specific build options`_ section for detail on the options).
1839 - ``fvp-base-gicv2-psci.dts``
1841 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1842 affinities and with Base memory map configuration.
1844 - ``fvp-base-gicv2-psci-aarch32.dts``
1846 For use with models such as the Cortex-A32 Base FVPs without shifted
1847 affinities and running Linux in AArch32 state with Base memory map
1850 - ``fvp-base-gicv3-psci.dts``
1852 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1853 affinities and with Base memory map configuration and Linux GICv3 support.
1855 - ``fvp-base-gicv3-psci-1t.dts``
1857 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1858 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1860 - ``fvp-base-gicv3-psci-dynamiq.dts``
1862 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1863 single cluster, single threaded CPUs, Base memory map configuration and Linux
1866 - ``fvp-base-gicv3-psci-aarch32.dts``
1868 For use with models such as the Cortex-A32 Base FVPs without shifted
1869 affinities and running Linux in AArch32 state with Base memory map
1870 configuration and Linux GICv3 support.
1872 - ``fvp-foundation-gicv2-psci.dts``
1874 For use with Foundation FVP with Base memory map configuration.
1876 - ``fvp-foundation-gicv3-psci.dts``
1878 (Default) For use with Foundation FVP with Base memory map configuration
1879 and Linux GICv3 support.
1881 Running on the Foundation FVP with reset to BL1 entrypoint
1882 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1884 The following ``Foundation_Platform`` parameters should be used to boot Linux with
1885 4 CPUs using the AArch64 build of TF-A.
1889 <path-to>/Foundation_Platform \
1895 --data="<path-to>/<bl1-binary>"@0x0 \
1896 --data="<path-to>/<FIP-binary>"@0x08000000 \
1897 --data="<path-to>/<kernel-binary>"@0x80080000 \
1898 --data="<path-to>/<ramdisk-binary>"@0x84000000
1902 - BL1 is loaded at the start of the Trusted ROM.
1903 - The Firmware Image Package is loaded at the start of NOR FLASH0.
1904 - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1905 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
1906 - The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1907 and enable the GICv3 device in the model. Note that without this option,
1908 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1909 is not supported by TF-A.
1910 - In order for TF-A to run correctly on the Foundation FVP, the architecture
1911 versions must match. The Foundation FVP defaults to the highest v8.x
1912 version it supports but the default build for TF-A is for v8.0. To avoid
1913 issues either start the Foundation FVP to use v8.0 architecture using the
1914 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1917 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1918 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1920 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
1921 with 8 CPUs using the AArch64 build of TF-A.
1925 <path-to>/FVP_Base_RevC-2xAEMv8A \
1926 -C pctl.startup=0.0.0.0 \
1927 -C bp.secure_memory=1 \
1928 -C bp.tzc_400.diagnostics=1 \
1929 -C cluster0.NUM_CORES=4 \
1930 -C cluster1.NUM_CORES=4 \
1931 -C cache_state_modelled=1 \
1932 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1933 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1934 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1935 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1938 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
1939 a specific DTS for all the CPUs to be loaded.
1941 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1942 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1944 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1945 with 8 CPUs using the AArch32 build of TF-A.
1949 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1950 -C pctl.startup=0.0.0.0 \
1951 -C bp.secure_memory=1 \
1952 -C bp.tzc_400.diagnostics=1 \
1953 -C cluster0.NUM_CORES=4 \
1954 -C cluster1.NUM_CORES=4 \
1955 -C cache_state_modelled=1 \
1956 -C cluster0.cpu0.CONFIG64=0 \
1957 -C cluster0.cpu1.CONFIG64=0 \
1958 -C cluster0.cpu2.CONFIG64=0 \
1959 -C cluster0.cpu3.CONFIG64=0 \
1960 -C cluster1.cpu0.CONFIG64=0 \
1961 -C cluster1.cpu1.CONFIG64=0 \
1962 -C cluster1.cpu2.CONFIG64=0 \
1963 -C cluster1.cpu3.CONFIG64=0 \
1964 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1965 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1966 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1967 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1969 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1970 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1972 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1973 boot Linux with 8 CPUs using the AArch64 build of TF-A.
1977 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1978 -C pctl.startup=0.0.0.0 \
1979 -C bp.secure_memory=1 \
1980 -C bp.tzc_400.diagnostics=1 \
1981 -C cache_state_modelled=1 \
1982 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1983 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1984 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1985 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1987 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1988 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1990 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1991 boot Linux with 4 CPUs using the AArch32 build of TF-A.
1995 <path-to>/FVP_Base_Cortex-A32x4 \
1996 -C pctl.startup=0.0.0.0 \
1997 -C bp.secure_memory=1 \
1998 -C bp.tzc_400.diagnostics=1 \
1999 -C cache_state_modelled=1 \
2000 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
2001 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
2002 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2003 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2005 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
2006 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2008 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
2009 with 8 CPUs using the AArch64 build of TF-A.
2013 <path-to>/FVP_Base_RevC-2xAEMv8A \
2014 -C pctl.startup=0.0.0.0 \
2015 -C bp.secure_memory=1 \
2016 -C bp.tzc_400.diagnostics=1 \
2017 -C cluster0.NUM_CORES=4 \
2018 -C cluster1.NUM_CORES=4 \
2019 -C cache_state_modelled=1 \
2020 -C cluster0.cpu0.RVBAR=0x04010000 \
2021 -C cluster0.cpu1.RVBAR=0x04010000 \
2022 -C cluster0.cpu2.RVBAR=0x04010000 \
2023 -C cluster0.cpu3.RVBAR=0x04010000 \
2024 -C cluster1.cpu0.RVBAR=0x04010000 \
2025 -C cluster1.cpu1.RVBAR=0x04010000 \
2026 -C cluster1.cpu2.RVBAR=0x04010000 \
2027 -C cluster1.cpu3.RVBAR=0x04010000 \
2028 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2029 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
2030 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2031 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2032 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2033 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2037 - If Position Independent Executable (PIE) support is enabled for BL31
2038 in this config, it can be loaded at any valid address for execution.
2040 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
2041 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
2042 parameter is needed to load the individual bootloader images in memory.
2043 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
2044 Payload. For the same reason, the FDT needs to be compiled from the DT source
2045 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
2048 - The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
2049 specific DTS for all the CPUs to be loaded.
2051 - The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
2052 X and Y are the cluster and CPU numbers respectively, is used to set the
2053 reset vector for each core.
2055 - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
2056 changing the value of
2057 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
2060 Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
2061 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2063 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
2064 with 8 CPUs using the AArch32 build of TF-A.
2068 <path-to>/FVP_Base_AEMv8A-AEMv8A \
2069 -C pctl.startup=0.0.0.0 \
2070 -C bp.secure_memory=1 \
2071 -C bp.tzc_400.diagnostics=1 \
2072 -C cluster0.NUM_CORES=4 \
2073 -C cluster1.NUM_CORES=4 \
2074 -C cache_state_modelled=1 \
2075 -C cluster0.cpu0.CONFIG64=0 \
2076 -C cluster0.cpu1.CONFIG64=0 \
2077 -C cluster0.cpu2.CONFIG64=0 \
2078 -C cluster0.cpu3.CONFIG64=0 \
2079 -C cluster1.cpu0.CONFIG64=0 \
2080 -C cluster1.cpu1.CONFIG64=0 \
2081 -C cluster1.cpu2.CONFIG64=0 \
2082 -C cluster1.cpu3.CONFIG64=0 \
2083 -C cluster0.cpu0.RVBAR=0x04002000 \
2084 -C cluster0.cpu1.RVBAR=0x04002000 \
2085 -C cluster0.cpu2.RVBAR=0x04002000 \
2086 -C cluster0.cpu3.RVBAR=0x04002000 \
2087 -C cluster1.cpu0.RVBAR=0x04002000 \
2088 -C cluster1.cpu1.RVBAR=0x04002000 \
2089 -C cluster1.cpu2.RVBAR=0x04002000 \
2090 -C cluster1.cpu3.RVBAR=0x04002000 \
2091 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2092 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2093 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2094 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2095 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2098 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
2099 It should match the address programmed into the RVBAR register as well.
2101 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
2102 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2104 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
2105 boot Linux with 8 CPUs using the AArch64 build of TF-A.
2109 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
2110 -C pctl.startup=0.0.0.0 \
2111 -C bp.secure_memory=1 \
2112 -C bp.tzc_400.diagnostics=1 \
2113 -C cache_state_modelled=1 \
2114 -C cluster0.cpu0.RVBARADDR=0x04010000 \
2115 -C cluster0.cpu1.RVBARADDR=0x04010000 \
2116 -C cluster0.cpu2.RVBARADDR=0x04010000 \
2117 -C cluster0.cpu3.RVBARADDR=0x04010000 \
2118 -C cluster1.cpu0.RVBARADDR=0x04010000 \
2119 -C cluster1.cpu1.RVBARADDR=0x04010000 \
2120 -C cluster1.cpu2.RVBARADDR=0x04010000 \
2121 -C cluster1.cpu3.RVBARADDR=0x04010000 \
2122 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2123 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
2124 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2125 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2126 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2127 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2129 Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
2130 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2132 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
2133 boot Linux with 4 CPUs using the AArch32 build of TF-A.
2137 <path-to>/FVP_Base_Cortex-A32x4 \
2138 -C pctl.startup=0.0.0.0 \
2139 -C bp.secure_memory=1 \
2140 -C bp.tzc_400.diagnostics=1 \
2141 -C cache_state_modelled=1 \
2142 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2143 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2144 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2145 -C cluster0.cpu3.RVBARADDR=0x04002000 \
2146 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2147 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2148 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2149 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2150 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2152 Running the software on Juno
2153 ----------------------------
2155 This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
2157 To execute the software stack on Juno, the version of the Juno board recovery
2158 image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2159 earlier version installed or are unsure which version is installed, please
2160 re-install the recovery image by following the
2161 `Instructions for using Linaro's deliverables on Juno`_.
2163 Preparing TF-A images
2164 ~~~~~~~~~~~~~~~~~~~~~
2166 After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2167 ``SOFTWARE/`` directory of the Juno SD card.
2169 Other Juno software information
2170 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2172 Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
2173 software information. Please also refer to the `Juno Getting Started Guide`_ to
2174 get more detailed information about the Juno Arm development platform and how to
2177 Testing SYSTEM SUSPEND on Juno
2178 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2180 The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2181 to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2182 on Juno, at the linux shell prompt, issue the following command:
2186 echo +10 > /sys/class/rtc/rtc0/wakealarm
2187 echo -n mem > /sys/power/state
2189 The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2190 wakeup interrupt from RTC.
2194 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
2196 .. _arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
2197 .. _Linaro: `Linaro Release Notes`_
2198 .. _Linaro Release: `Linaro Release Notes`_
2199 .. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
2200 .. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
2201 .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
2202 .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
2203 .. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
2204 .. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
2205 .. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
2206 .. _Linux master tree: https://github.com/torvalds/linux/tree/master/
2207 .. _Dia: https://wiki.gnome.org/Apps/Dia/Download
2208 .. _here: psci-lib-integration-guide.rst
2209 .. _Trusted Board Boot: ../design/trusted-board-boot.rst
2210 .. _TB_FW_CONFIG for FVP: ../../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
2211 .. _Secure-EL1 Payloads and Dispatchers: ../design/firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
2212 .. _Firmware Update: ../components/firmware-update.rst
2213 .. _Firmware Design: ../design/firmware-design.rst
2214 .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2215 .. _mbed TLS Security Center: https://tls.mbed.org/security
2216 .. _Arm's website: `FVP models`_
2217 .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
2218 .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
2219 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2220 .. _Secure Partition Manager Design guide: ../components/secure-partition-manager-design.rst
2221 .. _`Trusted Firmware-A Coding Guidelines`: ../process/coding-guidelines.rst
2222 .. _Library at ROM: ../components/romlib-design.rst