4 This document describes how to build Trusted Firmware-A (TF-A) and run it with a
5 tested set of other software components using defined configurations on the Juno
6 Arm development platform and Arm Fixed Virtual Platform (FVP) models. It is
7 possible to use other software components, configurations and platforms but that
8 is outside the scope of this document.
10 This document assumes that the reader has previous experience running a fully
11 bootable Linux software stack on Juno or FVP using the prebuilt binaries and
12 filesystems provided by `Linaro`_. Further information may be found in the
13 `Linaro instructions`_. It also assumes that the user understands the role of
14 the different software components required to boot a Linux system:
16 - Specific firmware images required by the platform (e.g. SCP firmware on Juno)
17 - Normal world bootloader (e.g. UEFI or U-Boot)
22 This document also assumes that the user is familiar with the `FVP models`_ and
23 the different command line options available to launch the model.
25 This document should be used in conjunction with the `Firmware Design`_.
27 Host machine requirements
28 -------------------------
30 The minimum recommended machine specification for building the software and
31 running the FVP models is a dual-core processor running at 2GHz with 12GB of
32 RAM. For best performance, use a machine with a quad-core processor running at
33 2.6GHz with 16GB of RAM.
35 The software has been tested on Ubuntu 16.04 LTS (64-bit). Packages used for
36 building the software were installed from that distribution unless otherwise
39 The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE,
40 Cygwin, and Msys (MinGW) shells, using version 5.3.1 of the GNU toolchain.
45 Install the required packages to build TF-A with the following command:
49 sudo apt-get install device-tree-compiler build-essential gcc make git libssl-dev
51 TF-A has been tested with Linaro Release 18.04.
53 Download and install the AArch32 (arm-eabi) or AArch64 little-endian
54 (aarch64-linux-gnu) GCC cross compiler. If you would like to use the latest
55 features available, download GCC 8.3-2019.03 compiler from
56 `arm Developer page`_. Otherwise, the `Linaro Release Notes`_ documents which
57 version of the compiler to use for a given Linaro Release. Also, these
58 `Linaro instructions`_ provide further guidance and a script, which can be used
59 to download Linaro deliverables automatically.
61 Optionally, TF-A can be built using clang version 4.0 or newer or Arm
62 Compiler 6. See instructions below on how to switch the default compiler.
64 In addition, the following optional packages and tools may be needed:
66 - ``device-tree-compiler`` (dtc) package if you need to rebuild the Flattened Device
67 Tree (FDT) source files (``.dts`` files) provided with this software. The
68 version of dtc must be 1.4.6 or above.
70 - For debugging, Arm `Development Studio 5 (DS-5)`_.
72 - To create and modify the diagram files included in the documentation, `Dia`_.
73 This tool can be found in most Linux distributions. Inkscape is needed to
74 generate the actual \*.png files.
76 Getting the TF-A source code
77 ----------------------------
79 Clone the repository from the Gerrit server. The project details may be found
80 on the `arm-trusted-firmware-a project page`_. We recommend the "`Clone with
81 commit-msg hook`" clone method, which will setup the git commit hook that
82 automatically generates and inserts appropriate `Change-Id:` lines in your
85 Checking source code style
86 ~~~~~~~~~~~~~~~~~~~~~~~~~~
88 Trusted Firmware follows the `Linux Coding Style`_ . When making changes to the
89 source, for submission to the project, the source must be in compliance with
92 Additional, project-specific guidelines are defined in the `Trusted Firmware-A
93 Coding Guidelines`_ document.
95 To assist with coding style compliance, the project Makefile contains two
96 targets which both utilise the `checkpatch.pl` script that ships with the Linux
97 source tree. The project also defines certain *checkpatch* options in the
98 ``.checkpatch.conf`` file in the top-level directory.
101 Checkpatch errors will gate upstream merging of pull requests.
102 Checkpatch warnings will not gate merging but should be reviewed and fixed if
105 To check the entire source tree, you must first download copies of
106 ``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
107 in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
108 environment variable to point to ``checkpatch.pl`` (with the other 2 files in
109 the same directory) and build the `checkcodebase` target:
113 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
115 To just check the style on the files that differ between your local branch and
116 the remote master, use:
120 make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
122 If you wish to check your patch against something other than the remote master,
123 set the ``BASE_COMMIT`` variable to your desired branch. By default, ``BASE_COMMIT``
124 is set to ``origin/master``.
129 - Before building TF-A, the environment variable ``CROSS_COMPILE`` must point
130 to the Linaro cross compiler.
136 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
142 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-eabi-
144 It is possible to build TF-A using Clang or Arm Compiler 6. To do so
145 ``CC`` needs to point to the clang or armclang binary, which will
146 also select the clang or armclang assembler. Be aware that the
147 GNU linker is used by default. In case of being needed the linker
148 can be overridden using the ``LD`` variable. Clang linker version 6 is
149 known to work with TF-A.
151 In both cases ``CROSS_COMPILE`` should be set as described above.
153 Arm Compiler 6 will be selected when the base name of the path assigned
154 to ``CC`` matches the string 'armclang'.
156 For AArch64 using Arm Compiler 6:
160 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
161 make CC=<path-to-armclang>/bin/armclang PLAT=<platform> all
163 Clang will be selected when the base name of the path assigned to ``CC``
164 contains the string 'clang'. This is to allow both clang and clang-X.Y
167 For AArch64 using clang:
171 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
172 make CC=<path-to-clang>/bin/clang PLAT=<platform> all
174 - Change to the root directory of the TF-A source tree and build.
180 make PLAT=<platform> all
186 make PLAT=<platform> ARCH=aarch32 AARCH32_SP=sp_min all
190 - If ``PLAT`` is not specified, ``fvp`` is assumed by default. See the
191 `Summary of build options`_ for more information on available build
194 - (AArch32 only) Currently only ``PLAT=fvp`` is supported.
196 - (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
197 corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
198 provided by TF-A to demonstrate how PSCI Library can be integrated with
199 an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
200 include other runtime services, for example Trusted OS services. A guide
201 to integrate PSCI library with AArch32 EL3 Runtime Software can be found
204 - (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32
205 image, is not compiled in by default. Refer to the
206 `Building the Test Secure Payload`_ section below.
208 - By default this produces a release version of the build. To produce a
209 debug version instead, refer to the "Debugging options" section below.
211 - The build process creates products in a ``build`` directory tree, building
212 the objects and binaries for each boot loader stage in separate
213 sub-directories. The following boot loader binary files are created
214 from the corresponding ELF files:
216 - ``build/<platform>/<build-type>/bl1.bin``
217 - ``build/<platform>/<build-type>/bl2.bin``
218 - ``build/<platform>/<build-type>/bl31.bin`` (AArch64 only)
219 - ``build/<platform>/<build-type>/bl32.bin`` (mandatory for AArch32)
221 where ``<platform>`` is the name of the chosen platform and ``<build-type>``
222 is either ``debug`` or ``release``. The actual number of images might differ
223 depending on the platform.
225 - Build products for a specific build variant can be removed using:
229 make DEBUG=<D> PLAT=<platform> clean
231 ... where ``<D>`` is ``0`` or ``1``, as specified when building.
233 The build tree can be removed completely using:
239 Summary of build options
240 ~~~~~~~~~~~~~~~~~~~~~~~~
242 The TF-A build system supports the following build options. Unless mentioned
243 otherwise, these options are expected to be specified at the build command
244 line and are not to be modified in any component makefiles. Note that the
245 build system doesn't track dependency for build options. Therefore, if any of
246 the build options are changed from a previous build, a clean build must be
252 - ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the
253 compiler should use. Valid values are T32 and A32. It defaults to T32 due to
254 code having a smaller resulting size.
256 - ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as
257 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the
258 directory containing the SP source, relative to the ``bl32/``; the directory
259 is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
261 - ``ARCH`` : Choose the target build architecture for TF-A. It can take either
262 ``aarch64`` or ``aarch32`` as values. By default, it is defined to
265 - ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when
266 compiling TF-A. Its value must be numeric, and defaults to 8 . See also,
267 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in
270 - ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when
271 compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
272 *Armv8 Architecture Extensions* in `Firmware Design`_.
274 - ``BL2``: This is an optional build option which specifies the path to BL2
275 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be
278 - ``BL2U``: This is an optional build option which specifies the path to
279 BL2U image. In this case, the BL2U in TF-A will not be built.
281 - ``BL2_AT_EL3``: This is an optional build option that enables the use of
282 BL2 at EL3 execution level.
284 - ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place
285 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize
286 the RW sections in RAM, while leaving the RO sections in place. This option
287 enable this use-case. For now, this option is only supported when BL2_AT_EL3
290 - ``BL2_INV_DCACHE``: This is an optional build option which control dcache
291 invalidation upon BL2 entry. Some platform cannot handle cache operations
292 during entry as the coherency unit is not yet initialized. This may cause
293 crashing. Leaving this option to '1' (default) will allow the operation.
294 This option is only relevant when BL2_AT_EL3 is set to '1'.
296 - ``BL31``: This is an optional build option which specifies the path to
297 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not
300 - ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
301 file that contains the BL31 private key in PEM format. If ``SAVE_KEYS=1``,
302 this file name will be used to save the key.
304 - ``BL32``: This is an optional build option which specifies the path to
305 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not
308 - ``BL32_EXTRA1``: This is an optional build option which specifies the path to
309 Trusted OS Extra1 image for the ``fip`` target.
311 - ``BL32_EXTRA2``: This is an optional build option which specifies the path to
312 Trusted OS Extra2 image for the ``fip`` target.
314 - ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
315 file that contains the BL32 private key in PEM format. If ``SAVE_KEYS=1``,
316 this file name will be used to save the key.
318 - ``BL33``: Path to BL33 image in the host file system. This is mandatory for
319 ``fip`` target in case TF-A BL2 is used.
321 - ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
322 file that contains the BL33 private key in PEM format. If ``SAVE_KEYS=1``,
323 this file name will be used to save the key.
325 - ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication
326 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves.
327 If enabled, it is needed to use a compiler that supports the option
328 ``-mbranch-protection``. Selects the branch protection features to use:
329 - 0: Default value turns off all types of branch protection
330 - 1: Enables all types of branch protection features
331 - 2: Return address signing to its standard level
332 - 3: Extend the signing to include leaf functions
334 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options
335 and resulting PAuth/BTI features.
337 +-------+--------------+-------+-----+
338 | Value | GCC option | PAuth | BTI |
339 +=======+==============+=======+=====+
341 +-------+--------------+-------+-----+
342 | 1 | standard | Y | Y |
343 +-------+--------------+-------+-----+
344 | 2 | pac-ret | Y | N |
345 +-------+--------------+-------+-----+
346 | 3 | pac-ret+leaf | Y | N |
347 +-------+--------------+-------+-----+
349 This option defaults to 0 and this is an experimental feature.
350 Note that Pointer Authentication is enabled for Non-secure world
351 irrespective of the value of this option if the CPU supports it.
353 - ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the
354 compilation of each build. It must be set to a C string (including quotes
355 where applicable). Defaults to a string that contains the time and date of
358 - ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
359 build to be uniquely identified. Defaults to the current git commit id.
361 - ``CFLAGS``: Extra user options appended on the compiler's command line in
362 addition to the options set by the build system.
364 - ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may
365 release several CPUs out of reset. It can take either 0 (several CPUs may be
366 brought up) or 1 (only one CPU will ever be brought up during cold reset).
367 Default is 0. If the platform always brings up a single CPU, there is no
368 need to distinguish between primary and secondary CPUs and the boot path can
369 be optimised. The ``plat_is_my_cpu_primary()`` and
370 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
371 to be implemented in this case.
373 - ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
374 register state when an unexpected exception occurs during execution of
375 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
376 this is only enabled for a debug build of the firmware.
378 - ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
379 certificate generation tool to create new keys in case no valid keys are
380 present or specified. Allowed options are '0' or '1'. Default is '1'.
382 - ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause
383 the AArch32 system registers to be included when saving and restoring the
384 CPU context. The option must be set to 0 for AArch64-only platforms (that
385 is on hardware that does not implement AArch32, or at least not at EL1 and
386 higher ELs). Default value is 1.
388 - ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
389 registers to be included when saving and restoring the CPU context. Default
392 - ``CTX_INCLUDE_MTE_REGS``: Enables register saving/reloading support for
393 ARMv8.5 Memory Tagging Extension. A value of 0 will disable
394 saving/reloading and restrict the use of MTE to the normal world if the
395 CPU has support, while a value of 1 enables the saving/reloading, allowing
396 the use of MTE in both the secure and non-secure worlds. Default is 0
397 (disabled) and this feature is experimental.
399 - ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables
400 Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth
401 registers to be included when saving and restoring the CPU context as
402 part of world switch. Default value is 0 and this is an experimental feature.
403 Note that Pointer Authentication is enabled for Non-secure world irrespective
404 of the value of this flag if the CPU supports it.
406 - ``DEBUG``: Chooses between a debug and release build. It can take either 0
407 (release) or 1 (debug) as values. 0 is the default.
409 - ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation
410 of the binary image. If set to 1, then only the ELF image is built.
413 - ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
414 Board Boot authentication at runtime. This option is meant to be enabled only
415 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
416 flag has to be enabled. 0 is the default.
418 - ``E``: Boolean option to make warnings into errors. Default is 1.
420 - ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
421 the normal boot flow. It must specify the entry point address of the EL3
422 payload. Please refer to the "Booting an EL3 payload" section for more
425 - ``ENABLE_AMU``: Boolean option to enable Activity Monitor Unit extensions.
426 This is an optional architectural feature available on v8.4 onwards. Some
427 v8.2 implementations also implement an AMU and this option can be used to
428 enable this feature on those systems as well. Default is 0.
430 - ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()``
431 are compiled out. For debug builds, this option defaults to 1, and calls to
432 ``assert()`` are left in place. For release builds, this option defaults to 0
433 and calls to ``assert()`` function are compiled out. This option can be set
434 independently of ``DEBUG``. It can also be used to hide any auxiliary code
435 that is only required for the assertion and does not fit in the assertion
438 - ``ENABLE_BACKTRACE``: This option controls whether to enables backtrace
439 dumps or not. It is supported in both AArch64 and AArch32. However, in
440 AArch32 the format of the frame records are not defined in the AAPCS and they
441 are defined by the implementation. This implementation of backtrace only
442 supports the format used by GCC when T32 interworking is disabled. For this
443 reason enabling this option in AArch32 will force the compiler to only
444 generate A32 code. This option is enabled by default only in AArch64 debug
445 builds, but this behaviour can be overridden in each platform's Makefile or
446 in the build command line.
448 - ``ENABLE_MPAM_FOR_LOWER_ELS``: Boolean option to enable lower ELs to use MPAM
449 feature. MPAM is an optional Armv8.4 extension that enables various memory
450 system components and resources to define partitions; software running at
451 various ELs can assign themselves to desired partition to control their
454 When this option is set to ``1``, EL3 allows lower ELs to access their own
455 MPAM registers without trapping into EL3. This option doesn't make use of
456 partitioning in EL3, however. Platform initialisation code should configure
457 and use partitions in EL3 as required. This option defaults to ``0``.
459 - ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
460 support within generic code in TF-A. This option is currently only supported
461 in BL31. Default is 0.
463 - ``ENABLE_PMF``: Boolean option to enable support for optional Performance
464 Measurement Framework(PMF). Default is 0.
466 - ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI
467 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0.
468 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must
469 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in
472 - ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime
473 instrumentation which injects timestamp collection points into TF-A to
474 allow runtime performance to be measured. Currently, only PSCI is
475 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option
476 as well. Default is 0.
478 - ``ENABLE_SPE_FOR_LOWER_ELS`` : Boolean option to enable Statistical Profiling
479 extensions. This is an optional architectural feature for AArch64.
480 The default is 1 but is automatically disabled when the target architecture
483 - ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
484 Refer to the `Secure Partition Manager Design guide`_ for more details about
485 this feature. Default is 0.
487 - ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
488 (SVE) for the Non-secure world only. SVE is an optional architectural feature
489 for AArch64. Note that when SVE is enabled for the Non-secure world, access
490 to SIMD and floating-point functionality from the Secure world is disabled.
491 This is to avoid corruption of the Non-secure world data in the Z-registers
492 which are aliased by the SIMD and FP registers. The build option is not
493 compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
494 assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` set to
495 1. The default is 1 but is automatically disabled when the target
496 architecture is AArch32.
498 - ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
499 checks in GCC. Allowed values are "all", "strong", "default" and "none". The
500 default value is set to "none". "strong" is the recommended stack protection
501 level if this feature is desired. "none" disables the stack protection. For
502 all values other than "none", the ``plat_get_stack_protector_canary()``
503 platform hook needs to be implemented. The value is passed as the last
504 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``.
506 - ``ERROR_DEPRECATED``: This option decides whether to treat the usage of
507 deprecated platform APIs, helper functions or drivers within Trusted
508 Firmware as error. It can take the value 1 (flag the use of deprecated
509 APIs as error) or 0. The default is 0.
511 - ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions
512 targeted at EL3. When set ``0`` (default), no exceptions are expected or
513 handled at EL3, and a panic will result. This is supported only for AArch64
516 - ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault
517 injection from lower ELs, and this build option enables lower ELs to use
518 Error Records accessed via System Registers to inject faults. This is
519 applicable only to AArch64 builds.
521 This feature is intended for testing purposes only, and is advisable to keep
522 disabled for production images.
524 - ``FIP_NAME``: This is an optional build option which specifies the FIP
525 filename for the ``fip`` target. Default is ``fip.bin``.
527 - ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU
528 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``.
530 - ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
531 tool to create certificates as per the Chain of Trust described in
532 `Trusted Board Boot`_. The build system then calls ``fiptool`` to
533 include the certificates in the FIP and FWU_FIP. Default value is '0'.
535 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
536 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
537 the corresponding certificates, and to include those certificates in the
540 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
541 images will not include support for Trusted Board Boot. The FIP will still
542 include the corresponding certificates. This FIP can be used to verify the
543 Chain of Trust on the host machine through other mechanisms.
545 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
546 images will include support for Trusted Board Boot, but the FIP and FWU_FIP
547 will not include the corresponding certificates, causing a boot failure.
549 - ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
550 inherent support for specific EL3 type interrupts. Setting this build option
551 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both
552 by `platform abstraction layer`__ and `Interrupt Management Framework`__.
553 This allows GICv2 platforms to enable features requiring EL3 interrupt type.
554 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and
555 the Secure Payload interrupts needs to be synchronously handed over to Secure
556 EL1 for handling. The default value of this option is ``0``, which means the
557 Group 0 interrupts are assumed to be handled by Secure EL1.
559 .. __: `platform-interrupt-controller-API.rst`
560 .. __: `interrupt-framework-design.rst`
562 - ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
563 Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
564 ``0`` (default), these exceptions will be trapped in the current exception
565 level (or in EL1 if the current exception level is EL0).
567 - ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
568 software operations are required for CPUs to enter and exit coherency.
569 However, newer systems exist where CPUs' entry to and exit from coherency
570 is managed in hardware. Such systems require software to only initiate these
571 operations, and the rest is managed in hardware, minimizing active software
572 management. In such systems, this boolean option enables TF-A to carry out
573 build and run-time optimizations during boot and power management operations.
574 This option defaults to 0 and if it is enabled, then it implies
575 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
577 If this flag is disabled while the platform which TF-A is compiled for
578 includes cores that manage coherency in hardware, then a compilation error is
579 generated. This is based on the fact that a system cannot have, at the same
580 time, cores that manage coherency in hardware and cores that don't. In other
581 words, a platform cannot have, at the same time, cores that require
582 ``HW_ASSISTED_COHERENCY=1`` and cores that require
583 ``HW_ASSISTED_COHERENCY=0``.
585 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
586 translation library (xlat tables v2) must be used; version 1 of translation
587 library is not supported.
589 - ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3
590 runtime software in AArch32 mode, which is required to run AArch32 on Juno.
591 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in
592 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
595 - ``KEY_ALG``: This build flag enables the user to select the algorithm to be
596 used for generating the PKCS keys and subsequent signing of the certificate.
597 It accepts 3 values: ``rsa``, ``rsa_1_5`` and ``ecdsa``. The option
598 ``rsa_1_5`` is the legacy PKCS#1 RSA 1.5 algorithm which is not TBBR
599 compliant and is retained only for compatibility. The default value of this
600 flag is ``rsa`` which is the TBBR compliant PKCS#1 RSA 2.1 scheme.
602 - ``HASH_ALG``: This build flag enables the user to select the secure hash
603 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``.
604 The default value of this flag is ``sha256``.
606 - ``LDFLAGS``: Extra user options appended to the linkers' command line in
607 addition to the one set by the build system.
609 - ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
610 output compiled into the build. This should be one of the following:
616 20 (LOG_LEVEL_NOTICE)
617 30 (LOG_LEVEL_WARNING)
619 50 (LOG_LEVEL_VERBOSE)
621 All log output up to and including the selected log level is compiled into
622 the build. The default value is 40 in debug builds and 20 in release builds.
624 - ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
625 specifies the file that contains the Non-Trusted World private key in PEM
626 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
628 - ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
629 optional. It is only needed if the platform makefile specifies that it
630 is required in order to build the ``fwu_fip`` target.
632 - ``NS_TIMER_SWITCH``: Enable save and restore for non-secure timer register
633 contents upon world switch. It can take either 0 (don't save and restore) or
634 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
635 wants the timer registers to be saved and restored.
637 - ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
638 for the BL image. It can be either 0 (include) or 1 (remove). The default
641 - ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
642 the underlying hardware is not a full PL011 UART but a minimally compliant
643 generic UART, which is a subset of the PL011. The driver will not access
644 any register that is not part of the SBSA generic UART specification.
645 Default value is 0 (a full PL011 compliant UART is present).
647 - ``PLAT``: Choose a platform to build TF-A for. The chosen platform name
648 must be subdirectory of any depth under ``plat/``, and must contain a
649 platform makefile named ``platform.mk``. For example, to build TF-A for the
650 Arm Juno board, select PLAT=juno.
652 - ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image
653 instead of the normal boot flow. When defined, it must specify the entry
654 point address for the preloaded BL33 image. This option is incompatible with
655 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority
656 over ``PRELOADED_BL33_BASE``.
658 - ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset
659 vector address can be programmed or is fixed on the platform. It can take
660 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a
661 programmable reset address, it is expected that a CPU will start executing
662 code directly at the right address, both on a cold and warm reset. In this
663 case, there is no need to identify the entrypoint on boot and the boot path
664 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface
665 does not need to be implemented in this case.
667 - ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats
668 possible for the PSCI power-state parameter: original and extended State-ID
669 formats. This flag if set to 1, configures the generic PSCI layer to use the
670 extended format. The default value of this flag is 0, which means by default
671 the original power-state format is used by the PSCI implementation. This flag
672 should be specified by the platform makefile and it governs the return value
673 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is
674 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be
677 - ``RAS_EXTENSION``: When set to ``1``, enable Armv8.2 RAS features. RAS features
678 are an optional extension for pre-Armv8.2 CPUs, but are mandatory for Armv8.2
681 When ``RAS_EXTENSION`` is set to ``1``, ``HANDLE_EA_EL3_FIRST`` must also be
684 This option is disabled by default.
686 - ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead
687 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
688 entrypoint) or 1 (CPU reset to BL31 entrypoint).
689 The default value is 0.
691 - ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
692 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
693 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
694 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
696 - ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
697 file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
698 file name will be used to save the key.
700 - ``SANITIZE_UB``: This option enables the Undefined Behaviour sanitizer. It
701 can take 3 values: 'off' (default), 'on' and 'trap'. When using 'trap',
702 gcc and clang will insert calls to ``__builtin_trap`` on detected
703 undefined behaviour, which defaults to a ``brk`` instruction. When using
704 'on', undefined behaviour is translated to a call to special handlers which
705 prints the exact location of the problem and its cause and then panics.
708 Because of the space penalty of the Undefined Behaviour sanitizer,
709 this option will increase the size of the binary. Depending on the
710 memory constraints of the target platform, it may not be possible to
711 enable the sanitizer for all images (BL1 and BL2 are especially
712 likely to be memory constrained). We recommend that the
713 sanitizer is enabled only in debug builds.
715 - ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the
716 certificate generation tool to save the keys used to establish the Chain of
717 Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
719 - ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
720 If a SCP_BL2 image is present then this option must be passed for the ``fip``
723 - ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
724 file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
725 this file name will be used to save the key.
727 - ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
728 optional. It is only needed if the platform makefile specifies that it
729 is required in order to build the ``fwu_fip`` target.
731 - ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software
732 Delegated Exception Interface to BL31 image. This defaults to ``0``.
734 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be
737 - ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
738 isolated on separate memory pages. This is a trade-off between security and
739 memory usage. See "Isolating code and read-only data on separate memory
740 pages" section in `Firmware Design`_. This flag is disabled by default and
741 affects all BL images.
743 - ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
744 This build option is only valid if ``ARCH=aarch64``. The value should be
745 the path to the directory containing the SPD source, relative to
746 ``services/spd/``; the directory is expected to contain a makefile called
749 - ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
750 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
751 execution in BL1 just before handing over to BL31. At this point, all
752 firmware images have been loaded in memory, and the MMU and caches are
753 turned off. Refer to the "Debugging options" section for more details.
755 - ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
756 secure interrupts (caught through the FIQ line). Platforms can enable
757 this directive if they need to handle such interruption. When enabled,
758 the FIQ are handled in monitor mode and non secure world is not allowed
759 to mask these events. Platforms that enable FIQ handling in SP_MIN shall
760 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0.
762 - ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board
763 Boot feature. When set to '1', BL1 and BL2 images include support to load
764 and verify the certificates and images in a FIP, and BL1 includes support
765 for the Firmware Update. The default value is '0'. Generation and inclusion
766 of certificates in the FIP and FWU_FIP depends upon the value of the
767 ``GENERATE_COT`` option.
770 This option depends on ``CREATE_KEYS`` to be enabled. If the keys
771 already exist in disk, they will be overwritten without further notice.
773 - ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
774 specifies the file that contains the Trusted World private key in PEM
775 format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
777 - ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or
778 synchronous, (see "Initializing a BL32 Image" section in
779 `Firmware Design`_). It can take the value 0 (BL32 is initialized using
780 synchronous method) or 1 (BL32 is initialized using asynchronous method).
783 - ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt
784 routing model which routes non-secure interrupts asynchronously from TSP
785 to EL3 causing immediate preemption of TSP. The EL3 is responsible
786 for saving and restoring the TSP context in this routing model. The
787 default routing model (when the value is 0) is to route non-secure
788 interrupts to TSP allowing it to save its context and hand over
789 synchronously to EL3 via an SMC.
792 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT``
793 must also be set to ``1``.
795 - ``USE_ARM_LINK``: This flag determines whether to enable support for ARM
796 linker. When the ``LINKER`` build variable points to the armlink linker,
797 this flag is enabled automatically. To enable support for armlink, platforms
798 will have to provide a scatter file for the BL image. Currently, Tegra
799 platforms use the armlink support to compile BL3-1 images.
801 - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
802 memory region in the BL memory map or not (see "Use of Coherent memory in
803 TF-A" section in `Firmware Design`_). It can take the value 1
804 (Coherent memory region is included) or 0 (Coherent memory region is
805 excluded). Default is 1.
807 - ``USE_ROMLIB``: This flag determines whether library at ROM will be used.
808 This feature creates a library of functions to be placed in ROM and thus
809 reduces SRAM usage. Refer to `Library at ROM`_ for further details. Default
812 - ``V``: Verbose build. If assigned anything other than 0, the build commands
813 are printed. Default is 0.
815 - ``VERSION_STRING``: String used in the log output for each TF-A image.
816 Defaults to a string formed by concatenating the version number, build type
819 - ``W``: Warning level. Some compiler warning options of interest have been
820 regrouped and put in the root Makefile. This flag can take the values 0 to 3,
821 each level enabling more warning options. Default is 0.
823 - ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
824 the CPU after warm boot. This is applicable for platforms which do not
825 require interconnect programming to enable cache coherency (eg: single
826 cluster platforms). If this option is enabled, then warm boot path
827 enables D-caches immediately after enabling MMU. This option defaults to 0.
830 Arm development platform specific build options
831 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
833 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
834 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
835 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
836 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
839 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
840 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
841 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
842 match the frame used by the Non-Secure image (normally the Linux kernel).
843 Default is true (access to the frame is allowed).
845 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
846 By default, Arm platforms use a watchdog to trigger a system reset in case
847 an error is encountered during the boot process (for example, when an image
848 could not be loaded or authenticated). The watchdog is enabled in the early
849 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
850 Trusted Watchdog may be disabled at build time for testing or development
853 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
854 have specific values at boot. This boolean option allows the Trusted Firmware
855 to have a Linux kernel image as BL33 by preparing the registers to these
856 values before jumping to BL33. This option defaults to 0 (disabled). For
857 AArch64 ``RESET_TO_BL31`` and for AArch32 ``RESET_TO_SP_MIN`` must be 1 when
858 using it. If this option is set to 1, ``ARM_PRELOADED_DTB_BASE`` must be set
859 to the location of a device tree blob (DTB) already loaded in memory. The
860 Linux Image address must be specified using the ``PRELOADED_BL33_BASE``
863 - ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
864 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
865 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
866 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
867 this flag is 0. Note that this option is not used on FVP platforms.
869 - ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding
870 for the construction of composite state-ID in the power-state parameter.
871 The existing PSCI clients currently do not support this encoding of
872 State-ID yet. Hence this flag is used to configure whether to use the
873 recommended State-ID encoding or not. The default value of this flag is 0,
874 in which case the platform is configured to expect NULL in the State-ID
875 field of power-state parameter.
877 - ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
878 location of the ROTPK hash returned by the function ``plat_get_rotpk_info()``
879 for Arm platforms. Depending on the selected option, the proper private key
880 must be specified using the ``ROT_KEY`` option when building the Trusted
881 Firmware. This private key will be used by the certificate generation tool
882 to sign the BL2 and Trusted Key certificates. Available options for
883 ``ARM_ROTPK_LOCATION`` are:
885 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
886 registers. The private key corresponding to this ROTPK hash is not
888 - ``devel_rsa`` : return a development public key hash embedded in the BL1
889 and BL2 binaries. This hash has been obtained from the RSA public key
890 ``arm_rotpk_rsa.der``, located in ``plat/arm/board/common/rotpk``. To use
891 this option, ``arm_rotprivk_rsa.pem`` must be specified as ``ROT_KEY`` when
892 creating the certificates.
893 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1
894 and BL2 binaries. This hash has been obtained from the ECDSA public key
895 ``arm_rotpk_ecdsa.der``, located in ``plat/arm/board/common/rotpk``. To use
896 this option, ``arm_rotprivk_ecdsa.pem`` must be specified as ``ROT_KEY``
897 when creating the certificates.
899 - ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
901 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
902 - ``tdram`` : Trusted DRAM (if available)
903 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
904 configured by the TrustZone controller)
906 - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
907 of the translation tables library instead of version 2. It is set to 0 by
908 default, which selects version 2.
910 - ``ARM_CRYPTOCELL_INTEG`` : bool option to enable TF-A to invoke Arm®
911 TrustZone® CryptoCell functionality for Trusted Board Boot on capable Arm
912 platforms. If this option is specified, then the path to the CryptoCell
913 SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
915 For a better understanding of these options, the Arm development platform memory
916 map is explained in the `Firmware Design`_.
918 Arm CSS platform specific build options
919 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
921 - ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version
922 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
923 compatible change to the MTL protocol, used for AP/SCP communication.
924 TF-A no longer supports earlier SCP versions. If this option is set to 1
925 then TF-A will detect if an earlier version is in use. Default is 1.
927 - ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
928 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
929 during boot. Default is 1.
931 - ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
932 instead of SCPI/BOM driver for communicating with the SCP during power
933 management operations and for SCP RAM Firmware transfer. If this option
934 is set to 1, then SCMI/SDS drivers will be used. Default is 0.
936 Arm FVP platform specific build options
937 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
939 - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
940 build the topology tree within TF-A. By default TF-A is configured for dual
941 cluster topology and this option can be used to override the default value.
943 - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
944 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
945 explained in the options below:
947 - ``FVP_CCI`` : The CCI driver is selected. This is the default
948 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
949 - ``FVP_CCN`` : The CCN driver is selected. This is the default
950 if ``FVP_CLUSTER_COUNT`` > 2.
952 - ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
953 a single cluster. This option defaults to 4.
955 - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
956 in the system. This option defaults to 1. Note that the build option
957 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
959 - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
961 - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
962 - ``FVP_GICV2`` : The GICv2 only driver is selected
963 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
965 - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
966 for functions that wait for an arbitrary time length (udelay and mdelay).
967 The default value is 0.
969 - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
970 to DTB and packaged in FIP as the HW_CONFIG. See `Firmware Design`_ for
971 details on HW_CONFIG. By default, this is initialized to a sensible DTS
972 file in ``fdts/`` folder depending on other build options. But some cases,
973 like shifted affinity format for MPIDR, cannot be detected at build time
974 and this option is needed to specify the appropriate DTS file.
976 - ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
977 FIP. See `Firmware Design`_ for details on HW_CONFIG. This option is
978 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
979 HW_CONFIG blob instead of the DTS file. This option is useful to override
980 the default HW_CONFIG selected by the build system.
982 ARM JUNO platform specific build options
983 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
985 - ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
986 Media Protection (TZ-MP1). Default value of this flag is 0.
991 To compile a debug version and make the build more verbose use
995 make PLAT=<platform> DEBUG=1 V=1 all
997 AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
998 example DS-5) might not support this and may need an older version of DWARF
999 symbols to be emitted by GCC. This can be achieved by using the
1000 ``-gdwarf-<version>`` flag, with the version being set to 2 or 3. Setting the
1001 version to 2 is recommended for DS-5 versions older than 5.16.
1003 When debugging logic problems it might also be useful to disable all compiler
1004 optimizations by using ``-O0``.
1007 Using ``-O0`` could cause output images to be larger and base addresses
1008 might need to be recalculated (see the **Memory layout on Arm development
1009 platforms** section in the `Firmware Design`_).
1011 Extra debug options can be passed to the build system by setting ``CFLAGS`` or
1016 CFLAGS='-O0 -gdwarf-2' \
1017 make PLAT=<platform> DEBUG=1 V=1 all
1019 Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be
1020 ignored as the linker is called directly.
1022 It is also possible to introduce an infinite loop to help in debugging the
1023 post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the
1024 ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
1025 section. In this case, the developer may take control of the target using a
1026 debugger when indicated by the console output. When using DS-5, the following
1027 commands can be used:
1031 # Stop target execution
1035 # Prepare your debugging environment, e.g. set breakpoints
1038 # Jump over the debug loop
1039 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4
1044 Building the Test Secure Payload
1045 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1047 The TSP is coupled with a companion runtime service in the BL31 firmware,
1048 called the TSPD. Therefore, if you intend to use the TSP, the BL31 image
1049 must be recompiled as well. For more information on SPs and SPDs, see the
1050 `Secure-EL1 Payloads and Dispatchers`_ section in the `Firmware Design`_.
1052 First clean the TF-A build directory to get rid of any previous BL31 binary.
1053 Then to build the TSP image use:
1057 make PLAT=<platform> SPD=tspd all
1059 An additional boot loader binary file is created in the ``build`` directory:
1063 build/<platform>/<build-type>/bl32.bin
1066 Building and using the FIP tool
1067 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1069 Firmware Image Package (FIP) is a packaging format used by TF-A to package
1070 firmware images in a single binary. The number and type of images that should
1071 be packed in a FIP is platform specific and may include TF-A images and other
1072 firmware images required by the platform. For example, most platforms require
1073 a BL33 image which corresponds to the normal world bootloader (e.g. UEFI or
1076 The TF-A build system provides the make target ``fip`` to create a FIP file
1077 for the specified platform using the FIP creation tool included in the TF-A
1078 project. Examples below show how to build a FIP file for FVP, packaging TF-A
1085 make PLAT=fvp BL33=<path-to>/bl33.bin fip
1091 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=<path-to>/bl33.bin fip
1093 The resulting FIP may be found in:
1097 build/fvp/<build-type>/fip.bin
1099 For advanced operations on FIP files, it is also possible to independently build
1100 the tool and create or modify FIPs using this tool. To do this, follow these
1103 It is recommended to remove old artifacts before building the tool:
1107 make -C tools/fiptool clean
1113 make [DEBUG=1] [V=1] fiptool
1115 The tool binary can be located in:
1119 ./tools/fiptool/fiptool
1121 Invoking the tool with ``help`` will print a help message with all available
1124 Example 1: create a new Firmware package ``fip.bin`` that contains BL2 and BL31:
1128 ./tools/fiptool/fiptool create \
1129 --tb-fw build/<platform>/<build-type>/bl2.bin \
1130 --soc-fw build/<platform>/<build-type>/bl31.bin \
1133 Example 2: view the contents of an existing Firmware package:
1137 ./tools/fiptool/fiptool info <path-to>/fip.bin
1139 Example 3: update the entries of an existing Firmware package:
1143 # Change the BL2 from Debug to Release version
1144 ./tools/fiptool/fiptool update \
1145 --tb-fw build/<platform>/release/bl2.bin \
1146 build/<platform>/debug/fip.bin
1148 Example 4: unpack all entries from an existing Firmware package:
1152 # Images will be unpacked to the working directory
1153 ./tools/fiptool/fiptool unpack <path-to>/fip.bin
1155 Example 5: remove an entry from an existing Firmware package:
1159 ./tools/fiptool/fiptool remove \
1160 --tb-fw build/<platform>/debug/fip.bin
1162 Note that if the destination FIP file exists, the create, update and
1163 remove operations will automatically overwrite it.
1165 The unpack operation will fail if the images already exist at the
1166 destination. In that case, use -f or --force to continue.
1168 More information about FIP can be found in the `Firmware Design`_ document.
1170 Building FIP images with support for Trusted Board Boot
1171 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1173 Trusted Board Boot primarily consists of the following two features:
1175 - Image Authentication, described in `Trusted Board Boot`_, and
1176 - Firmware Update, described in `Firmware Update`_
1178 The following steps should be followed to build FIP and (optionally) FWU_FIP
1179 images with support for these features:
1181 #. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
1182 modules by checking out a recent version of the `mbed TLS Repository`_. It
1183 is important to use a version that is compatible with TF-A and fixes any
1184 known security vulnerabilities. See `mbed TLS Security Center`_ for more
1185 information. The latest version of TF-A is tested with tag
1188 The ``drivers/auth/mbedtls/mbedtls_*.mk`` files contain the list of mbed TLS
1189 source files the modules depend upon.
1190 ``include/drivers/auth/mbedtls/mbedtls_config.h`` contains the configuration
1191 options required to build the mbed TLS sources.
1193 Note that the mbed TLS library is licensed under the Apache version 2.0
1194 license. Using mbed TLS source code will affect the licensing of TF-A
1195 binaries that are built using this library.
1197 #. To build the FIP image, ensure the following command line variables are set
1198 while invoking ``make`` to build TF-A:
1200 - ``MBEDTLS_DIR=<path of the directory containing mbed TLS sources>``
1201 - ``TRUSTED_BOARD_BOOT=1``
1202 - ``GENERATE_COT=1``
1204 In the case of Arm platforms, the location of the ROTPK hash must also be
1205 specified at build time. Two locations are currently supported (see
1206 ``ARM_ROTPK_LOCATION`` build option):
1208 - ``ARM_ROTPK_LOCATION=regs``: the ROTPK hash is obtained from the Trusted
1209 root-key storage registers present in the platform. On Juno, this
1210 registers are read-only. On FVP Base and Cortex models, the registers
1211 are read-only, but the value can be specified using the command line
1212 option ``bp.trusted_key_storage.public_key`` when launching the model.
1213 On both Juno and FVP models, the default value corresponds to an
1214 ECDSA-SECP256R1 public key hash, whose private part is not currently
1217 - ``ARM_ROTPK_LOCATION=devel_rsa``: use the ROTPK hash that is hardcoded
1218 in the Arm platform port. The private/public RSA key pair may be
1219 found in ``plat/arm/board/common/rotpk``.
1221 - ``ARM_ROTPK_LOCATION=devel_ecdsa``: use the ROTPK hash that is hardcoded
1222 in the Arm platform port. The private/public ECDSA key pair may be
1223 found in ``plat/arm/board/common/rotpk``.
1225 Example of command line using RSA development keys:
1229 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1230 make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1231 ARM_ROTPK_LOCATION=devel_rsa \
1232 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1233 BL33=<path-to>/<bl33_image> \
1236 The result of this build will be the bl1.bin and the fip.bin binaries. This
1237 FIP will include the certificates corresponding to the Chain of Trust
1238 described in the TBBR-client document. These certificates can also be found
1239 in the output build directory.
1241 #. The optional FWU_FIP contains any additional images to be loaded from
1242 Non-Volatile storage during the `Firmware Update`_ process. To build the
1243 FWU_FIP, any FWU images required by the platform must be specified on the
1244 command line. On Arm development platforms like Juno, these are:
1246 - NS_BL2U. The AP non-secure Firmware Updater image.
1247 - SCP_BL2U. The SCP Firmware Update Configuration image.
1249 Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
1250 targets using RSA development:
1254 MBEDTLS_DIR=<path of the directory containing mbed TLS sources> \
1255 make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
1256 ARM_ROTPK_LOCATION=devel_rsa \
1257 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
1258 BL33=<path-to>/<bl33_image> \
1259 SCP_BL2=<path-to>/<scp_bl2_image> \
1260 SCP_BL2U=<path-to>/<scp_bl2u_image> \
1261 NS_BL2U=<path-to>/<ns_bl2u_image> \
1265 The BL2U image will be built by default and added to the FWU_FIP.
1266 The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
1267 to the command line above.
1270 Building and installing the non-secure and SCP FWU images (NS_BL1U,
1271 NS_BL2U and SCP_BL2U) is outside the scope of this document.
1273 The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
1274 Both the FIP and FWU_FIP will include the certificates corresponding to the
1275 Chain of Trust described in the TBBR-client document. These certificates
1276 can also be found in the output build directory.
1278 Building the Certificate Generation Tool
1279 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1281 The ``cert_create`` tool is built as part of the TF-A build process when the
1282 ``fip`` make target is specified and TBB is enabled (as described in the
1283 previous section), but it can also be built separately with the following
1288 make PLAT=<platform> [DEBUG=1] [V=1] certtool
1290 For platforms that require their own IDs in certificate files, the generic
1291 'cert_create' tool can be built with the following command. Note that the target
1292 platform must define its IDs within a ``platform_oid.h`` header file for the
1297 make PLAT=<platform> USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
1299 ``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
1300 verbose. The following command should be used to obtain help about the tool:
1304 ./tools/cert_create/cert_create -h
1306 Building a FIP for Juno and FVP
1307 -------------------------------
1309 This section provides Juno and FVP specific instructions to build Trusted
1310 Firmware, obtain the additional required firmware, and pack it all together in
1311 a single FIP binary. It assumes that a `Linaro Release`_ has been installed.
1314 Pre-built binaries for AArch32 are available from Linaro Release 16.12
1315 onwards. Before that release, pre-built binaries are only available for
1319 Follow the full instructions for one platform before switching to a
1320 different one. Mixing instructions for different platforms may result in
1324 The uboot image downloaded by the Linaro workspace script does not always
1325 match the uboot image packaged as BL33 in the corresponding fip file. It is
1326 recommended to use the version that is packaged in the fip file using the
1330 For the FVP, the kernel FDT is packaged in FIP during build and loaded
1331 by the firmware at runtime. See `Obtaining the Flattened Device Trees`_
1332 section for more info on selecting the right FDT to use.
1334 #. Clean the working directory
1340 #. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
1342 Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
1343 package included in the Linaro release:
1348 make [DEBUG=1] [V=1] fiptool
1350 # Unpack firmware images from Linaro FIP
1351 ./tools/fiptool/fiptool unpack <path-to-linaro-release>/fip.bin
1353 The unpack operation will result in a set of binary images extracted to the
1354 current working directory. The SCP_BL2 image corresponds to
1355 ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
1358 The fiptool will complain if the images to be unpacked already
1359 exist in the current directory. If that is the case, either delete those
1360 files or use the ``--force`` option to overwrite.
1363 For AArch32, the instructions below assume that nt-fw.bin is a
1364 normal world boot loader that supports AArch32.
1366 #. Build TF-A images and create a new FIP for FVP
1371 make PLAT=fvp BL33=nt-fw.bin all fip
1374 make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip
1376 #. Build TF-A images and create a new FIP for Juno
1380 Building for AArch64 on Juno simply requires the addition of ``SCP_BL2``
1381 as a build parameter.
1385 make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
1389 Hardware restrictions on Juno prevent cold reset into AArch32 execution mode,
1390 therefore BL1 and BL2 must be compiled for AArch64, and BL32 is compiled
1391 separately for AArch32.
1393 - Before building BL32, the environment variable ``CROSS_COMPILE`` must point
1394 to the AArch32 Linaro cross compiler.
1398 export CROSS_COMPILE=<path-to-aarch32-gcc>/bin/arm-linux-gnueabihf-
1400 - Build BL32 in AArch32.
1404 make ARCH=aarch32 PLAT=juno AARCH32_SP=sp_min \
1405 RESET_TO_SP_MIN=1 JUNO_AARCH32_EL3_RUNTIME=1 bl32
1407 - Save ``bl32.bin`` to a temporary location and clean the build products.
1411 cp <path-to-build>/bl32.bin <path-to-temporary>
1414 - Before building BL1 and BL2, the environment variable ``CROSS_COMPILE``
1415 must point to the AArch64 Linaro cross compiler.
1419 export CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu-
1421 - The following parameters should be used to build BL1 and BL2 in AArch64
1422 and point to the BL32 file.
1426 make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
1427 BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
1428 BL32=<path-to-temporary>/bl32.bin all fip
1430 The resulting BL1 and FIP images may be found in:
1435 ./build/juno/release/bl1.bin
1436 ./build/juno/release/fip.bin
1439 ./build/fvp/release/bl1.bin
1440 ./build/fvp/release/fip.bin
1443 Booting Firmware Update images
1444 -------------------------------------
1446 When Firmware Update (FWU) is enabled there are at least 2 new images
1447 that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
1453 The new images must be programmed in flash memory by adding
1454 an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1455 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1456 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1457 programming" for more information. User should ensure these do not
1458 overlap with any other entries in the file.
1462 NOR10UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1463 NOR10ADDRESS: 0x00400000 ;Image Flash Address [ns_bl2u_base_address]
1464 NOR10FILE: \SOFTWARE\fwu_fip.bin ;Image File Name
1465 NOR10LOAD: 00000000 ;Image Load Address
1466 NOR10ENTRY: 00000000 ;Image Entry Point
1468 NOR11UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
1469 NOR11ADDRESS: 0x03EB8000 ;Image Flash Address [ns_bl1u_base_address]
1470 NOR11FILE: \SOFTWARE\ns_bl1u.bin ;Image File Name
1471 NOR11LOAD: 00000000 ;Image Load Address
1473 The address ns_bl1u_base_address is the value of NS_BL1U_BASE - 0x8000000.
1474 In the same way, the address ns_bl2u_base_address is the value of
1475 NS_BL2U_BASE - 0x8000000.
1480 The additional fip images must be loaded with:
1484 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
1485 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
1487 The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
1488 In the same way, the address ns_bl2u_base_address is the value of
1492 EL3 payloads alternative boot flow
1493 ----------------------------------
1495 On a pre-production system, the ability to execute arbitrary, bare-metal code at
1496 the highest exception level is required. It allows full, direct access to the
1497 hardware, for example to run silicon soak tests.
1499 Although it is possible to implement some baremetal secure firmware from
1500 scratch, this is a complex task on some platforms, depending on the level of
1501 configuration required to put the system in the expected state.
1503 Rather than booting a baremetal application, a possible compromise is to boot
1504 ``EL3 payloads`` through TF-A instead. This is implemented as an alternative
1505 boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
1506 other BL images and passing control to BL31. It reduces the complexity of
1507 developing EL3 baremetal code by:
1509 - putting the system into a known architectural state;
1510 - taking care of platform secure world initialization;
1511 - loading the SCP_BL2 image if required by the platform.
1513 When booting an EL3 payload on Arm standard platforms, the configuration of the
1514 TrustZone controller is simplified such that only region 0 is enabled and is
1515 configured to permit secure access only. This gives full access to the whole
1516 DRAM to the EL3 payload.
1518 The system is left in the same state as when entering BL31 in the default boot
1519 flow. In particular:
1522 - Current state is AArch64;
1523 - Little-endian data access;
1524 - All exceptions disabled;
1528 Booting an EL3 payload
1529 ~~~~~~~~~~~~~~~~~~~~~~
1531 The EL3 payload image is a standalone image and is not part of the FIP. It is
1532 not loaded by TF-A. Therefore, there are 2 possible scenarios:
1534 - The EL3 payload may reside in non-volatile memory (NVM) and execute in
1535 place. In this case, booting it is just a matter of specifying the right
1536 address in NVM through ``EL3_PAYLOAD_BASE`` when building TF-A.
1538 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
1541 To help in the latter scenario, the ``SPIN_ON_BL1_EXIT=1`` build option can be
1542 used. The infinite loop that it introduces in BL1 stops execution at the right
1543 moment for a debugger to take control of the target and load the payload (for
1544 example, over JTAG).
1546 It is expected that this loading method will work in most cases, as a debugger
1547 connection is usually available in a pre-production system. The user is free to
1548 use any other platform-specific mechanism to load the EL3 payload, though.
1550 Booting an EL3 payload on FVP
1551 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1553 The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
1554 the secondary CPUs holding pen to work properly. Unfortunately, its reset value
1555 is undefined on the FVP platform and the FVP platform code doesn't clear it.
1556 Therefore, one must modify the way the model is normally invoked in order to
1557 clear the mailbox at start-up.
1559 One way to do that is to create an 8-byte file containing all zero bytes using
1560 the following command:
1564 dd if=/dev/zero of=mailbox.dat bs=1 count=8
1566 and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
1567 using the following model parameters:
1571 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
1572 --data=mailbox.dat@0x04000000 [Foundation FVP]
1574 To provide the model with the EL3 payload image, the following methods may be
1577 #. If the EL3 payload is able to execute in place, it may be programmed into
1578 flash memory. On Base Cortex and AEM FVPs, the following model parameter
1579 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
1584 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
1586 On Foundation FVP, there is no flash loader component and the EL3 payload
1587 may be programmed anywhere in flash using method 3 below.
1589 #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
1590 command may be used to load the EL3 payload ELF image over JTAG:
1594 load <path-to>/el3-payload.elf
1596 #. The EL3 payload may be pre-loaded in volatile memory using the following
1601 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
1602 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
1604 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
1605 used when building TF-A.
1607 Booting an EL3 payload on Juno
1608 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1610 If the EL3 payload is able to execute in place, it may be programmed in flash
1611 memory by adding an entry in the ``SITE1/HBI0262x/images.txt`` configuration file
1612 on the Juno SD card (where ``x`` depends on the revision of the Juno board).
1613 Refer to the `Juno Getting Started Guide`_, section 2.3 "Flash memory
1614 programming" for more information.
1616 Alternatively, the same DS-5 command mentioned in the FVP section above can
1617 be used to load the EL3 payload's ELF file over JTAG on Juno.
1619 Preloaded BL33 alternative boot flow
1620 ------------------------------------
1622 Some platforms have the ability to preload BL33 into memory instead of relying
1623 on TF-A to load it. This may simplify packaging of the normal world code and
1624 improve performance in a development environment. When secure world cold boot
1625 is complete, TF-A simply jumps to a BL33 base address provided at build time.
1627 For this option to be used, the ``PRELOADED_BL33_BASE`` build option has to be
1628 used when compiling TF-A. For example, the following command will create a FIP
1629 without a BL33 and prepare to jump to a BL33 image loaded at address
1634 make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip
1636 Boot of a preloaded kernel image on Base FVP
1637 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1639 The following example uses a simplified boot flow by directly jumping from the
1640 TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
1641 useful if both the kernel and the device tree blob (DTB) are already present in
1642 memory (like in FVP).
1644 For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
1645 address ``0x82000000``, the firmware can be built like this:
1649 CROSS_COMPILE=aarch64-linux-gnu- \
1650 make PLAT=fvp DEBUG=1 \
1652 ARM_LINUX_KERNEL_AS_BL33=1 \
1653 PRELOADED_BL33_BASE=0x80080000 \
1654 ARM_PRELOADED_DTB_BASE=0x82000000 \
1657 Now, it is needed to modify the DTB so that the kernel knows the address of the
1658 ramdisk. The following script generates a patched DTB from the provided one,
1659 assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
1660 script assumes that the user is using a ramdisk image prepared for U-Boot, like
1661 the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
1662 offset in ``INITRD_START`` has to be removed.
1668 # Path to the input DTB
1669 KERNEL_DTB=<path-to>/<fdt>
1670 # Path to the output DTB
1671 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
1672 # Base address of the ramdisk
1673 INITRD_BASE=0x84000000
1674 # Path to the ramdisk
1675 INITRD=<path-to>/<ramdisk.img>
1677 # Skip uboot header (64 bytes)
1678 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
1679 INITRD_SIZE=$(stat -Lc %s ${INITRD})
1680 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
1682 CHOSEN_NODE=$(echo \
1685 linux,initrd-start = <${INITRD_START}>; \
1686 linux,initrd-end = <${INITRD_END}>; \
1690 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
1691 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
1693 And the FVP binary can be run with the following command:
1697 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1698 -C pctl.startup=0.0.0.0 \
1699 -C bp.secure_memory=1 \
1700 -C cluster0.NUM_CORES=4 \
1701 -C cluster1.NUM_CORES=4 \
1702 -C cache_state_modelled=1 \
1703 -C cluster0.cpu0.RVBAR=0x04020000 \
1704 -C cluster0.cpu1.RVBAR=0x04020000 \
1705 -C cluster0.cpu2.RVBAR=0x04020000 \
1706 -C cluster0.cpu3.RVBAR=0x04020000 \
1707 -C cluster1.cpu0.RVBAR=0x04020000 \
1708 -C cluster1.cpu1.RVBAR=0x04020000 \
1709 -C cluster1.cpu2.RVBAR=0x04020000 \
1710 -C cluster1.cpu3.RVBAR=0x04020000 \
1711 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \
1712 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
1713 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1714 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
1716 Boot of a preloaded kernel image on Juno
1717 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1719 The Trusted Firmware must be compiled in a similar way as for FVP explained
1720 above. The process to load binaries to memory is the one explained in
1721 `Booting an EL3 payload on Juno`_.
1723 Running the software on FVP
1724 ---------------------------
1726 The latest version of the AArch64 build of TF-A has been tested on the following
1727 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1728 (64-bit host machine only).
1731 The FVP models used are Version 11.6 Build 45, unless otherwise stated.
1733 - ``FVP_Base_AEMv8A-AEMv8A``
1734 - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
1735 - ``FVP_Base_RevC-2xAEMv8A``
1736 - ``FVP_Base_Cortex-A32x4``
1737 - ``FVP_Base_Cortex-A35x4``
1738 - ``FVP_Base_Cortex-A53x4``
1739 - ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
1740 - ``FVP_Base_Cortex-A55x4``
1741 - ``FVP_Base_Cortex-A57x1-A53x1``
1742 - ``FVP_Base_Cortex-A57x2-A53x4``
1743 - ``FVP_Base_Cortex-A57x4-A53x4``
1744 - ``FVP_Base_Cortex-A57x4``
1745 - ``FVP_Base_Cortex-A72x4-A53x4``
1746 - ``FVP_Base_Cortex-A72x4``
1747 - ``FVP_Base_Cortex-A73x4-A53x4``
1748 - ``FVP_Base_Cortex-A73x4``
1749 - ``FVP_Base_Cortex-A75x4``
1750 - ``FVP_Base_Cortex-A76x4``
1751 - ``FVP_Base_Cortex-A76AEx4``
1752 - ``FVP_Base_Cortex-A76AEx8``
1753 - ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36)
1754 - ``FVP_Base_Neoverse-N1x4``
1755 - ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
1756 - ``FVP_CSS_SGM-775`` (Version 11.3 build 42)
1757 - ``FVP_RD_E1Edge`` (Version 11.3 build 42)
1759 - ``Foundation_Platform``
1761 The latest version of the AArch32 build of TF-A has been tested on the following
1762 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
1763 (64-bit host machine only).
1765 - ``FVP_Base_AEMv8A-AEMv8A``
1766 - ``FVP_Base_Cortex-A32x4``
1769 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
1770 is not compatible with legacy GIC configurations. Therefore this FVP does not
1771 support these legacy GIC configurations.
1774 The build numbers quoted above are those reported by launching the FVP
1775 with the ``--version`` parameter.
1778 Linaro provides a ramdisk image in prebuilt FVP configurations and full
1779 file systems that can be downloaded separately. To run an FVP with a virtio
1780 file system image an additional FVP configuration option
1781 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
1785 The software will not work on Version 1.0 of the Foundation FVP.
1786 The commands below would report an ``unhandled argument`` error in this case.
1789 FVPs can be launched with ``--cadi-server`` option such that a
1790 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
1794 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
1795 the internal synchronisation timings changed compared to older versions of
1796 the models. The models can be launched with ``-Q 100`` option if they are
1797 required to match the run time characteristics of the older versions.
1799 The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be
1800 downloaded for free from `Arm's website`_.
1802 The Cortex-A models listed above are also available to download from
1805 Please refer to the FVP documentation for a detailed description of the model
1806 parameter options. A brief description of the important ones that affect TF-A
1807 and normal world software behavior is provided below.
1809 Obtaining the Flattened Device Trees
1810 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1812 Depending on the FVP configuration and Linux configuration used, different
1813 FDT files are required. FDT source files for the Foundation and Base FVPs can
1814 be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
1815 a subset of the Base FVP components. For example, the Foundation FVP lacks
1816 CLCD and MMC support, and has only one CPU cluster.
1819 It is not recommended to use the FDTs built along the kernel because not
1820 all FDTs are available from there.
1822 The dynamic configuration capability is enabled in the firmware for FVPs.
1823 This means that the firmware can authenticate and load the FDT if present in
1824 FIP. A default FDT is packaged into FIP during the build based on
1825 the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
1826 or ``FVP_HW_CONFIG_DTS`` build options (refer to the
1827 `Arm FVP platform specific build options`_ section for detail on the options).
1829 - ``fvp-base-gicv2-psci.dts``
1831 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1832 affinities and with Base memory map configuration.
1834 - ``fvp-base-gicv2-psci-aarch32.dts``
1836 For use with models such as the Cortex-A32 Base FVPs without shifted
1837 affinities and running Linux in AArch32 state with Base memory map
1840 - ``fvp-base-gicv3-psci.dts``
1842 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
1843 affinities and with Base memory map configuration and Linux GICv3 support.
1845 - ``fvp-base-gicv3-psci-1t.dts``
1847 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
1848 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
1850 - ``fvp-base-gicv3-psci-dynamiq.dts``
1852 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
1853 single cluster, single threaded CPUs, Base memory map configuration and Linux
1856 - ``fvp-base-gicv3-psci-aarch32.dts``
1858 For use with models such as the Cortex-A32 Base FVPs without shifted
1859 affinities and running Linux in AArch32 state with Base memory map
1860 configuration and Linux GICv3 support.
1862 - ``fvp-foundation-gicv2-psci.dts``
1864 For use with Foundation FVP with Base memory map configuration.
1866 - ``fvp-foundation-gicv3-psci.dts``
1868 (Default) For use with Foundation FVP with Base memory map configuration
1869 and Linux GICv3 support.
1871 Running on the Foundation FVP with reset to BL1 entrypoint
1872 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1874 The following ``Foundation_Platform`` parameters should be used to boot Linux with
1875 4 CPUs using the AArch64 build of TF-A.
1879 <path-to>/Foundation_Platform \
1885 --data="<path-to>/<bl1-binary>"@0x0 \
1886 --data="<path-to>/<FIP-binary>"@0x08000000 \
1887 --data="<path-to>/<kernel-binary>"@0x80080000 \
1888 --data="<path-to>/<ramdisk-binary>"@0x84000000
1892 - BL1 is loaded at the start of the Trusted ROM.
1893 - The Firmware Image Package is loaded at the start of NOR FLASH0.
1894 - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
1895 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
1896 - The default use-case for the Foundation FVP is to use the ``--gicv3`` option
1897 and enable the GICv3 device in the model. Note that without this option,
1898 the Foundation FVP defaults to legacy (Versatile Express) memory map which
1899 is not supported by TF-A.
1900 - In order for TF-A to run correctly on the Foundation FVP, the architecture
1901 versions must match. The Foundation FVP defaults to the highest v8.x
1902 version it supports but the default build for TF-A is for v8.0. To avoid
1903 issues either start the Foundation FVP to use v8.0 architecture using the
1904 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
1907 Running on the AEMv8 Base FVP with reset to BL1 entrypoint
1908 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1910 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
1911 with 8 CPUs using the AArch64 build of TF-A.
1915 <path-to>/FVP_Base_RevC-2xAEMv8A \
1916 -C pctl.startup=0.0.0.0 \
1917 -C bp.secure_memory=1 \
1918 -C bp.tzc_400.diagnostics=1 \
1919 -C cluster0.NUM_CORES=4 \
1920 -C cluster1.NUM_CORES=4 \
1921 -C cache_state_modelled=1 \
1922 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1923 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1924 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1925 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1928 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
1929 a specific DTS for all the CPUs to be loaded.
1931 Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
1932 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1934 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
1935 with 8 CPUs using the AArch32 build of TF-A.
1939 <path-to>/FVP_Base_AEMv8A-AEMv8A \
1940 -C pctl.startup=0.0.0.0 \
1941 -C bp.secure_memory=1 \
1942 -C bp.tzc_400.diagnostics=1 \
1943 -C cluster0.NUM_CORES=4 \
1944 -C cluster1.NUM_CORES=4 \
1945 -C cache_state_modelled=1 \
1946 -C cluster0.cpu0.CONFIG64=0 \
1947 -C cluster0.cpu1.CONFIG64=0 \
1948 -C cluster0.cpu2.CONFIG64=0 \
1949 -C cluster0.cpu3.CONFIG64=0 \
1950 -C cluster1.cpu0.CONFIG64=0 \
1951 -C cluster1.cpu1.CONFIG64=0 \
1952 -C cluster1.cpu2.CONFIG64=0 \
1953 -C cluster1.cpu3.CONFIG64=0 \
1954 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1955 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1956 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1957 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1959 Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
1960 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1962 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
1963 boot Linux with 8 CPUs using the AArch64 build of TF-A.
1967 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
1968 -C pctl.startup=0.0.0.0 \
1969 -C bp.secure_memory=1 \
1970 -C bp.tzc_400.diagnostics=1 \
1971 -C cache_state_modelled=1 \
1972 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1973 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1974 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1975 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1977 Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
1978 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1980 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
1981 boot Linux with 4 CPUs using the AArch32 build of TF-A.
1985 <path-to>/FVP_Base_Cortex-A32x4 \
1986 -C pctl.startup=0.0.0.0 \
1987 -C bp.secure_memory=1 \
1988 -C bp.tzc_400.diagnostics=1 \
1989 -C cache_state_modelled=1 \
1990 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
1991 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
1992 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
1993 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
1995 Running on the AEMv8 Base FVP with reset to BL31 entrypoint
1996 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1998 The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
1999 with 8 CPUs using the AArch64 build of TF-A.
2003 <path-to>/FVP_Base_RevC-2xAEMv8A \
2004 -C pctl.startup=0.0.0.0 \
2005 -C bp.secure_memory=1 \
2006 -C bp.tzc_400.diagnostics=1 \
2007 -C cluster0.NUM_CORES=4 \
2008 -C cluster1.NUM_CORES=4 \
2009 -C cache_state_modelled=1 \
2010 -C cluster0.cpu0.RVBAR=0x04010000 \
2011 -C cluster0.cpu1.RVBAR=0x04010000 \
2012 -C cluster0.cpu2.RVBAR=0x04010000 \
2013 -C cluster0.cpu3.RVBAR=0x04010000 \
2014 -C cluster1.cpu0.RVBAR=0x04010000 \
2015 -C cluster1.cpu1.RVBAR=0x04010000 \
2016 -C cluster1.cpu2.RVBAR=0x04010000 \
2017 -C cluster1.cpu3.RVBAR=0x04010000 \
2018 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2019 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
2020 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2021 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2022 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2023 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2027 - If Position Independent Executable (PIE) support is enabled for BL31
2028 in this config, it can be loaded at any valid address for execution.
2030 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
2031 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
2032 parameter is needed to load the individual bootloader images in memory.
2033 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
2034 Payload. For the same reason, the FDT needs to be compiled from the DT source
2035 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
2038 - The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
2039 specific DTS for all the CPUs to be loaded.
2041 - The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
2042 X and Y are the cluster and CPU numbers respectively, is used to set the
2043 reset vector for each core.
2045 - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
2046 changing the value of
2047 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
2050 Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
2051 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2053 The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
2054 with 8 CPUs using the AArch32 build of TF-A.
2058 <path-to>/FVP_Base_AEMv8A-AEMv8A \
2059 -C pctl.startup=0.0.0.0 \
2060 -C bp.secure_memory=1 \
2061 -C bp.tzc_400.diagnostics=1 \
2062 -C cluster0.NUM_CORES=4 \
2063 -C cluster1.NUM_CORES=4 \
2064 -C cache_state_modelled=1 \
2065 -C cluster0.cpu0.CONFIG64=0 \
2066 -C cluster0.cpu1.CONFIG64=0 \
2067 -C cluster0.cpu2.CONFIG64=0 \
2068 -C cluster0.cpu3.CONFIG64=0 \
2069 -C cluster1.cpu0.CONFIG64=0 \
2070 -C cluster1.cpu1.CONFIG64=0 \
2071 -C cluster1.cpu2.CONFIG64=0 \
2072 -C cluster1.cpu3.CONFIG64=0 \
2073 -C cluster0.cpu0.RVBAR=0x04002000 \
2074 -C cluster0.cpu1.RVBAR=0x04002000 \
2075 -C cluster0.cpu2.RVBAR=0x04002000 \
2076 -C cluster0.cpu3.RVBAR=0x04002000 \
2077 -C cluster1.cpu0.RVBAR=0x04002000 \
2078 -C cluster1.cpu1.RVBAR=0x04002000 \
2079 -C cluster1.cpu2.RVBAR=0x04002000 \
2080 -C cluster1.cpu3.RVBAR=0x04002000 \
2081 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2082 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2083 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2084 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2085 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2088 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
2089 It should match the address programmed into the RVBAR register as well.
2091 Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
2092 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2094 The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
2095 boot Linux with 8 CPUs using the AArch64 build of TF-A.
2099 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
2100 -C pctl.startup=0.0.0.0 \
2101 -C bp.secure_memory=1 \
2102 -C bp.tzc_400.diagnostics=1 \
2103 -C cache_state_modelled=1 \
2104 -C cluster0.cpu0.RVBARADDR=0x04010000 \
2105 -C cluster0.cpu1.RVBARADDR=0x04010000 \
2106 -C cluster0.cpu2.RVBARADDR=0x04010000 \
2107 -C cluster0.cpu3.RVBARADDR=0x04010000 \
2108 -C cluster1.cpu0.RVBARADDR=0x04010000 \
2109 -C cluster1.cpu1.RVBARADDR=0x04010000 \
2110 -C cluster1.cpu2.RVBARADDR=0x04010000 \
2111 -C cluster1.cpu3.RVBARADDR=0x04010000 \
2112 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
2113 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
2114 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2115 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2116 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2117 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2119 Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
2120 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2122 The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
2123 boot Linux with 4 CPUs using the AArch32 build of TF-A.
2127 <path-to>/FVP_Base_Cortex-A32x4 \
2128 -C pctl.startup=0.0.0.0 \
2129 -C bp.secure_memory=1 \
2130 -C bp.tzc_400.diagnostics=1 \
2131 -C cache_state_modelled=1 \
2132 -C cluster0.cpu0.RVBARADDR=0x04002000 \
2133 -C cluster0.cpu1.RVBARADDR=0x04002000 \
2134 -C cluster0.cpu2.RVBARADDR=0x04002000 \
2135 -C cluster0.cpu3.RVBARADDR=0x04002000 \
2136 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
2137 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
2138 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
2139 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
2140 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
2142 Running the software on Juno
2143 ----------------------------
2145 This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
2147 To execute the software stack on Juno, the version of the Juno board recovery
2148 image indicated in the `Linaro Release Notes`_ must be installed. If you have an
2149 earlier version installed or are unsure which version is installed, please
2150 re-install the recovery image by following the
2151 `Instructions for using Linaro's deliverables on Juno`_.
2153 Preparing TF-A images
2154 ~~~~~~~~~~~~~~~~~~~~~
2156 After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
2157 ``SOFTWARE/`` directory of the Juno SD card.
2159 Other Juno software information
2160 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2162 Please visit the `Arm Platforms Portal`_ to get support and obtain any other Juno
2163 software information. Please also refer to the `Juno Getting Started Guide`_ to
2164 get more detailed information about the Juno Arm development platform and how to
2167 Testing SYSTEM SUSPEND on Juno
2168 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2170 The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend
2171 to RAM. For more details refer to section 5.16 of `PSCI`_. To test system suspend
2172 on Juno, at the linux shell prompt, issue the following command:
2176 echo +10 > /sys/class/rtc/rtc0/wakealarm
2177 echo -n mem > /sys/power/state
2179 The Juno board should suspend to RAM and then wakeup after 10 seconds due to
2180 wakeup interrupt from RTC.
2184 *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
2186 .. _arm Developer page: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
2187 .. _Linaro: `Linaro Release Notes`_
2188 .. _Linaro Release: `Linaro Release Notes`_
2189 .. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
2190 .. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
2191 .. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
2192 .. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
2193 .. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
2194 .. _arm-trusted-firmware-a project page: https://review.trustedfirmware.org/admin/projects/TF-A/trusted-firmware-a
2195 .. _`Linux Coding Style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
2196 .. _Linux master tree: https://github.com/torvalds/linux/tree/master/
2197 .. _Dia: https://wiki.gnome.org/Apps/Dia/Download
2198 .. _here: psci-lib-integration-guide.rst
2199 .. _Trusted Board Boot: ../design/trusted-board-boot.rst
2200 .. _TB_FW_CONFIG for FVP: ../../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
2201 .. _Secure-EL1 Payloads and Dispatchers: ../design/firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
2202 .. _Firmware Update: ../components/firmware-update.rst
2203 .. _Firmware Design: ../design/firmware-design.rst
2204 .. _mbed TLS Repository: https://github.com/ARMmbed/mbedtls.git
2205 .. _mbed TLS Security Center: https://tls.mbed.org/security
2206 .. _Arm's website: `FVP models`_
2207 .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
2208 .. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
2209 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2210 .. _Secure Partition Manager Design guide: ../components/secure-partition-manager-design.rst
2211 .. _`Trusted Firmware-A Coding Guidelines`: ../process/coding-guidelines.rst
2212 .. _Library at ROM: ../components/romlib-design.rst