docs/plat/marvell/misc/mvebu-io-win.txt

   1 Marvell IO WIN address decoding bindings
   2 =====================================
   3
   4 IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
   5
   6 The IO WIN includes a description of the address decoding configuration.
   7
   8 Transactions that are decoded by CCU windows as IO peripheral, have an additional
   9 layer of decoding. This additional address decoding layer defines one of the
  10 following targets:
  11         0x0 = BootRom
  12         0x1 = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
  13         0x2 = SPI direct access
  14         0x3 = PCIe registers
  15         0x4 = MCI Port
  16         0x5 = PCIe port
  17
  18 Mandatory functions:
  19         - marvell_get_io_win_memory_map
  20                 returns the IO windows configuration and the number of windows
  21                 of the specific AP.
  22
  23 Mandatory structures:
  24         io_win_memory_map - Array that include the configuration of the windows
  25           every window/entry is a struct which has 3 parameters:
  26           - Base address of the window
  27           - Size of the window
  28           - Target-ID of the window
  29
  30 Example:
  31         struct addr_map_win io_win_memory_map[] = {
  32                 {0x00000000fe000000,    0x000000001f00000,      PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
  33                 {0x00000000ffe00000,    0x000000000100000,      PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
  34                 {0x00000000f6000000,    0x000000000100000,      MCIPHY_TID},    /* MCI window  1Mb for PHY-reg*/
  35         };