drivers/arm/css/scp/css_pm_scmi.c

   1 /*
   2  * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <assert.h>
   8 #include <string.h>
   9
  10 #include <arch_helpers.h>
  11 #include <common/debug.h>
  12 #include <drivers/arm/css/css_scp.h>
  13 #include <drivers/arm/css/scmi.h>
  14 #include <plat/arm/common/plat_arm.h>
  15 #include <plat/arm/css/common/css_pm.h>
  16 #include <plat/common/platform.h>
  17 #include <platform_def.h>
  18
  19 /*
  20  * This file implements the SCP helper functions using SCMI protocol.
  21  */
  22
  23 /*
  24  * SCMI power state parameter bit field encoding for ARM CSS platforms.
  25  *
  26  * 31  20 19       16 15      12 11       8 7        4 3         0
  27  * +-------------------------------------------------------------+
  28  * | SBZ | Max level |  Level 3 |  Level 2 |  Level 1 |  Level 0 |
  29  * |     |           |   state  |   state  |   state  |   state  |
  30  * +-------------------------------------------------------------+
  31  *
  32  * `Max level` encodes the highest level that has a valid power state
  33  * encoded in the power state.
  34  */
  35 #define SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT        16
  36 #define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH        4
  37 #define SCMI_PWR_STATE_MAX_PWR_LVL_MASK         \
  38                                 ((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1)
  39 #define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level)                \
  40                 (_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\
  41                                 << SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT
  42 #define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state)            \
  43                 (((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT)   \
  44                                 & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)
  45
  46 #define SCMI_PWR_STATE_LVL_WIDTH                4
  47 #define SCMI_PWR_STATE_LVL_MASK                 \
  48                                 ((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1)
  49 #define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state)              \
  50                 (_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK)    \
  51                                 << (SCMI_PWR_STATE_LVL_WIDTH * (_level))
  52 #define SCMI_GET_PWR_STATE_LVL(_power_state, _level)            \
  53                 (((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) &    \
  54                                 SCMI_PWR_STATE_LVL_MASK)
  55
  56 /*
  57  * The SCMI power state enumeration for a power domain level
  58  */
  59 typedef enum {
  60         scmi_power_state_off = 0,
  61         scmi_power_state_on = 1,
  62         scmi_power_state_sleep = 2,
  63 } scmi_power_state_t;
  64
  65 /*
  66  * The global handle for invoking the SCMI driver APIs after the driver
  67  * has been initialized.
  68  */
  69 static void *scmi_handle;
  70
  71 /* The SCMI channel global object */
  72 static scmi_channel_t channel;
  73
  74 ARM_SCMI_INSTANTIATE_LOCK;
  75
  76 /*
  77  * Helper function to suspend a CPU power domain and its parent power domains
  78  * if applicable.
  79  */
  80 void css_scp_suspend(const struct psci_power_state *target_state)
  81 {
  82         int ret;
  83
  84         /* At least power domain level 0 should be specified to be suspended */
  85         assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
  86                                                 ARM_LOCAL_STATE_OFF);
  87
  88         /* Check if power down at system power domain level is requested */
  89         if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) {
  90                 /* Issue SCMI command for SYSTEM_SUSPEND */
  91                 ret = scmi_sys_pwr_state_set(scmi_handle,
  92                                 SCMI_SYS_PWR_FORCEFUL_REQ,
  93                                 SCMI_SYS_PWR_SUSPEND);
  94                 if (ret != SCMI_E_SUCCESS) {
  95                         ERROR("SCMI system power domain suspend return 0x%x unexpected\n",
  96                                         ret);
  97                         panic();
  98                 }
  99                 return;
 100         }
 101 #if !HW_ASSISTED_COHERENCY
 102         unsigned int lvl;
 103         uint32_t scmi_pwr_state = 0;
 104         /*
 105          * If we reach here, then assert that power down at system power domain
 106          * level is running.
 107          */
 108         assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN);
 109
 110         /* For level 0, specify `scmi_power_state_sleep` as the power state */
 111         SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, ARM_PWR_LVL0,
 112                                                 scmi_power_state_sleep);
 113
 114         for (lvl = ARM_PWR_LVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
 115                 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN)
 116                         break;
 117
 118                 assert(target_state->pwr_domain_state[lvl] ==
 119                                                         ARM_LOCAL_STATE_OFF);
 120                 /*
 121                  * Specify `scmi_power_state_off` as power state for higher
 122                  * levels.
 123                  */
 124                 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
 125                                                 scmi_power_state_off);
 126         }
 127
 128         SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
 129
 130         ret = scmi_pwr_state_set(scmi_handle,
 131                 plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()],
 132                 scmi_pwr_state);
 133
 134         if (ret != SCMI_E_SUCCESS) {
 135                 ERROR("SCMI set power state command return 0x%x unexpected\n",
 136                                 ret);
 137                 panic();
 138         }
 139 #endif
 140 }
 141
 142 /*
 143  * Helper function to turn off a CPU power domain and its parent power domains
 144  * if applicable.
 145  */
 146 void css_scp_off(const struct psci_power_state *target_state)
 147 {
 148         unsigned int lvl = 0;
 149         int ret;
 150         uint32_t scmi_pwr_state = 0;
 151
 152         /* At-least the CPU level should be specified to be OFF */
 153         assert(target_state->pwr_domain_state[ARM_PWR_LVL0] ==
 154                                                         ARM_LOCAL_STATE_OFF);
 155
 156         /* PSCI CPU OFF cannot be used to turn OFF system power domain */
 157         assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN);
 158
 159         for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) {
 160                 if (target_state->pwr_domain_state[lvl] == ARM_LOCAL_STATE_RUN)
 161                         break;
 162
 163                 assert(target_state->pwr_domain_state[lvl] ==
 164                                                         ARM_LOCAL_STATE_OFF);
 165                 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
 166                                 scmi_power_state_off);
 167         }
 168
 169         SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
 170
 171         ret = scmi_pwr_state_set(scmi_handle,
 172                 plat_css_core_pos_to_scmi_dmn_id_map[plat_my_core_pos()],
 173                 scmi_pwr_state);
 174
 175         if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
 176                 ERROR("SCMI set power state command return 0x%x unexpected\n",
 177                                 ret);
 178                 panic();
 179         }
 180 }
 181
 182 /*
 183  * Helper function to turn ON a CPU power domain and its parent power domains
 184  * if applicable.
 185  */
 186 void css_scp_on(u_register_t mpidr)
 187 {
 188         unsigned int lvl = 0;
 189         int ret, core_pos;
 190         uint32_t scmi_pwr_state = 0;
 191
 192         for (; lvl <= PLAT_MAX_PWR_LVL; lvl++)
 193                 SCMI_SET_PWR_STATE_LVL(scmi_pwr_state, lvl,
 194                                 scmi_power_state_on);
 195
 196         SCMI_SET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state, lvl - 1);
 197
 198         core_pos = plat_core_pos_by_mpidr(mpidr);
 199         assert(core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT);
 200
 201         ret = scmi_pwr_state_set(scmi_handle,
 202                 plat_css_core_pos_to_scmi_dmn_id_map[core_pos],
 203                 scmi_pwr_state);
 204
 205         if (ret != SCMI_E_QUEUED && ret != SCMI_E_SUCCESS) {
 206                 ERROR("SCMI set power state command return 0x%x unexpected\n",
 207                                 ret);
 208                 panic();
 209         }
 210 }
 211
 212 /*
 213  * Helper function to get the power state of a power domain node as reported
 214  * by the SCP.
 215  */
 216 int css_scp_get_power_state(u_register_t mpidr, unsigned int power_level)
 217 {
 218         int ret, cpu_idx;
 219         uint32_t scmi_pwr_state = 0, lvl_state;
 220
 221         /* We don't support get power state at the system power domain level */
 222         if ((power_level > PLAT_MAX_PWR_LVL) ||
 223                         (power_level == CSS_SYSTEM_PWR_DMN_LVL)) {
 224                 WARN("Invalid power level %u specified for SCMI get power state\n",
 225                                 power_level);
 226                 return PSCI_E_INVALID_PARAMS;
 227         }
 228
 229         cpu_idx = plat_core_pos_by_mpidr(mpidr);
 230         assert(cpu_idx > -1);
 231
 232         ret = scmi_pwr_state_get(scmi_handle,
 233                 plat_css_core_pos_to_scmi_dmn_id_map[cpu_idx],
 234                 &scmi_pwr_state);
 235
 236         if (ret != SCMI_E_SUCCESS) {
 237                 WARN("SCMI get power state command return 0x%x unexpected\n",
 238                                 ret);
 239                 return PSCI_E_INVALID_PARAMS;
 240         }
 241
 242         /*
 243          * Find the maximum power level described in the get power state
 244          * command. If it is less than the requested power level, then assume
 245          * the requested power level is ON.
 246          */
 247         if (SCMI_GET_PWR_STATE_MAX_PWR_LVL(scmi_pwr_state) < power_level)
 248                 return HW_ON;
 249
 250         lvl_state = SCMI_GET_PWR_STATE_LVL(scmi_pwr_state, power_level);
 251         if (lvl_state == scmi_power_state_on)
 252                 return HW_ON;
 253
 254         assert((lvl_state == scmi_power_state_off) ||
 255                                 (lvl_state == scmi_power_state_sleep));
 256         return HW_OFF;
 257 }
 258
 259 void __dead2 css_scp_system_off(int state)
 260 {
 261         int ret;
 262
 263         /*
 264          * Disable GIC CPU interface to prevent pending interrupt from waking
 265          * up the AP from WFI.
 266          */
 267         plat_arm_gic_cpuif_disable();
 268
 269         /*
 270          * Issue SCMI command. First issue a graceful
 271          * request and if that fails force the request.
 272          */
 273         ret = scmi_sys_pwr_state_set(scmi_handle,
 274                         SCMI_SYS_PWR_FORCEFUL_REQ,
 275                         state);
 276
 277         if (ret != SCMI_E_SUCCESS) {
 278                 ERROR("SCMI system power state set 0x%x returns unexpected 0x%x\n",
 279                         state, ret);
 280                 panic();
 281         }
 282         wfi();
 283         ERROR("CSS set power state: operation not handled.\n");
 284         panic();
 285 }
 286
 287 /*
 288  * Helper function to shutdown the system via SCMI.
 289  */
 290 void __dead2 css_scp_sys_shutdown(void)
 291 {
 292         css_scp_system_off(SCMI_SYS_PWR_SHUTDOWN);
 293 }
 294
 295 /*
 296  * Helper function to reset the system via SCMI.
 297  */
 298 void __dead2 css_scp_sys_reboot(void)
 299 {
 300         css_scp_system_off(SCMI_SYS_PWR_COLD_RESET);
 301 }
 302
 303 static int scmi_ap_core_init(scmi_channel_t *ch)
 304 {
 305 #if PROGRAMMABLE_RESET_ADDRESS
 306         uint32_t version;
 307         int ret;
 308
 309         ret = scmi_proto_version(ch, SCMI_AP_CORE_PROTO_ID, &version);
 310         if (ret != SCMI_E_SUCCESS) {
 311                 WARN("SCMI AP core protocol version message failed\n");
 312                 return -1;
 313         }
 314
 315         if (!is_scmi_version_compatible(SCMI_AP_CORE_PROTO_VER, version)) {
 316                 WARN("SCMI AP core protocol version 0x%x incompatible with driver version 0x%x\n",
 317                         version, SCMI_AP_CORE_PROTO_VER);
 318                 return -1;
 319         }
 320         INFO("SCMI AP core protocol version 0x%x detected\n", version);
 321 #endif
 322         return 0;
 323 }
 324
 325 void __init plat_arm_pwrc_setup(void)
 326 {
 327         channel.info = plat_css_get_scmi_info();
 328         channel.lock = ARM_SCMI_LOCK_GET_INSTANCE;
 329         scmi_handle = scmi_init(&channel);
 330         if (scmi_handle == NULL) {
 331                 ERROR("SCMI Initialization failed\n");
 332                 panic();
 333         }
 334         if (scmi_ap_core_init(&channel) < 0) {
 335                 ERROR("SCMI AP core protocol initialization failed\n");
 336                 panic();
 337         }
 338 }
 339
 340 /******************************************************************************
 341  * This function overrides the default definition for ARM platforms. Initialize
 342  * the SCMI driver, query capability via SCMI and modify the PSCI capability
 343  * based on that.
 344  *****************************************************************************/
 345 const plat_psci_ops_t *css_scmi_override_pm_ops(plat_psci_ops_t *ops)
 346 {
 347         uint32_t msg_attr;
 348         int ret;
 349
 350         assert(scmi_handle);
 351
 352         /* Check that power domain POWER_STATE_SET message is supported */
 353         ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID,
 354                                 SCMI_PWR_STATE_SET_MSG, &msg_attr);
 355         if (ret != SCMI_E_SUCCESS) {
 356                 ERROR("Set power state command is not supported by SCMI\n");
 357                 panic();
 358         }
 359
 360         /*
 361          * Don't support PSCI NODE_HW_STATE call if SCMI doesn't support
 362          * POWER_STATE_GET message.
 363          */
 364         ret = scmi_proto_msg_attr(scmi_handle, SCMI_PWR_DMN_PROTO_ID,
 365                                 SCMI_PWR_STATE_GET_MSG, &msg_attr);
 366         if (ret != SCMI_E_SUCCESS)
 367                 ops->get_node_hw_state = NULL;
 368
 369         /* Check if the SCMI SYSTEM_POWER_STATE_SET message is supported */
 370         ret = scmi_proto_msg_attr(scmi_handle, SCMI_SYS_PWR_PROTO_ID,
 371                                 SCMI_SYS_PWR_STATE_SET_MSG, &msg_attr);
 372         if (ret != SCMI_E_SUCCESS) {
 373                 /* System power management operations are not supported */
 374                 ops->system_off = NULL;
 375                 ops->system_reset = NULL;
 376                 ops->get_sys_suspend_power_state = NULL;
 377         } else {
 378                 if (!(msg_attr & SCMI_SYS_PWR_SUSPEND_SUPPORTED)) {
 379                         /*
 380                          * System power management protocol is available, but
 381                          * it does not support SYSTEM SUSPEND.
 382                          */
 383                         ops->get_sys_suspend_power_state = NULL;
 384                 }
 385                 if (!(msg_attr & SCMI_SYS_PWR_WARM_RESET_SUPPORTED)) {
 386                         /*
 387                          * WARM reset is not available.
 388                          */
 389                         ops->system_reset2 = NULL;
 390                 }
 391         }
 392
 393         return ops;
 394 }
 395
 396 int css_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
 397 {
 398         if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET))
 399                 return PSCI_E_INVALID_PARAMS;
 400
 401         css_scp_system_off(SCMI_SYS_PWR_WARM_RESET);
 402         /*
 403          * css_scp_system_off cannot return (it is a __dead function),
 404          * but css_system_reset2 has to return some value, even in
 405          * this case.
 406          */
 407         return 0;
 408 }
 409
 410 #if PROGRAMMABLE_RESET_ADDRESS
 411 void plat_arm_program_trusted_mailbox(uintptr_t address)
 412 {
 413         int ret;
 414
 415         assert(scmi_handle);
 416         ret = scmi_ap_core_set_reset_addr(scmi_handle, address,
 417                 SCMI_AP_CORE_LOCK_ATTR);
 418         if (ret != SCMI_E_SUCCESS) {
 419                 ERROR("CSS: Failed to program reset address: %d\n", ret);
 420                 panic();
 421         }
 422 }
 423 #endif