2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
8 #include <arch_helpers.h>
11 #include <gic_common.h>
13 #include <interrupt_props.h>
15 #include "../common/gic_common_private.h"
16 #include "gicv2_private.h"
18 static const gicv2_driver_data_t
*driver_data
;
21 * Spinlock to guard registers needing read-modify-write. APIs protected by this
22 * spinlock are used either at boot time (when only a single CPU is active), or
23 * when the system is fully coherent.
25 static spinlock_t gic_lock
;
27 /*******************************************************************************
28 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
29 * and set the priority mask register to allow all interrupts to trickle in.
30 ******************************************************************************/
31 void gicv2_cpuif_enable(void)
36 assert(driver_data
->gicc_base
);
39 * Enable the Group 0 interrupts, FIQEn and disable Group 0/1
42 val
= CTLR_ENABLE_G0_BIT
| FIQ_EN_BIT
| FIQ_BYP_DIS_GRP0
;
43 val
|= IRQ_BYP_DIS_GRP0
| FIQ_BYP_DIS_GRP1
| IRQ_BYP_DIS_GRP1
;
45 /* Program the idle priority in the PMR */
46 gicc_write_pmr(driver_data
->gicc_base
, GIC_PRI_MASK
);
47 gicc_write_ctlr(driver_data
->gicc_base
, val
);
50 /*******************************************************************************
51 * Place the cpu interface in a state where it can never make a cpu exit wfi as
52 * as result of an asserted interrupt. This is critical for powering down a cpu
53 ******************************************************************************/
54 void gicv2_cpuif_disable(void)
59 assert(driver_data
->gicc_base
);
61 /* Disable secure, non-secure interrupts and disable their bypass */
62 val
= gicc_read_ctlr(driver_data
->gicc_base
);
63 val
&= ~(CTLR_ENABLE_G0_BIT
| CTLR_ENABLE_G1_BIT
);
64 val
|= FIQ_BYP_DIS_GRP1
| FIQ_BYP_DIS_GRP0
;
65 val
|= IRQ_BYP_DIS_GRP0
| IRQ_BYP_DIS_GRP1
;
66 gicc_write_ctlr(driver_data
->gicc_base
, val
);
69 /*******************************************************************************
70 * Per cpu gic distributor setup which will be done by all cpus after a cold
71 * boot/hotplug. This marks out the secure SPIs and PPIs & enables them.
72 ******************************************************************************/
73 void gicv2_pcpu_distif_init(void)
78 assert(driver_data
->gicd_base
);
81 if (driver_data
->interrupt_props
!= NULL
) {
83 gicv2_secure_ppi_sgi_setup_props(driver_data
->gicd_base
,
84 driver_data
->interrupt_props
,
85 driver_data
->interrupt_props_num
);
88 assert(driver_data
->g0_interrupt_array
);
89 gicv2_secure_ppi_sgi_setup(driver_data
->gicd_base
,
90 driver_data
->g0_interrupt_num
,
91 driver_data
->g0_interrupt_array
);
95 /* Enable G0 interrupts if not already */
96 ctlr
= gicd_read_ctlr(driver_data
->gicd_base
);
97 if ((ctlr
& CTLR_ENABLE_G0_BIT
) == 0) {
98 gicd_write_ctlr(driver_data
->gicd_base
,
99 ctlr
| CTLR_ENABLE_G0_BIT
);
103 /*******************************************************************************
104 * Global gic distributor init which will be done by the primary cpu after a
105 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
106 * then enables the secure GIC distributor interface.
107 ******************************************************************************/
108 void gicv2_distif_init(void)
113 assert(driver_data
->gicd_base
);
115 /* Disable the distributor before going further */
116 ctlr
= gicd_read_ctlr(driver_data
->gicd_base
);
117 gicd_write_ctlr(driver_data
->gicd_base
,
118 ctlr
& ~(CTLR_ENABLE_G0_BIT
| CTLR_ENABLE_G1_BIT
));
120 /* Set the default attribute of all SPIs */
121 gicv2_spis_configure_defaults(driver_data
->gicd_base
);
123 #if !ERROR_DEPRECATED
124 if (driver_data
->interrupt_props
!= NULL
) {
126 gicv2_secure_spis_configure_props(driver_data
->gicd_base
,
127 driver_data
->interrupt_props
,
128 driver_data
->interrupt_props_num
);
129 #if !ERROR_DEPRECATED
131 assert(driver_data
->g0_interrupt_array
);
133 /* Configure the G0 SPIs */
134 gicv2_secure_spis_configure(driver_data
->gicd_base
,
135 driver_data
->g0_interrupt_num
,
136 driver_data
->g0_interrupt_array
);
140 /* Re-enable the secure SPIs now that they have been configured */
141 gicd_write_ctlr(driver_data
->gicd_base
, ctlr
| CTLR_ENABLE_G0_BIT
);
144 /*******************************************************************************
145 * Initialize the ARM GICv2 driver with the provided platform inputs
146 ******************************************************************************/
147 void gicv2_driver_init(const gicv2_driver_data_t
*plat_driver_data
)
149 unsigned int gic_version
;
150 assert(plat_driver_data
);
151 assert(plat_driver_data
->gicd_base
);
152 assert(plat_driver_data
->gicc_base
);
154 #if !ERROR_DEPRECATED
155 if (plat_driver_data
->interrupt_props
== NULL
) {
156 /* Interrupt properties array size must be 0 */
157 assert(plat_driver_data
->interrupt_props_num
== 0);
159 /* The platform should provide a list of secure interrupts */
160 assert(plat_driver_data
->g0_interrupt_array
);
163 * If there are no interrupts of a particular type, then the
164 * number of interrupts of that type should be 0 and vice-versa.
166 assert(plat_driver_data
->g0_interrupt_array
?
167 plat_driver_data
->g0_interrupt_num
:
168 plat_driver_data
->g0_interrupt_num
== 0);
171 assert(plat_driver_data
->interrupt_props
!= NULL
);
172 assert(plat_driver_data
->interrupt_props_num
> 0);
175 /* Ensure that this is a GICv2 system */
176 gic_version
= gicd_read_pidr2(plat_driver_data
->gicd_base
);
177 gic_version
= (gic_version
>> PIDR2_ARCH_REV_SHIFT
)
178 & PIDR2_ARCH_REV_MASK
;
181 * GICv1 with security extension complies with trusted firmware
182 * GICv2 driver as far as virtualization and few tricky power
183 * features are not used. GICv2 features that are not supported
184 * by GICv1 with Security Extensions are:
185 * - virtual interrupt support.
187 * - writeable GIC state register (for power sequences)
188 * - interrupt priority drop.
189 * - interrupt signal bypass.
191 assert(gic_version
== ARCH_REV_GICV2
|| gic_version
== ARCH_REV_GICV1
);
193 driver_data
= plat_driver_data
;
196 * The GIC driver data is initialized by the primary CPU with caches
197 * enabled. When the secondary CPU boots up, it initializes the
198 * GICC/GICR interface with the caches disabled. Hence flush the
199 * driver_data to ensure coherency. This is not required if the
200 * platform has HW_ASSISTED_COHERENCY enabled.
202 #if !HW_ASSISTED_COHERENCY
203 flush_dcache_range((uintptr_t) &driver_data
, sizeof(driver_data
));
204 flush_dcache_range((uintptr_t) driver_data
, sizeof(*driver_data
));
206 INFO("ARM GICv2 driver initialized\n");
209 /******************************************************************************
210 * This function returns whether FIQ is enabled in the GIC CPU interface.
211 *****************************************************************************/
212 unsigned int gicv2_is_fiq_enabled(void)
214 unsigned int gicc_ctlr
;
217 assert(driver_data
->gicc_base
);
219 gicc_ctlr
= gicc_read_ctlr(driver_data
->gicc_base
);
220 return (gicc_ctlr
>> FIQ_EN_SHIFT
) & 0x1;
223 /*******************************************************************************
224 * This function returns the type of the highest priority pending interrupt at
225 * the GIC cpu interface. The return values can be one of the following :
226 * PENDING_G1_INTID : The interrupt type is non secure Group 1.
227 * 0 - 1019 : The interrupt type is secure Group 0.
228 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
229 * sufficient priority to be signaled
230 ******************************************************************************/
231 unsigned int gicv2_get_pending_interrupt_type(void)
234 assert(driver_data
->gicc_base
);
236 return gicc_read_hppir(driver_data
->gicc_base
) & INT_ID_MASK
;
239 /*******************************************************************************
240 * This function returns the id of the highest priority pending interrupt at
241 * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no
243 ******************************************************************************/
244 unsigned int gicv2_get_pending_interrupt_id(void)
249 assert(driver_data
->gicc_base
);
251 id
= gicc_read_hppir(driver_data
->gicc_base
) & INT_ID_MASK
;
254 * Find out which non-secure interrupt it is under the assumption that
255 * the GICC_CTLR.AckCtl bit is 0.
257 if (id
== PENDING_G1_INTID
)
258 id
= gicc_read_ahppir(driver_data
->gicc_base
) & INT_ID_MASK
;
263 /*******************************************************************************
264 * This functions reads the GIC cpu interface Interrupt Acknowledge register
265 * to start handling the pending secure 0 interrupt. It returns the
266 * contents of the IAR.
267 ******************************************************************************/
268 unsigned int gicv2_acknowledge_interrupt(void)
271 assert(driver_data
->gicc_base
);
273 return gicc_read_IAR(driver_data
->gicc_base
);
276 /*******************************************************************************
277 * This functions writes the GIC cpu interface End Of Interrupt register with
278 * the passed value to finish handling the active secure group 0 interrupt.
279 ******************************************************************************/
280 void gicv2_end_of_interrupt(unsigned int id
)
283 assert(driver_data
->gicc_base
);
285 gicc_write_EOIR(driver_data
->gicc_base
, id
);
288 /*******************************************************************************
289 * This function returns the type of the interrupt id depending upon the group
290 * this interrupt has been configured under by the interrupt controller i.e.
291 * group0 secure or group1 non secure. It returns zero for Group 0 secure and
292 * one for Group 1 non secure interrupt.
293 ******************************************************************************/
294 unsigned int gicv2_get_interrupt_group(unsigned int id
)
297 assert(driver_data
->gicd_base
);
299 return gicd_get_igroupr(driver_data
->gicd_base
, id
);
302 /*******************************************************************************
303 * This function returns the priority of the interrupt the processor is
304 * currently servicing.
305 ******************************************************************************/
306 unsigned int gicv2_get_running_priority(void)
309 assert(driver_data
->gicc_base
);
311 return gicc_read_rpr(driver_data
->gicc_base
);
314 /*******************************************************************************
315 * This function sets the GICv2 target mask pattern for the current PE. The PE
316 * target mask is used to translate linear PE index (returned by platform core
317 * position) to a bit mask used when targeting interrupts to a PE, viz. when
318 * raising SGIs and routing SPIs.
319 ******************************************************************************/
320 void gicv2_set_pe_target_mask(unsigned int proc_num
)
323 assert(driver_data
->gicd_base
);
324 assert(driver_data
->target_masks
);
325 assert(proc_num
< GICV2_MAX_TARGET_PE
);
326 assert(proc_num
< driver_data
->target_masks_num
);
328 /* Return if the target mask is already populated */
329 if (driver_data
->target_masks
[proc_num
])
333 * Update target register corresponding to this CPU and flush for it to
334 * be visible to other CPUs.
336 if (driver_data
->target_masks
[proc_num
] == 0) {
337 driver_data
->target_masks
[proc_num
] =
338 gicv2_get_cpuif_id(driver_data
->gicd_base
);
339 #if !HW_ASSISTED_COHERENCY
341 * PEs only update their own masks. Primary updates it with
342 * caches on. But because secondaries does it with caches off,
343 * all updates go to memory directly, and there's no danger of
344 * secondaries overwriting each others' mask, despite
345 * target_masks[] not being cache line aligned.
347 flush_dcache_range((uintptr_t)
348 &driver_data
->target_masks
[proc_num
],
349 sizeof(driver_data
->target_masks
[proc_num
]));
354 /*******************************************************************************
355 * This function returns the active status of the interrupt (either because the
356 * state is active, or active and pending).
357 ******************************************************************************/
358 unsigned int gicv2_get_interrupt_active(unsigned int id
)
361 assert(driver_data
->gicd_base
);
362 assert(id
<= MAX_SPI_ID
);
364 return gicd_get_isactiver(driver_data
->gicd_base
, id
);
367 /*******************************************************************************
368 * This function enables the interrupt identified by id.
369 ******************************************************************************/
370 void gicv2_enable_interrupt(unsigned int id
)
373 assert(driver_data
->gicd_base
);
374 assert(id
<= MAX_SPI_ID
);
377 * Ensure that any shared variable updates depending on out of band
378 * interrupt trigger are observed before enabling interrupt.
381 gicd_set_isenabler(driver_data
->gicd_base
, id
);
384 /*******************************************************************************
385 * This function disables the interrupt identified by id.
386 ******************************************************************************/
387 void gicv2_disable_interrupt(unsigned int id
)
390 assert(driver_data
->gicd_base
);
391 assert(id
<= MAX_SPI_ID
);
394 * Disable interrupt, and ensure that any shared variable updates
395 * depending on out of band interrupt trigger are observed afterwards.
397 gicd_set_icenabler(driver_data
->gicd_base
, id
);
401 /*******************************************************************************
402 * This function sets the interrupt priority as supplied for the given interrupt
404 ******************************************************************************/
405 void gicv2_set_interrupt_priority(unsigned int id
, unsigned int priority
)
408 assert(driver_data
->gicd_base
);
409 assert(id
<= MAX_SPI_ID
);
411 gicd_set_ipriorityr(driver_data
->gicd_base
, id
, priority
);
414 /*******************************************************************************
415 * This function assigns group for the interrupt identified by id. The group can
416 * be any of GICV2_INTR_GROUP*
417 ******************************************************************************/
418 void gicv2_set_interrupt_type(unsigned int id
, unsigned int type
)
421 assert(driver_data
->gicd_base
);
422 assert(id
<= MAX_SPI_ID
);
424 /* Serialize read-modify-write to Distributor registers */
425 spin_lock(&gic_lock
);
427 case GICV2_INTR_GROUP1
:
428 gicd_set_igroupr(driver_data
->gicd_base
, id
);
430 case GICV2_INTR_GROUP0
:
431 gicd_clr_igroupr(driver_data
->gicd_base
, id
);
436 spin_unlock(&gic_lock
);
439 /*******************************************************************************
440 * This function raises the specified SGI to requested targets.
442 * The proc_num parameter must be the linear index of the target PE in the
444 ******************************************************************************/
445 void gicv2_raise_sgi(int sgi_num
, int proc_num
)
447 unsigned int sgir_val
, target
;
450 assert(proc_num
< GICV2_MAX_TARGET_PE
);
451 assert(driver_data
->gicd_base
);
454 * Target masks array must have been supplied, and the core position
457 assert(driver_data
->target_masks
);
458 assert(proc_num
< driver_data
->target_masks_num
);
460 /* Don't raise SGI if the mask hasn't been populated */
461 target
= driver_data
->target_masks
[proc_num
];
464 sgir_val
= GICV2_SGIR_VALUE(SGIR_TGT_SPECIFIC
, target
, sgi_num
);
467 * Ensure that any shared variable updates depending on out of band
468 * interrupt trigger are observed before raising SGI.
471 gicd_write_sgir(driver_data
->gicd_base
, sgir_val
);
474 /*******************************************************************************
475 * This function sets the interrupt routing for the given SPI interrupt id.
476 * The interrupt routing is specified in routing mode. The proc_num parameter is
477 * linear index of the PE to target SPI. When proc_num < 0, the SPI may target
479 ******************************************************************************/
480 void gicv2_set_spi_routing(unsigned int id
, int proc_num
)
485 assert(driver_data
->gicd_base
);
487 assert(id
>= MIN_SPI_ID
&& id
<= MAX_SPI_ID
);
490 * Target masks array must have been supplied, and the core position
493 assert(driver_data
->target_masks
);
494 assert(proc_num
< GICV2_MAX_TARGET_PE
);
495 assert(proc_num
< driver_data
->target_masks_num
);
499 target
= GIC_TARGET_CPU_MASK
;
501 /* Don't route interrupt if the mask hasn't been populated */
502 target
= driver_data
->target_masks
[proc_num
];
506 gicd_set_itargetsr(driver_data
->gicd_base
, id
, target
);
509 /*******************************************************************************
510 * This function clears the pending status of an interrupt identified by id.
511 ******************************************************************************/
512 void gicv2_clear_interrupt_pending(unsigned int id
)
515 assert(driver_data
->gicd_base
);
517 /* SGIs can't be cleared pending */
518 assert(id
>= MIN_PPI_ID
);
521 * Clear pending interrupt, and ensure that any shared variable updates
522 * depending on out of band interrupt trigger are observed afterwards.
524 gicd_set_icpendr(driver_data
->gicd_base
, id
);
528 /*******************************************************************************
529 * This function sets the pending status of an interrupt identified by id.
530 ******************************************************************************/
531 void gicv2_set_interrupt_pending(unsigned int id
)
534 assert(driver_data
->gicd_base
);
536 /* SGIs can't be cleared pending */
537 assert(id
>= MIN_PPI_ID
);
540 * Ensure that any shared variable updates depending on out of band
541 * interrupt trigger are observed before setting interrupt pending.
544 gicd_set_ispendr(driver_data
->gicd_base
, id
);
547 /*******************************************************************************
548 * This function sets the PMR register with the supplied value. Returns the
550 ******************************************************************************/
551 unsigned int gicv2_set_pmr(unsigned int mask
)
553 unsigned int old_mask
;
556 assert(driver_data
->gicc_base
);
558 old_mask
= gicc_read_pmr(driver_data
->gicc_base
);
561 * Order memory updates w.r.t. PMR write, and ensure they're visible
562 * before potential out of band interrupt trigger because of PMR update.
565 gicc_write_pmr(driver_data
->gicc_base
, mask
);