2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <common/interrupt_props.h>
13 #include <drivers/arm/gicv3.h>
14 #include <lib/spinlock.h>
16 #include "gicv3_private.h"
18 const gicv3_driver_data_t
*gicv3_driver_data
;
21 * Spinlock to guard registers needing read-modify-write. APIs protected by this
22 * spinlock are used either at boot time (when only a single CPU is active), or
23 * when the system is fully coherent.
25 static spinlock_t gic_lock
;
28 * Redistributor power operations are weakly bound so that they can be
31 #pragma weak gicv3_rdistif_off
32 #pragma weak gicv3_rdistif_on
35 /* Helper macros to save and restore GICD registers to and from the context */
36 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
38 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
39 int_id += (1U << REG##_SHIFT)) { \
40 gicd_write_##reg(base, int_id, \
41 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \
45 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
47 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
48 int_id += (1U << REG##_SHIFT)) { \
49 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\
50 gicd_read_##reg(base, int_id); \
55 /*******************************************************************************
56 * This function initialises the ARM GICv3 driver in EL3 with provided platform
58 ******************************************************************************/
59 void __init
gicv3_driver_init(const gicv3_driver_data_t
*plat_driver_data
)
61 unsigned int gic_version
;
62 unsigned int gicv2_compat
;
64 assert(plat_driver_data
!= NULL
);
65 assert(plat_driver_data
->gicd_base
!= 0U);
66 assert(plat_driver_data
->rdistif_num
!= 0U);
67 assert(plat_driver_data
->rdistif_base_addrs
!= NULL
);
71 assert((plat_driver_data
->interrupt_props_num
!= 0U) ?
72 (plat_driver_data
->interrupt_props
!= NULL
) : 1);
74 /* Check for system register support */
76 assert((read_id_pfr1() &
77 (ID_PFR1_GIC_MASK
<< ID_PFR1_GIC_SHIFT
)) != 0U);
79 assert((read_id_aa64pfr0_el1() &
80 (ID_AA64PFR0_GIC_MASK
<< ID_AA64PFR0_GIC_SHIFT
)) != 0U);
81 #endif /* !__aarch64__ */
83 /* The GIC version should be 3.0 */
84 gic_version
= gicd_read_pidr2(plat_driver_data
->gicd_base
);
85 gic_version
>>= PIDR2_ARCH_REV_SHIFT
;
86 gic_version
&= PIDR2_ARCH_REV_MASK
;
87 assert(gic_version
== ARCH_REV_GICV3
);
90 * Find out whether the GIC supports the GICv2 compatibility mode.
91 * The ARE_S bit resets to 0 if supported
93 gicv2_compat
= gicd_read_ctlr(plat_driver_data
->gicd_base
);
94 gicv2_compat
>>= CTLR_ARE_S_SHIFT
;
95 gicv2_compat
= gicv2_compat
& CTLR_ARE_S_MASK
;
97 if (plat_driver_data
->gicr_base
!= 0U) {
99 * Find the base address of each implemented Redistributor interface.
100 * The number of interfaces should be equal to the number of CPUs in the
101 * system. The memory for saving these addresses has to be allocated by
104 gicv3_rdistif_base_addrs_probe(plat_driver_data
->rdistif_base_addrs
,
105 plat_driver_data
->rdistif_num
,
106 plat_driver_data
->gicr_base
,
107 plat_driver_data
->mpidr_to_core_pos
);
108 #if !HW_ASSISTED_COHERENCY
110 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
112 flush_dcache_range((uintptr_t)(plat_driver_data
->rdistif_base_addrs
),
113 plat_driver_data
->rdistif_num
*
114 sizeof(*(plat_driver_data
->rdistif_base_addrs
)));
117 gicv3_driver_data
= plat_driver_data
;
120 * The GIC driver data is initialized by the primary CPU with caches
121 * enabled. When the secondary CPU boots up, it initializes the
122 * GICC/GICR interface with the caches disabled. Hence flush the
123 * driver data to ensure coherency. This is not required if the
124 * platform has HW_ASSISTED_COHERENCY enabled.
126 #if !HW_ASSISTED_COHERENCY
127 flush_dcache_range((uintptr_t)&gicv3_driver_data
,
128 sizeof(gicv3_driver_data
));
129 flush_dcache_range((uintptr_t)gicv3_driver_data
,
130 sizeof(*gicv3_driver_data
));
133 INFO("GICv3 with%s legacy support detected."
134 " ARM GICv3 driver initialized in EL3\n",
135 (gicv2_compat
== 0U) ? "" : "out");
139 /*******************************************************************************
140 * This function initialises the GIC distributor interface based upon the data
141 * provided by the platform while initialising the driver.
142 ******************************************************************************/
143 void __init
gicv3_distif_init(void)
145 unsigned int bitmap
= 0;
147 assert(gicv3_driver_data
!= NULL
);
148 assert(gicv3_driver_data
->gicd_base
!= 0U);
153 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
154 * the ARE_S bit. The Distributor might generate a system error
157 gicd_clr_ctlr(gicv3_driver_data
->gicd_base
,
159 CTLR_ENABLE_G1S_BIT
|
160 CTLR_ENABLE_G1NS_BIT
,
163 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
164 gicd_set_ctlr(gicv3_driver_data
->gicd_base
,
165 CTLR_ARE_S_BIT
| CTLR_ARE_NS_BIT
, RWP_TRUE
);
167 /* Set the default attribute of all SPIs */
168 gicv3_spis_config_defaults(gicv3_driver_data
->gicd_base
);
170 bitmap
= gicv3_secure_spis_config_props(
171 gicv3_driver_data
->gicd_base
,
172 gicv3_driver_data
->interrupt_props
,
173 gicv3_driver_data
->interrupt_props_num
);
175 /* Enable the secure SPIs now that they have been configured */
176 gicd_set_ctlr(gicv3_driver_data
->gicd_base
, bitmap
, RWP_TRUE
);
179 /*******************************************************************************
180 * This function initialises the GIC Redistributor interface of the calling CPU
181 * (identified by the 'proc_num' parameter) based upon the data provided by the
182 * platform while initialising the driver.
183 ******************************************************************************/
184 void gicv3_rdistif_init(unsigned int proc_num
)
187 unsigned int bitmap
= 0U;
190 assert(gicv3_driver_data
!= NULL
);
191 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
192 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
193 assert(gicv3_driver_data
->gicd_base
!= 0U);
195 ctlr
= gicd_read_ctlr(gicv3_driver_data
->gicd_base
);
196 assert((ctlr
& CTLR_ARE_S_BIT
) != 0U);
200 /* Power on redistributor */
201 gicv3_rdistif_on(proc_num
);
203 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
204 assert(gicr_base
!= 0U);
206 /* Set the default attribute of all SGIs and PPIs */
207 gicv3_ppi_sgi_config_defaults(gicr_base
);
209 bitmap
= gicv3_secure_ppi_sgi_config_props(gicr_base
,
210 gicv3_driver_data
->interrupt_props
,
211 gicv3_driver_data
->interrupt_props_num
);
213 /* Enable interrupt groups as required, if not already */
214 if ((ctlr
& bitmap
) != bitmap
)
215 gicd_set_ctlr(gicv3_driver_data
->gicd_base
, bitmap
, RWP_TRUE
);
218 /*******************************************************************************
219 * Functions to perform power operations on GIC Redistributor
220 ******************************************************************************/
221 void gicv3_rdistif_off(unsigned int proc_num
)
226 void gicv3_rdistif_on(unsigned int proc_num
)
231 /*******************************************************************************
232 * This function enables the GIC CPU interface of the calling CPU using only
233 * system register accesses.
234 ******************************************************************************/
235 void gicv3_cpuif_enable(unsigned int proc_num
)
238 unsigned int scr_el3
;
239 unsigned int icc_sre_el3
;
241 assert(gicv3_driver_data
!= NULL
);
242 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
243 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
246 /* Mark the connected core as awake */
247 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
248 gicv3_rdistif_mark_core_awake(gicr_base
);
250 /* Disable the legacy interrupt bypass */
251 icc_sre_el3
= ICC_SRE_DIB_BIT
| ICC_SRE_DFB_BIT
;
254 * Enable system register access for EL3 and allow lower exception
255 * levels to configure the same for themselves. If the legacy mode is
256 * not supported, the SRE bit is RAO/WI
258 icc_sre_el3
|= (ICC_SRE_EN_BIT
| ICC_SRE_SRE_BIT
);
259 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3
);
261 scr_el3
= (uint32_t) read_scr_el3();
264 * Switch to NS state to write Non secure ICC_SRE_EL1 and
265 * ICC_SRE_EL2 registers.
267 write_scr_el3(scr_el3
| SCR_NS_BIT
);
270 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3
);
271 write_icc_sre_el1(ICC_SRE_SRE_BIT
);
274 /* Switch to secure state. */
275 write_scr_el3(scr_el3
& (~SCR_NS_BIT
));
278 /* Write the secure ICC_SRE_EL1 register */
279 write_icc_sre_el1(ICC_SRE_SRE_BIT
);
282 /* Program the idle priority in the PMR */
283 write_icc_pmr_el1(GIC_PRI_MASK
);
285 /* Enable Group0 interrupts */
286 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT
);
288 /* Enable Group1 Secure interrupts */
289 write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
290 IGRPEN1_EL3_ENABLE_G1S_BIT
);
294 /*******************************************************************************
295 * This function disables the GIC CPU interface of the calling CPU using
296 * only system register accesses.
297 ******************************************************************************/
298 void gicv3_cpuif_disable(unsigned int proc_num
)
302 assert(gicv3_driver_data
!= NULL
);
303 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
304 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
308 /* Disable legacy interrupt bypass */
309 write_icc_sre_el3(read_icc_sre_el3() |
310 (ICC_SRE_DIB_BIT
| ICC_SRE_DFB_BIT
));
312 /* Disable Group0 interrupts */
313 write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
314 ~IGRPEN1_EL1_ENABLE_G0_BIT
);
316 /* Disable Group1 Secure and Non-Secure interrupts */
317 write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
318 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT
|
319 IGRPEN1_EL3_ENABLE_G1S_BIT
));
321 /* Synchronise accesses to group enable registers */
324 /* Mark the connected core as asleep */
325 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
326 assert(gicr_base
!= 0U);
327 gicv3_rdistif_mark_core_asleep(gicr_base
);
330 /*******************************************************************************
331 * This function returns the id of the highest priority pending interrupt at
332 * the GIC cpu interface.
333 ******************************************************************************/
334 unsigned int gicv3_get_pending_interrupt_id(void)
339 id
= (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK
;
342 * If the ID is special identifier corresponding to G1S or G1NS
343 * interrupt, then read the highest pending group 1 interrupt.
345 if ((id
== PENDING_G1S_INTID
) || (id
== PENDING_G1NS_INTID
))
346 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK
;
351 /*******************************************************************************
352 * This function returns the type of the highest priority pending interrupt at
353 * the GIC cpu interface. The return values can be one of the following :
354 * PENDING_G1S_INTID : The interrupt type is secure Group 1.
355 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
356 * 0 - 1019 : The interrupt type is secure Group 0.
357 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
358 * sufficient priority to be signaled
359 ******************************************************************************/
360 unsigned int gicv3_get_pending_interrupt_type(void)
363 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK
;
366 /*******************************************************************************
367 * This function returns the type of the interrupt id depending upon the group
368 * this interrupt has been configured under by the interrupt controller i.e.
369 * group0 or group1 Secure / Non Secure. The return value can be one of the
371 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
372 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
373 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
375 ******************************************************************************/
376 unsigned int gicv3_get_interrupt_type(unsigned int id
,
377 unsigned int proc_num
)
379 unsigned int igroup
, grpmodr
;
383 assert(gicv3_driver_data
!= NULL
);
385 /* Ensure the parameters are valid */
386 assert((id
< PENDING_G1S_INTID
) || (id
>= MIN_LPI_ID
));
387 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
389 /* All LPI interrupts are Group 1 non secure */
390 if (id
>= MIN_LPI_ID
)
391 return INTR_GROUP1NS
;
393 if (id
< MIN_SPI_ID
) {
394 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
395 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
396 igroup
= gicr_get_igroupr0(gicr_base
, id
);
397 grpmodr
= gicr_get_igrpmodr0(gicr_base
, id
);
399 assert(gicv3_driver_data
->gicd_base
!= 0U);
400 igroup
= gicd_get_igroupr(gicv3_driver_data
->gicd_base
, id
);
401 grpmodr
= gicd_get_igrpmodr(gicv3_driver_data
->gicd_base
, id
);
405 * If the IGROUP bit is set, then it is a Group 1 Non secure
409 return INTR_GROUP1NS
;
411 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
415 /* Else it is a Group 0 Secure interrupt */
419 /*****************************************************************************
420 * Function to save and disable the GIC ITS register context. The power
421 * management of GIC ITS is implementation-defined and this function doesn't
422 * save any memory structures required to support ITS. As the sequence to save
423 * this state is implementation defined, it should be executed in platform
424 * specific code. Calling this function alone and then powering down the GIC and
425 * ITS without implementing the aforementioned platform specific code will
426 * corrupt the ITS state.
428 * This function must be invoked after the GIC CPU interface is disabled.
429 *****************************************************************************/
430 void gicv3_its_save_disable(uintptr_t gits_base
, gicv3_its_ctx_t
* const its_ctx
)
434 assert(gicv3_driver_data
!= NULL
);
436 assert(its_ctx
!= NULL
);
437 assert(gits_base
!= 0U);
439 its_ctx
->gits_ctlr
= gits_read_ctlr(gits_base
);
441 /* Disable the ITS */
442 gits_write_ctlr(gits_base
, its_ctx
->gits_ctlr
&
443 (~GITS_CTLR_ENABLED_BIT
));
445 /* Wait for quiescent state */
446 gits_wait_for_quiescent_bit(gits_base
);
448 its_ctx
->gits_cbaser
= gits_read_cbaser(gits_base
);
449 its_ctx
->gits_cwriter
= gits_read_cwriter(gits_base
);
451 for (i
= 0; i
< ARRAY_SIZE(its_ctx
->gits_baser
); i
++)
452 its_ctx
->gits_baser
[i
] = gits_read_baser(gits_base
, i
);
455 /*****************************************************************************
456 * Function to restore the GIC ITS register context. The power
457 * management of GIC ITS is implementation defined and this function doesn't
458 * restore any memory structures required to support ITS. The assumption is
459 * that these structures are in memory and are retained during system suspend.
461 * This must be invoked before the GIC CPU interface is enabled.
462 *****************************************************************************/
463 void gicv3_its_restore(uintptr_t gits_base
, const gicv3_its_ctx_t
* const its_ctx
)
467 assert(gicv3_driver_data
!= NULL
);
469 assert(its_ctx
!= NULL
);
470 assert(gits_base
!= 0U);
472 /* Assert that the GITS is disabled and quiescent */
473 assert((gits_read_ctlr(gits_base
) & GITS_CTLR_ENABLED_BIT
) == 0U);
474 assert((gits_read_ctlr(gits_base
) & GITS_CTLR_QUIESCENT_BIT
) != 0U);
476 gits_write_cbaser(gits_base
, its_ctx
->gits_cbaser
);
477 gits_write_cwriter(gits_base
, its_ctx
->gits_cwriter
);
479 for (i
= 0; i
< ARRAY_SIZE(its_ctx
->gits_baser
); i
++)
480 gits_write_baser(gits_base
, i
, its_ctx
->gits_baser
[i
]);
482 /* Restore the ITS CTLR but leave the ITS disabled */
483 gits_write_ctlr(gits_base
, its_ctx
->gits_ctlr
&
484 (~GITS_CTLR_ENABLED_BIT
));
487 /*****************************************************************************
488 * Function to save the GIC Redistributor register context. This function
489 * must be invoked after CPU interface disable and prior to Distributor save.
490 *****************************************************************************/
491 void gicv3_rdistif_save(unsigned int proc_num
, gicv3_redist_ctx_t
* const rdist_ctx
)
496 assert(gicv3_driver_data
!= NULL
);
497 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
498 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
500 assert(rdist_ctx
!= NULL
);
502 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
505 * Wait for any write to GICR_CTLR to complete before trying to save any
508 gicr_wait_for_pending_write(gicr_base
);
510 rdist_ctx
->gicr_ctlr
= gicr_read_ctlr(gicr_base
);
512 rdist_ctx
->gicr_propbaser
= gicr_read_propbaser(gicr_base
);
513 rdist_ctx
->gicr_pendbaser
= gicr_read_pendbaser(gicr_base
);
515 rdist_ctx
->gicr_igroupr0
= gicr_read_igroupr0(gicr_base
);
516 rdist_ctx
->gicr_isenabler0
= gicr_read_isenabler0(gicr_base
);
517 rdist_ctx
->gicr_ispendr0
= gicr_read_ispendr0(gicr_base
);
518 rdist_ctx
->gicr_isactiver0
= gicr_read_isactiver0(gicr_base
);
519 rdist_ctx
->gicr_icfgr0
= gicr_read_icfgr0(gicr_base
);
520 rdist_ctx
->gicr_icfgr1
= gicr_read_icfgr1(gicr_base
);
521 rdist_ctx
->gicr_igrpmodr0
= gicr_read_igrpmodr0(gicr_base
);
522 rdist_ctx
->gicr_nsacr
= gicr_read_nsacr(gicr_base
);
523 for (int_id
= MIN_SGI_ID
; int_id
< TOTAL_PCPU_INTR_NUM
;
524 int_id
+= (1U << IPRIORITYR_SHIFT
)) {
525 rdist_ctx
->gicr_ipriorityr
[(int_id
- MIN_SGI_ID
) >> IPRIORITYR_SHIFT
] =
526 gicr_read_ipriorityr(gicr_base
, int_id
);
531 * Call the pre-save hook that implements the IMP DEF sequence that may
532 * be required on some GIC implementations. As this may need to access
533 * the Redistributor registers, we pass it proc_num.
535 gicv3_distif_pre_save(proc_num
);
538 /*****************************************************************************
539 * Function to restore the GIC Redistributor register context. We disable
540 * LPI and per-cpu interrupts before we start restore of the Redistributor.
541 * This function must be invoked after Distributor restore but prior to
542 * CPU interface enable. The pending and active interrupts are restored
543 * after the interrupts are fully configured and enabled.
544 *****************************************************************************/
545 void gicv3_rdistif_init_restore(unsigned int proc_num
,
546 const gicv3_redist_ctx_t
* const rdist_ctx
)
551 assert(gicv3_driver_data
!= NULL
);
552 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
553 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
555 assert(rdist_ctx
!= NULL
);
557 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
559 /* Power on redistributor */
560 gicv3_rdistif_on(proc_num
);
563 * Call the post-restore hook that implements the IMP DEF sequence that
564 * may be required on some GIC implementations. As this may need to
565 * access the Redistributor registers, we pass it proc_num.
567 gicv3_distif_post_restore(proc_num
);
570 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
571 * more scalable approach as it avoids clearing the enable bits in the
574 gicr_write_icenabler0(gicr_base
, ~0U);
575 /* Wait for pending writes to GICR_ICENABLER */
576 gicr_wait_for_pending_write(gicr_base
);
579 * Disable the LPIs to avoid unpredictable behavior when writing to
580 * GICR_PROPBASER and GICR_PENDBASER.
582 gicr_write_ctlr(gicr_base
,
583 rdist_ctx
->gicr_ctlr
& ~(GICR_CTLR_EN_LPIS_BIT
));
585 /* Restore registers' content */
586 gicr_write_propbaser(gicr_base
, rdist_ctx
->gicr_propbaser
);
587 gicr_write_pendbaser(gicr_base
, rdist_ctx
->gicr_pendbaser
);
589 gicr_write_igroupr0(gicr_base
, rdist_ctx
->gicr_igroupr0
);
591 for (int_id
= MIN_SGI_ID
; int_id
< TOTAL_PCPU_INTR_NUM
;
592 int_id
+= (1U << IPRIORITYR_SHIFT
)) {
593 gicr_write_ipriorityr(gicr_base
, int_id
,
594 rdist_ctx
->gicr_ipriorityr
[
595 (int_id
- MIN_SGI_ID
) >> IPRIORITYR_SHIFT
]);
598 gicr_write_icfgr0(gicr_base
, rdist_ctx
->gicr_icfgr0
);
599 gicr_write_icfgr1(gicr_base
, rdist_ctx
->gicr_icfgr1
);
600 gicr_write_igrpmodr0(gicr_base
, rdist_ctx
->gicr_igrpmodr0
);
601 gicr_write_nsacr(gicr_base
, rdist_ctx
->gicr_nsacr
);
603 /* Restore after group and priorities are set */
604 gicr_write_ispendr0(gicr_base
, rdist_ctx
->gicr_ispendr0
);
605 gicr_write_isactiver0(gicr_base
, rdist_ctx
->gicr_isactiver0
);
608 * Wait for all writes to the Distributor to complete before enabling
611 gicr_wait_for_upstream_pending_write(gicr_base
);
612 gicr_write_isenabler0(gicr_base
, rdist_ctx
->gicr_isenabler0
);
615 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case
616 * the first write to GICR_CTLR was still in flight (this write only
617 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this
620 gicr_write_ctlr(gicr_base
, rdist_ctx
->gicr_ctlr
);
621 gicr_wait_for_pending_write(gicr_base
);
624 /*****************************************************************************
625 * Function to save the GIC Distributor register context. This function
626 * must be invoked after CPU interface disable and Redistributor save.
627 *****************************************************************************/
628 void gicv3_distif_save(gicv3_dist_ctx_t
* const dist_ctx
)
630 unsigned int num_ints
;
632 assert(gicv3_driver_data
!= NULL
);
633 assert(gicv3_driver_data
->gicd_base
!= 0U);
635 assert(dist_ctx
!= NULL
);
637 uintptr_t gicd_base
= gicv3_driver_data
->gicd_base
;
639 num_ints
= gicd_read_typer(gicd_base
);
640 num_ints
&= TYPER_IT_LINES_NO_MASK
;
641 num_ints
= (num_ints
+ 1U) << 5;
643 assert(num_ints
<= (MAX_SPI_ID
+ 1U));
645 /* Wait for pending write to complete */
646 gicd_wait_for_pending_write(gicd_base
);
648 /* Save the GICD_CTLR */
649 dist_ctx
->gicd_ctlr
= gicd_read_ctlr(gicd_base
);
651 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */
652 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, igroupr
, IGROUPR
);
654 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */
655 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, isenabler
, ISENABLER
);
657 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */
658 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, ispendr
, ISPENDR
);
660 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */
661 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, isactiver
, ISACTIVER
);
663 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */
664 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, ipriorityr
, IPRIORITYR
);
666 /* Save GICD_ICFGR for INTIDs 32 - 1020 */
667 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, icfgr
, ICFGR
);
669 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */
670 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, igrpmodr
, IGRPMODR
);
672 /* Save GICD_NSACR for INTIDs 32 - 1020 */
673 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, nsacr
, NSACR
);
675 /* Save GICD_IROUTER for INTIDs 32 - 1024 */
676 SAVE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, irouter
, IROUTER
);
679 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when
680 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3
685 /*****************************************************************************
686 * Function to restore the GIC Distributor register context. We disable G0, G1S
687 * and G1NS interrupt groups before we start restore of the Distributor. This
688 * function must be invoked prior to Redistributor restore and CPU interface
689 * enable. The pending and active interrupts are restored after the interrupts
690 * are fully configured and enabled.
691 *****************************************************************************/
692 void gicv3_distif_init_restore(const gicv3_dist_ctx_t
* const dist_ctx
)
694 unsigned int num_ints
= 0U;
696 assert(gicv3_driver_data
!= NULL
);
697 assert(gicv3_driver_data
->gicd_base
!= 0U);
699 assert(dist_ctx
!= NULL
);
701 uintptr_t gicd_base
= gicv3_driver_data
->gicd_base
;
704 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
705 * the ARE_S bit. The Distributor might generate a system error
708 gicd_clr_ctlr(gicd_base
,
710 CTLR_ENABLE_G1S_BIT
|
711 CTLR_ENABLE_G1NS_BIT
,
714 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
715 gicd_set_ctlr(gicd_base
, CTLR_ARE_S_BIT
| CTLR_ARE_NS_BIT
, RWP_TRUE
);
717 num_ints
= gicd_read_typer(gicd_base
);
718 num_ints
&= TYPER_IT_LINES_NO_MASK
;
719 num_ints
= (num_ints
+ 1U) << 5;
721 assert(num_ints
<= (MAX_SPI_ID
+ 1U));
723 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */
724 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, igroupr
, IGROUPR
);
726 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */
727 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, ipriorityr
, IPRIORITYR
);
729 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */
730 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, icfgr
, ICFGR
);
732 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */
733 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, igrpmodr
, IGRPMODR
);
735 /* Restore GICD_NSACR for INTIDs 32 - 1020 */
736 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, nsacr
, NSACR
);
738 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */
739 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, irouter
, IROUTER
);
742 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are
746 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */
747 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, isenabler
, ISENABLER
);
749 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */
750 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, ispendr
, ISPENDR
);
752 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */
753 RESTORE_GICD_REGS(gicd_base
, dist_ctx
, num_ints
, isactiver
, ISACTIVER
);
755 /* Restore the GICD_CTLR */
756 gicd_write_ctlr(gicd_base
, dist_ctx
->gicd_ctlr
);
757 gicd_wait_for_pending_write(gicd_base
);
761 /*******************************************************************************
762 * This function gets the priority of the interrupt the processor is currently
764 ******************************************************************************/
765 unsigned int gicv3_get_running_priority(void)
767 return (unsigned int)read_icc_rpr_el1();
770 /*******************************************************************************
771 * This function checks if the interrupt identified by id is active (whether the
772 * state is either active, or active and pending). The proc_num is used if the
773 * interrupt is SGI or PPI and programs the corresponding Redistributor
775 ******************************************************************************/
776 unsigned int gicv3_get_interrupt_active(unsigned int id
, unsigned int proc_num
)
780 assert(gicv3_driver_data
!= NULL
);
781 assert(gicv3_driver_data
->gicd_base
!= 0U);
782 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
783 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
784 assert(id
<= MAX_SPI_ID
);
786 if (id
< MIN_SPI_ID
) {
787 /* For SGIs and PPIs */
788 value
= gicr_get_isactiver0(
789 gicv3_driver_data
->rdistif_base_addrs
[proc_num
], id
);
791 value
= gicd_get_isactiver(gicv3_driver_data
->gicd_base
, id
);
797 /*******************************************************************************
798 * This function enables the interrupt identified by id. The proc_num
799 * is used if the interrupt is SGI or PPI, and programs the corresponding
800 * Redistributor interface.
801 ******************************************************************************/
802 void gicv3_enable_interrupt(unsigned int id
, unsigned int proc_num
)
804 assert(gicv3_driver_data
!= NULL
);
805 assert(gicv3_driver_data
->gicd_base
!= 0U);
806 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
807 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
808 assert(id
<= MAX_SPI_ID
);
811 * Ensure that any shared variable updates depending on out of band
812 * interrupt trigger are observed before enabling interrupt.
815 if (id
< MIN_SPI_ID
) {
816 /* For SGIs and PPIs */
818 gicv3_driver_data
->rdistif_base_addrs
[proc_num
],
821 gicd_set_isenabler(gicv3_driver_data
->gicd_base
, id
);
825 /*******************************************************************************
826 * This function disables the interrupt identified by id. The proc_num
827 * is used if the interrupt is SGI or PPI, and programs the corresponding
828 * Redistributor interface.
829 ******************************************************************************/
830 void gicv3_disable_interrupt(unsigned int id
, unsigned int proc_num
)
832 assert(gicv3_driver_data
!= NULL
);
833 assert(gicv3_driver_data
->gicd_base
!= 0U);
834 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
835 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
836 assert(id
<= MAX_SPI_ID
);
839 * Disable interrupt, and ensure that any shared variable updates
840 * depending on out of band interrupt trigger are observed afterwards.
842 if (id
< MIN_SPI_ID
) {
843 /* For SGIs and PPIs */
845 gicv3_driver_data
->rdistif_base_addrs
[proc_num
],
848 /* Write to clear enable requires waiting for pending writes */
849 gicr_wait_for_pending_write(
850 gicv3_driver_data
->rdistif_base_addrs
[proc_num
]);
852 gicd_set_icenabler(gicv3_driver_data
->gicd_base
, id
);
854 /* Write to clear enable requires waiting for pending writes */
855 gicd_wait_for_pending_write(gicv3_driver_data
->gicd_base
);
861 /*******************************************************************************
862 * This function sets the interrupt priority as supplied for the given interrupt
864 ******************************************************************************/
865 void gicv3_set_interrupt_priority(unsigned int id
, unsigned int proc_num
,
866 unsigned int priority
)
870 assert(gicv3_driver_data
!= NULL
);
871 assert(gicv3_driver_data
->gicd_base
!= 0U);
872 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
873 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
874 assert(id
<= MAX_SPI_ID
);
876 if (id
< MIN_SPI_ID
) {
877 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
878 gicr_set_ipriorityr(gicr_base
, id
, priority
);
880 gicd_set_ipriorityr(gicv3_driver_data
->gicd_base
, id
, priority
);
884 /*******************************************************************************
885 * This function assigns group for the interrupt identified by id. The proc_num
886 * is used if the interrupt is SGI or PPI, and programs the corresponding
887 * Redistributor interface. The group can be any of GICV3_INTR_GROUP*
888 ******************************************************************************/
889 void gicv3_set_interrupt_type(unsigned int id
, unsigned int proc_num
,
892 bool igroup
= false, grpmod
= false;
895 assert(gicv3_driver_data
!= NULL
);
896 assert(gicv3_driver_data
->gicd_base
!= 0U);
897 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
898 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
918 if (id
< MIN_SPI_ID
) {
919 gicr_base
= gicv3_driver_data
->rdistif_base_addrs
[proc_num
];
921 gicr_set_igroupr0(gicr_base
, id
);
923 gicr_clr_igroupr0(gicr_base
, id
);
926 gicr_set_igrpmodr0(gicr_base
, id
);
928 gicr_clr_igrpmodr0(gicr_base
, id
);
930 /* Serialize read-modify-write to Distributor registers */
931 spin_lock(&gic_lock
);
933 gicd_set_igroupr(gicv3_driver_data
->gicd_base
, id
);
935 gicd_clr_igroupr(gicv3_driver_data
->gicd_base
, id
);
938 gicd_set_igrpmodr(gicv3_driver_data
->gicd_base
, id
);
940 gicd_clr_igrpmodr(gicv3_driver_data
->gicd_base
, id
);
941 spin_unlock(&gic_lock
);
945 /*******************************************************************************
946 * This function raises the specified Secure Group 0 SGI.
948 * The target parameter must be a valid MPIDR in the system.
949 ******************************************************************************/
950 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num
, u_register_t target
)
952 unsigned int tgt
, aff3
, aff2
, aff1
, aff0
;
955 /* Verify interrupt number is in the SGI range */
956 assert((sgi_num
>= MIN_SGI_ID
) && (sgi_num
< MIN_PPI_ID
));
958 /* Extract affinity fields from target */
959 aff0
= MPIDR_AFFLVL0_VAL(target
);
960 aff1
= MPIDR_AFFLVL1_VAL(target
);
961 aff2
= MPIDR_AFFLVL2_VAL(target
);
962 aff3
= MPIDR_AFFLVL3_VAL(target
);
965 * Make target list from affinity 0, and ensure GICv3 SGI can target
968 assert(aff0
< GICV3_MAX_SGI_TARGETS
);
971 /* Raise SGI to PE specified by its affinity */
972 sgi_val
= GICV3_SGIR_VALUE(aff3
, aff2
, aff1
, sgi_num
, SGIR_IRM_TO_AFF
,
976 * Ensure that any shared variable updates depending on out of band
977 * interrupt trigger are observed before raising SGI.
980 write_icc_sgi0r_el1(sgi_val
);
984 /*******************************************************************************
985 * This function sets the interrupt routing for the given SPI interrupt id.
986 * The interrupt routing is specified in routing mode and mpidr.
988 * The routing mode can be either of:
992 * The mpidr is the affinity of the PE to which the interrupt will be routed,
993 * and is ignored for routing mode GICV3_IRM_ANY.
994 ******************************************************************************/
995 void gicv3_set_spi_routing(unsigned int id
, unsigned int irm
, u_register_t mpidr
)
997 unsigned long long aff
;
1000 assert(gicv3_driver_data
!= NULL
);
1001 assert(gicv3_driver_data
->gicd_base
!= 0U);
1003 assert((irm
== GICV3_IRM_ANY
) || (irm
== GICV3_IRM_PE
));
1004 assert((id
>= MIN_SPI_ID
) && (id
<= MAX_SPI_ID
));
1006 aff
= gicd_irouter_val_from_mpidr(mpidr
, irm
);
1007 gicd_write_irouter(gicv3_driver_data
->gicd_base
, id
, aff
);
1010 * In implementations that do not require 1 of N distribution of SPIs,
1011 * IRM might be RAZ/WI. Read back and verify IRM bit.
1013 if (irm
== GICV3_IRM_ANY
) {
1014 router
= gicd_read_irouter(gicv3_driver_data
->gicd_base
, id
);
1015 if (((router
>> IROUTER_IRM_SHIFT
) & IROUTER_IRM_MASK
) == 0U) {
1016 ERROR("GICv3 implementation doesn't support routing ANY\n");
1022 /*******************************************************************************
1023 * This function clears the pending status of an interrupt identified by id.
1024 * The proc_num is used if the interrupt is SGI or PPI, and programs the
1025 * corresponding Redistributor interface.
1026 ******************************************************************************/
1027 void gicv3_clear_interrupt_pending(unsigned int id
, unsigned int proc_num
)
1029 assert(gicv3_driver_data
!= NULL
);
1030 assert(gicv3_driver_data
->gicd_base
!= 0U);
1031 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
1032 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
1035 * Clear pending interrupt, and ensure that any shared variable updates
1036 * depending on out of band interrupt trigger are observed afterwards.
1038 if (id
< MIN_SPI_ID
) {
1039 /* For SGIs and PPIs */
1040 gicr_set_icpendr0(gicv3_driver_data
->rdistif_base_addrs
[proc_num
],
1043 gicd_set_icpendr(gicv3_driver_data
->gicd_base
, id
);
1048 /*******************************************************************************
1049 * This function sets the pending status of an interrupt identified by id.
1050 * The proc_num is used if the interrupt is SGI or PPI and programs the
1051 * corresponding Redistributor interface.
1052 ******************************************************************************/
1053 void gicv3_set_interrupt_pending(unsigned int id
, unsigned int proc_num
)
1055 assert(gicv3_driver_data
!= NULL
);
1056 assert(gicv3_driver_data
->gicd_base
!= 0U);
1057 assert(proc_num
< gicv3_driver_data
->rdistif_num
);
1058 assert(gicv3_driver_data
->rdistif_base_addrs
!= NULL
);
1061 * Ensure that any shared variable updates depending on out of band
1062 * interrupt trigger are observed before setting interrupt pending.
1065 if (id
< MIN_SPI_ID
) {
1066 /* For SGIs and PPIs */
1067 gicr_set_ispendr0(gicv3_driver_data
->rdistif_base_addrs
[proc_num
],
1070 gicd_set_ispendr(gicv3_driver_data
->gicd_base
, id
);
1074 /*******************************************************************************
1075 * This function sets the PMR register with the supplied value. Returns the
1077 ******************************************************************************/
1078 unsigned int gicv3_set_pmr(unsigned int mask
)
1080 unsigned int old_mask
;
1082 old_mask
= (uint32_t) read_icc_pmr_el1();
1085 * Order memory updates w.r.t. PMR write, and ensure they're visible
1086 * before potential out of band interrupt trigger because of PMR update.
1087 * PMR system register writes are self-synchronizing, so no ISB required
1091 write_icc_pmr_el1(mask
);
1096 /*******************************************************************************
1097 * This function delegates the responsibility of discovering the corresponding
1098 * Redistributor frames to each CPU itself. It is a modified version of
1099 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
1100 * unlike the previous way in which only the Primary CPU did the discovery of
1101 * all the Redistributor frames for every CPU. It also handles the scenario in
1102 * which the frames of various CPUs are not contiguous in physical memory.
1103 ******************************************************************************/
1104 int gicv3_rdistif_probe(const uintptr_t gicr_frame
)
1107 unsigned int proc_num
, proc_self
;
1109 uintptr_t rdistif_base
;
1110 bool gicr_frame_found
= false;
1112 assert(gicv3_driver_data
->gicr_base
== 0U);
1114 /* Ensure this function is called with Data Cache enabled */
1116 assert((read_sctlr() & SCTLR_C_BIT
) != 0U);
1118 assert((read_sctlr_el3() & SCTLR_C_BIT
) != 0U);
1119 #endif /* !__aarch64__ */
1121 proc_self
= gicv3_driver_data
->mpidr_to_core_pos(read_mpidr_el1());
1122 rdistif_base
= gicr_frame
;
1124 typer_val
= gicr_read_typer(rdistif_base
);
1125 if (gicv3_driver_data
->mpidr_to_core_pos
!= NULL
) {
1126 mpidr
= mpidr_from_gicr_typer(typer_val
);
1127 proc_num
= gicv3_driver_data
->mpidr_to_core_pos(mpidr
);
1129 proc_num
= (unsigned int)(typer_val
>> TYPER_PROC_NUM_SHIFT
) &
1130 TYPER_PROC_NUM_MASK
;
1132 if (proc_num
== proc_self
) {
1133 /* The base address doesn't need to be initialized on
1136 if (gicv3_driver_data
->rdistif_base_addrs
[proc_num
] != 0U)
1138 gicv3_driver_data
->rdistif_base_addrs
[proc_num
] =
1140 gicr_frame_found
= true;
1143 rdistif_base
+= (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT
);
1144 } while ((typer_val
& TYPER_LAST_BIT
) == 0U);
1146 if (!gicr_frame_found
)
1150 * Flush the driver data to ensure coherency. This is
1151 * not required if platform has HW_ASSISTED_COHERENCY
1154 #if !HW_ASSISTED_COHERENCY
1156 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
1158 flush_dcache_range((uintptr_t)&(gicv3_driver_data
->rdistif_base_addrs
[proc_num
]),
1159 sizeof(*(gicv3_driver_data
->rdistif_base_addrs
)));
1161 return 0; /* Found matching GICR frame */