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Merge "GICv3 driver: Fix support for full SPI range" into integration
[project/bcm63xx/atf.git] / drivers / arm / gic / v3 / gicv3_main.c
1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <arch.h>
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <common/interrupt_props.h>
13 #include <drivers/arm/gicv3.h>
14 #include <lib/spinlock.h>
15
16 #include "gicv3_private.h"
17
18 const gicv3_driver_data_t *gicv3_driver_data;
19
20 /*
21 * Spinlock to guard registers needing read-modify-write. APIs protected by this
22 * spinlock are used either at boot time (when only a single CPU is active), or
23 * when the system is fully coherent.
24 */
25 static spinlock_t gic_lock;
26
27 /*
28 * Redistributor power operations are weakly bound so that they can be
29 * overridden
30 */
31 #pragma weak gicv3_rdistif_off
32 #pragma weak gicv3_rdistif_on
33
34
35 /* Helper macros to save and restore GICD registers to and from the context */
36 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \
37 do { \
38 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
39 int_id += (1U << REG##_SHIFT)) { \
40 gicd_write_##reg(base, int_id, \
41 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \
42 } \
43 } while (false)
44
45 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \
46 do { \
47 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num); \
48 int_id += (1U << REG##_SHIFT)) { \
49 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\
50 gicd_read_##reg(base, int_id); \
51 } \
52 } while (false)
53
54
55 /*******************************************************************************
56 * This function initialises the ARM GICv3 driver in EL3 with provided platform
57 * inputs.
58 ******************************************************************************/
59 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
60 {
61 unsigned int gic_version;
62 unsigned int gicv2_compat;
63
64 assert(plat_driver_data != NULL);
65 assert(plat_driver_data->gicd_base != 0U);
66 assert(plat_driver_data->rdistif_num != 0U);
67 assert(plat_driver_data->rdistif_base_addrs != NULL);
68
69 assert(IS_IN_EL3());
70
71 assert((plat_driver_data->interrupt_props_num != 0U) ?
72 (plat_driver_data->interrupt_props != NULL) : 1);
73
74 /* Check for system register support */
75 #ifndef __aarch64__
76 assert((read_id_pfr1() &
77 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
78 #else
79 assert((read_id_aa64pfr0_el1() &
80 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
81 #endif /* !__aarch64__ */
82
83 /* The GIC version should be 3.0 */
84 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
85 gic_version >>= PIDR2_ARCH_REV_SHIFT;
86 gic_version &= PIDR2_ARCH_REV_MASK;
87 assert(gic_version == ARCH_REV_GICV3);
88
89 /*
90 * Find out whether the GIC supports the GICv2 compatibility mode.
91 * The ARE_S bit resets to 0 if supported
92 */
93 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
94 gicv2_compat >>= CTLR_ARE_S_SHIFT;
95 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK;
96
97 if (plat_driver_data->gicr_base != 0U) {
98 /*
99 * Find the base address of each implemented Redistributor interface.
100 * The number of interfaces should be equal to the number of CPUs in the
101 * system. The memory for saving these addresses has to be allocated by
102 * the platform port
103 */
104 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
105 plat_driver_data->rdistif_num,
106 plat_driver_data->gicr_base,
107 plat_driver_data->mpidr_to_core_pos);
108 #if !HW_ASSISTED_COHERENCY
109 /*
110 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
111 */
112 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs),
113 plat_driver_data->rdistif_num *
114 sizeof(*(plat_driver_data->rdistif_base_addrs)));
115 #endif
116 }
117 gicv3_driver_data = plat_driver_data;
118
119 /*
120 * The GIC driver data is initialized by the primary CPU with caches
121 * enabled. When the secondary CPU boots up, it initializes the
122 * GICC/GICR interface with the caches disabled. Hence flush the
123 * driver data to ensure coherency. This is not required if the
124 * platform has HW_ASSISTED_COHERENCY enabled.
125 */
126 #if !HW_ASSISTED_COHERENCY
127 flush_dcache_range((uintptr_t)&gicv3_driver_data,
128 sizeof(gicv3_driver_data));
129 flush_dcache_range((uintptr_t)gicv3_driver_data,
130 sizeof(*gicv3_driver_data));
131 #endif
132
133 INFO("GICv3 with%s legacy support detected."
134 " ARM GICv3 driver initialized in EL3\n",
135 (gicv2_compat == 0U) ? "" : "out");
136
137 }
138
139 /*******************************************************************************
140 * This function initialises the GIC distributor interface based upon the data
141 * provided by the platform while initialising the driver.
142 ******************************************************************************/
143 void __init gicv3_distif_init(void)
144 {
145 unsigned int bitmap = 0;
146
147 assert(gicv3_driver_data != NULL);
148 assert(gicv3_driver_data->gicd_base != 0U);
149
150 assert(IS_IN_EL3());
151
152 /*
153 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
154 * the ARE_S bit. The Distributor might generate a system error
155 * otherwise.
156 */
157 gicd_clr_ctlr(gicv3_driver_data->gicd_base,
158 CTLR_ENABLE_G0_BIT |
159 CTLR_ENABLE_G1S_BIT |
160 CTLR_ENABLE_G1NS_BIT,
161 RWP_TRUE);
162
163 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
164 gicd_set_ctlr(gicv3_driver_data->gicd_base,
165 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
166
167 /* Set the default attribute of all SPIs */
168 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
169
170 bitmap = gicv3_secure_spis_config_props(
171 gicv3_driver_data->gicd_base,
172 gicv3_driver_data->interrupt_props,
173 gicv3_driver_data->interrupt_props_num);
174
175 /* Enable the secure SPIs now that they have been configured */
176 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
177 }
178
179 /*******************************************************************************
180 * This function initialises the GIC Redistributor interface of the calling CPU
181 * (identified by the 'proc_num' parameter) based upon the data provided by the
182 * platform while initialising the driver.
183 ******************************************************************************/
184 void gicv3_rdistif_init(unsigned int proc_num)
185 {
186 uintptr_t gicr_base;
187 unsigned int bitmap = 0U;
188 uint32_t ctlr;
189
190 assert(gicv3_driver_data != NULL);
191 assert(proc_num < gicv3_driver_data->rdistif_num);
192 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
193 assert(gicv3_driver_data->gicd_base != 0U);
194
195 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base);
196 assert((ctlr & CTLR_ARE_S_BIT) != 0U);
197
198 assert(IS_IN_EL3());
199
200 /* Power on redistributor */
201 gicv3_rdistif_on(proc_num);
202
203 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
204 assert(gicr_base != 0U);
205
206 /* Set the default attribute of all SGIs and PPIs */
207 gicv3_ppi_sgi_config_defaults(gicr_base);
208
209 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
210 gicv3_driver_data->interrupt_props,
211 gicv3_driver_data->interrupt_props_num);
212
213 /* Enable interrupt groups as required, if not already */
214 if ((ctlr & bitmap) != bitmap)
215 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
216 }
217
218 /*******************************************************************************
219 * Functions to perform power operations on GIC Redistributor
220 ******************************************************************************/
221 void gicv3_rdistif_off(unsigned int proc_num)
222 {
223 return;
224 }
225
226 void gicv3_rdistif_on(unsigned int proc_num)
227 {
228 return;
229 }
230
231 /*******************************************************************************
232 * This function enables the GIC CPU interface of the calling CPU using only
233 * system register accesses.
234 ******************************************************************************/
235 void gicv3_cpuif_enable(unsigned int proc_num)
236 {
237 uintptr_t gicr_base;
238 unsigned int scr_el3;
239 unsigned int icc_sre_el3;
240
241 assert(gicv3_driver_data != NULL);
242 assert(proc_num < gicv3_driver_data->rdistif_num);
243 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
244 assert(IS_IN_EL3());
245
246 /* Mark the connected core as awake */
247 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
248 gicv3_rdistif_mark_core_awake(gicr_base);
249
250 /* Disable the legacy interrupt bypass */
251 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT;
252
253 /*
254 * Enable system register access for EL3 and allow lower exception
255 * levels to configure the same for themselves. If the legacy mode is
256 * not supported, the SRE bit is RAO/WI
257 */
258 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
259 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
260
261 scr_el3 = (uint32_t) read_scr_el3();
262
263 /*
264 * Switch to NS state to write Non secure ICC_SRE_EL1 and
265 * ICC_SRE_EL2 registers.
266 */
267 write_scr_el3(scr_el3 | SCR_NS_BIT);
268 isb();
269
270 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3);
271 write_icc_sre_el1(ICC_SRE_SRE_BIT);
272 isb();
273
274 /* Switch to secure state. */
275 write_scr_el3(scr_el3 & (~SCR_NS_BIT));
276 isb();
277
278 /* Write the secure ICC_SRE_EL1 register */
279 write_icc_sre_el1(ICC_SRE_SRE_BIT);
280 isb();
281
282 /* Program the idle priority in the PMR */
283 write_icc_pmr_el1(GIC_PRI_MASK);
284
285 /* Enable Group0 interrupts */
286 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT);
287
288 /* Enable Group1 Secure interrupts */
289 write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
290 IGRPEN1_EL3_ENABLE_G1S_BIT);
291 isb();
292 }
293
294 /*******************************************************************************
295 * This function disables the GIC CPU interface of the calling CPU using
296 * only system register accesses.
297 ******************************************************************************/
298 void gicv3_cpuif_disable(unsigned int proc_num)
299 {
300 uintptr_t gicr_base;
301
302 assert(gicv3_driver_data != NULL);
303 assert(proc_num < gicv3_driver_data->rdistif_num);
304 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
305
306 assert(IS_IN_EL3());
307
308 /* Disable legacy interrupt bypass */
309 write_icc_sre_el3(read_icc_sre_el3() |
310 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT));
311
312 /* Disable Group0 interrupts */
313 write_icc_igrpen0_el1(read_icc_igrpen0_el1() &
314 ~IGRPEN1_EL1_ENABLE_G0_BIT);
315
316 /* Disable Group1 Secure and Non-Secure interrupts */
317 write_icc_igrpen1_el3(read_icc_igrpen1_el3() &
318 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT |
319 IGRPEN1_EL3_ENABLE_G1S_BIT));
320
321 /* Synchronise accesses to group enable registers */
322 isb();
323
324 /* Mark the connected core as asleep */
325 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
326 assert(gicr_base != 0U);
327 gicv3_rdistif_mark_core_asleep(gicr_base);
328 }
329
330 /*******************************************************************************
331 * This function returns the id of the highest priority pending interrupt at
332 * the GIC cpu interface.
333 ******************************************************************************/
334 unsigned int gicv3_get_pending_interrupt_id(void)
335 {
336 unsigned int id;
337
338 assert(IS_IN_EL3());
339 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
340
341 /*
342 * If the ID is special identifier corresponding to G1S or G1NS
343 * interrupt, then read the highest pending group 1 interrupt.
344 */
345 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID))
346 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
347
348 return id;
349 }
350
351 /*******************************************************************************
352 * This function returns the type of the highest priority pending interrupt at
353 * the GIC cpu interface. The return values can be one of the following :
354 * PENDING_G1S_INTID : The interrupt type is secure Group 1.
355 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1.
356 * 0 - 1019 : The interrupt type is secure Group 0.
357 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with
358 * sufficient priority to be signaled
359 ******************************************************************************/
360 unsigned int gicv3_get_pending_interrupt_type(void)
361 {
362 assert(IS_IN_EL3());
363 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK;
364 }
365
366 /*******************************************************************************
367 * This function returns the type of the interrupt id depending upon the group
368 * this interrupt has been configured under by the interrupt controller i.e.
369 * group0 or group1 Secure / Non Secure. The return value can be one of the
370 * following :
371 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
372 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
373 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
374 * interrupt.
375 ******************************************************************************/
376 unsigned int gicv3_get_interrupt_type(unsigned int id,
377 unsigned int proc_num)
378 {
379 unsigned int igroup, grpmodr;
380 uintptr_t gicr_base;
381
382 assert(IS_IN_EL3());
383 assert(gicv3_driver_data != NULL);
384
385 /* Ensure the parameters are valid */
386 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID));
387 assert(proc_num < gicv3_driver_data->rdistif_num);
388
389 /* All LPI interrupts are Group 1 non secure */
390 if (id >= MIN_LPI_ID)
391 return INTR_GROUP1NS;
392
393 if (id < MIN_SPI_ID) {
394 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
395 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
396 igroup = gicr_get_igroupr0(gicr_base, id);
397 grpmodr = gicr_get_igrpmodr0(gicr_base, id);
398 } else {
399 assert(gicv3_driver_data->gicd_base != 0U);
400 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id);
401 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id);
402 }
403
404 /*
405 * If the IGROUP bit is set, then it is a Group 1 Non secure
406 * interrupt
407 */
408 if (igroup != 0U)
409 return INTR_GROUP1NS;
410
411 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
412 if (grpmodr != 0U)
413 return INTR_GROUP1S;
414
415 /* Else it is a Group 0 Secure interrupt */
416 return INTR_GROUP0;
417 }
418
419 /*****************************************************************************
420 * Function to save and disable the GIC ITS register context. The power
421 * management of GIC ITS is implementation-defined and this function doesn't
422 * save any memory structures required to support ITS. As the sequence to save
423 * this state is implementation defined, it should be executed in platform
424 * specific code. Calling this function alone and then powering down the GIC and
425 * ITS without implementing the aforementioned platform specific code will
426 * corrupt the ITS state.
427 *
428 * This function must be invoked after the GIC CPU interface is disabled.
429 *****************************************************************************/
430 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx)
431 {
432 unsigned int i;
433
434 assert(gicv3_driver_data != NULL);
435 assert(IS_IN_EL3());
436 assert(its_ctx != NULL);
437 assert(gits_base != 0U);
438
439 its_ctx->gits_ctlr = gits_read_ctlr(gits_base);
440
441 /* Disable the ITS */
442 gits_write_ctlr(gits_base, its_ctx->gits_ctlr &
443 (~GITS_CTLR_ENABLED_BIT));
444
445 /* Wait for quiescent state */
446 gits_wait_for_quiescent_bit(gits_base);
447
448 its_ctx->gits_cbaser = gits_read_cbaser(gits_base);
449 its_ctx->gits_cwriter = gits_read_cwriter(gits_base);
450
451 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++)
452 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i);
453 }
454
455 /*****************************************************************************
456 * Function to restore the GIC ITS register context. The power
457 * management of GIC ITS is implementation defined and this function doesn't
458 * restore any memory structures required to support ITS. The assumption is
459 * that these structures are in memory and are retained during system suspend.
460 *
461 * This must be invoked before the GIC CPU interface is enabled.
462 *****************************************************************************/
463 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx)
464 {
465 unsigned int i;
466
467 assert(gicv3_driver_data != NULL);
468 assert(IS_IN_EL3());
469 assert(its_ctx != NULL);
470 assert(gits_base != 0U);
471
472 /* Assert that the GITS is disabled and quiescent */
473 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U);
474 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U);
475
476 gits_write_cbaser(gits_base, its_ctx->gits_cbaser);
477 gits_write_cwriter(gits_base, its_ctx->gits_cwriter);
478
479 for (i = 0; i < ARRAY_SIZE(its_ctx->gits_baser); i++)
480 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]);
481
482 /* Restore the ITS CTLR but leave the ITS disabled */
483 gits_write_ctlr(gits_base, its_ctx->gits_ctlr &
484 (~GITS_CTLR_ENABLED_BIT));
485 }
486
487 /*****************************************************************************
488 * Function to save the GIC Redistributor register context. This function
489 * must be invoked after CPU interface disable and prior to Distributor save.
490 *****************************************************************************/
491 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx)
492 {
493 uintptr_t gicr_base;
494 unsigned int int_id;
495
496 assert(gicv3_driver_data != NULL);
497 assert(proc_num < gicv3_driver_data->rdistif_num);
498 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
499 assert(IS_IN_EL3());
500 assert(rdist_ctx != NULL);
501
502 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
503
504 /*
505 * Wait for any write to GICR_CTLR to complete before trying to save any
506 * state.
507 */
508 gicr_wait_for_pending_write(gicr_base);
509
510 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base);
511
512 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base);
513 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base);
514
515 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base);
516 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base);
517 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base);
518 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base);
519 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base);
520 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base);
521 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base);
522 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base);
523 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
524 int_id += (1U << IPRIORITYR_SHIFT)) {
525 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] =
526 gicr_read_ipriorityr(gicr_base, int_id);
527 }
528
529
530 /*
531 * Call the pre-save hook that implements the IMP DEF sequence that may
532 * be required on some GIC implementations. As this may need to access
533 * the Redistributor registers, we pass it proc_num.
534 */
535 gicv3_distif_pre_save(proc_num);
536 }
537
538 /*****************************************************************************
539 * Function to restore the GIC Redistributor register context. We disable
540 * LPI and per-cpu interrupts before we start restore of the Redistributor.
541 * This function must be invoked after Distributor restore but prior to
542 * CPU interface enable. The pending and active interrupts are restored
543 * after the interrupts are fully configured and enabled.
544 *****************************************************************************/
545 void gicv3_rdistif_init_restore(unsigned int proc_num,
546 const gicv3_redist_ctx_t * const rdist_ctx)
547 {
548 uintptr_t gicr_base;
549 unsigned int int_id;
550
551 assert(gicv3_driver_data != NULL);
552 assert(proc_num < gicv3_driver_data->rdistif_num);
553 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
554 assert(IS_IN_EL3());
555 assert(rdist_ctx != NULL);
556
557 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
558
559 /* Power on redistributor */
560 gicv3_rdistif_on(proc_num);
561
562 /*
563 * Call the post-restore hook that implements the IMP DEF sequence that
564 * may be required on some GIC implementations. As this may need to
565 * access the Redistributor registers, we pass it proc_num.
566 */
567 gicv3_distif_post_restore(proc_num);
568
569 /*
570 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
571 * more scalable approach as it avoids clearing the enable bits in the
572 * GICD_CTLR
573 */
574 gicr_write_icenabler0(gicr_base, ~0U);
575 /* Wait for pending writes to GICR_ICENABLER */
576 gicr_wait_for_pending_write(gicr_base);
577
578 /*
579 * Disable the LPIs to avoid unpredictable behavior when writing to
580 * GICR_PROPBASER and GICR_PENDBASER.
581 */
582 gicr_write_ctlr(gicr_base,
583 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT));
584
585 /* Restore registers' content */
586 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser);
587 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser);
588
589 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0);
590
591 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM;
592 int_id += (1U << IPRIORITYR_SHIFT)) {
593 gicr_write_ipriorityr(gicr_base, int_id,
594 rdist_ctx->gicr_ipriorityr[
595 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]);
596 }
597
598 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0);
599 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1);
600 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0);
601 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr);
602
603 /* Restore after group and priorities are set */
604 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0);
605 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0);
606
607 /*
608 * Wait for all writes to the Distributor to complete before enabling
609 * the SGI and PPIs.
610 */
611 gicr_wait_for_upstream_pending_write(gicr_base);
612 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0);
613
614 /*
615 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case
616 * the first write to GICR_CTLR was still in flight (this write only
617 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this
618 * bit).
619 */
620 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr);
621 gicr_wait_for_pending_write(gicr_base);
622 }
623
624 /*****************************************************************************
625 * Function to save the GIC Distributor register context. This function
626 * must be invoked after CPU interface disable and Redistributor save.
627 *****************************************************************************/
628 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
629 {
630 unsigned int num_ints;
631
632 assert(gicv3_driver_data != NULL);
633 assert(gicv3_driver_data->gicd_base != 0U);
634 assert(IS_IN_EL3());
635 assert(dist_ctx != NULL);
636
637 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
638
639 num_ints = gicd_read_typer(gicd_base);
640 num_ints &= TYPER_IT_LINES_NO_MASK;
641 num_ints = (num_ints + 1U) << 5;
642
643 /* Filter out special INTIDs 1020-1023 */
644 if (num_ints > (MAX_SPI_ID + 1U))
645 num_ints = MAX_SPI_ID + 1U;
646
647 /* Wait for pending write to complete */
648 gicd_wait_for_pending_write(gicd_base);
649
650 /* Save the GICD_CTLR */
651 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
652
653 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */
654 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
655
656 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */
657 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
658
659 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */
660 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
661
662 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */
663 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
664
665 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */
666 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
667
668 /* Save GICD_ICFGR for INTIDs 32 - 1019 */
669 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
670
671 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */
672 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
673
674 /* Save GICD_NSACR for INTIDs 32 - 1019 */
675 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
676
677 /* Save GICD_IROUTER for INTIDs 32 - 1019 */
678 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
679
680 /*
681 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when
682 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3
683 * driver.
684 */
685 }
686
687 /*****************************************************************************
688 * Function to restore the GIC Distributor register context. We disable G0, G1S
689 * and G1NS interrupt groups before we start restore of the Distributor. This
690 * function must be invoked prior to Redistributor restore and CPU interface
691 * enable. The pending and active interrupts are restored after the interrupts
692 * are fully configured and enabled.
693 *****************************************************************************/
694 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
695 {
696 unsigned int num_ints = 0U;
697
698 assert(gicv3_driver_data != NULL);
699 assert(gicv3_driver_data->gicd_base != 0U);
700 assert(IS_IN_EL3());
701 assert(dist_ctx != NULL);
702
703 uintptr_t gicd_base = gicv3_driver_data->gicd_base;
704
705 /*
706 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring
707 * the ARE_S bit. The Distributor might generate a system error
708 * otherwise.
709 */
710 gicd_clr_ctlr(gicd_base,
711 CTLR_ENABLE_G0_BIT |
712 CTLR_ENABLE_G1S_BIT |
713 CTLR_ENABLE_G1NS_BIT,
714 RWP_TRUE);
715
716 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
717 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
718
719 num_ints = gicd_read_typer(gicd_base);
720 num_ints &= TYPER_IT_LINES_NO_MASK;
721 num_ints = (num_ints + 1U) << 5;
722
723 /* Filter out special INTIDs 1020-1023 */
724 if (num_ints > (MAX_SPI_ID + 1U))
725 num_ints = MAX_SPI_ID + 1U;
726
727 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
728 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
729
730 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */
731 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
732
733 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */
734 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
735
736 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */
737 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
738
739 /* Restore GICD_NSACR for INTIDs 32 - 1019 */
740 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
741
742 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */
743 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
744
745 /*
746 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are
747 * configured.
748 */
749
750 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */
751 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
752
753 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */
754 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
755
756 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */
757 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
758
759 /* Restore the GICD_CTLR */
760 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr);
761 gicd_wait_for_pending_write(gicd_base);
762
763 }
764
765 /*******************************************************************************
766 * This function gets the priority of the interrupt the processor is currently
767 * servicing.
768 ******************************************************************************/
769 unsigned int gicv3_get_running_priority(void)
770 {
771 return (unsigned int)read_icc_rpr_el1();
772 }
773
774 /*******************************************************************************
775 * This function checks if the interrupt identified by id is active (whether the
776 * state is either active, or active and pending). The proc_num is used if the
777 * interrupt is SGI or PPI and programs the corresponding Redistributor
778 * interface.
779 ******************************************************************************/
780 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num)
781 {
782 unsigned int value;
783
784 assert(gicv3_driver_data != NULL);
785 assert(gicv3_driver_data->gicd_base != 0U);
786 assert(proc_num < gicv3_driver_data->rdistif_num);
787 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
788 assert(id <= MAX_SPI_ID);
789
790 if (id < MIN_SPI_ID) {
791 /* For SGIs and PPIs */
792 value = gicr_get_isactiver0(
793 gicv3_driver_data->rdistif_base_addrs[proc_num], id);
794 } else {
795 value = gicd_get_isactiver(gicv3_driver_data->gicd_base, id);
796 }
797
798 return value;
799 }
800
801 /*******************************************************************************
802 * This function enables the interrupt identified by id. The proc_num
803 * is used if the interrupt is SGI or PPI, and programs the corresponding
804 * Redistributor interface.
805 ******************************************************************************/
806 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num)
807 {
808 assert(gicv3_driver_data != NULL);
809 assert(gicv3_driver_data->gicd_base != 0U);
810 assert(proc_num < gicv3_driver_data->rdistif_num);
811 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
812 assert(id <= MAX_SPI_ID);
813
814 /*
815 * Ensure that any shared variable updates depending on out of band
816 * interrupt trigger are observed before enabling interrupt.
817 */
818 dsbishst();
819 if (id < MIN_SPI_ID) {
820 /* For SGIs and PPIs */
821 gicr_set_isenabler0(
822 gicv3_driver_data->rdistif_base_addrs[proc_num],
823 id);
824 } else {
825 gicd_set_isenabler(gicv3_driver_data->gicd_base, id);
826 }
827 }
828
829 /*******************************************************************************
830 * This function disables the interrupt identified by id. The proc_num
831 * is used if the interrupt is SGI or PPI, and programs the corresponding
832 * Redistributor interface.
833 ******************************************************************************/
834 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num)
835 {
836 assert(gicv3_driver_data != NULL);
837 assert(gicv3_driver_data->gicd_base != 0U);
838 assert(proc_num < gicv3_driver_data->rdistif_num);
839 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
840 assert(id <= MAX_SPI_ID);
841
842 /*
843 * Disable interrupt, and ensure that any shared variable updates
844 * depending on out of band interrupt trigger are observed afterwards.
845 */
846 if (id < MIN_SPI_ID) {
847 /* For SGIs and PPIs */
848 gicr_set_icenabler0(
849 gicv3_driver_data->rdistif_base_addrs[proc_num],
850 id);
851
852 /* Write to clear enable requires waiting for pending writes */
853 gicr_wait_for_pending_write(
854 gicv3_driver_data->rdistif_base_addrs[proc_num]);
855 } else {
856 gicd_set_icenabler(gicv3_driver_data->gicd_base, id);
857
858 /* Write to clear enable requires waiting for pending writes */
859 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base);
860 }
861
862 dsbishst();
863 }
864
865 /*******************************************************************************
866 * This function sets the interrupt priority as supplied for the given interrupt
867 * id.
868 ******************************************************************************/
869 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
870 unsigned int priority)
871 {
872 uintptr_t gicr_base;
873
874 assert(gicv3_driver_data != NULL);
875 assert(gicv3_driver_data->gicd_base != 0U);
876 assert(proc_num < gicv3_driver_data->rdistif_num);
877 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
878 assert(id <= MAX_SPI_ID);
879
880 if (id < MIN_SPI_ID) {
881 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
882 gicr_set_ipriorityr(gicr_base, id, priority);
883 } else {
884 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority);
885 }
886 }
887
888 /*******************************************************************************
889 * This function assigns group for the interrupt identified by id. The proc_num
890 * is used if the interrupt is SGI or PPI, and programs the corresponding
891 * Redistributor interface. The group can be any of GICV3_INTR_GROUP*
892 ******************************************************************************/
893 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
894 unsigned int type)
895 {
896 bool igroup = false, grpmod = false;
897 uintptr_t gicr_base;
898
899 assert(gicv3_driver_data != NULL);
900 assert(gicv3_driver_data->gicd_base != 0U);
901 assert(proc_num < gicv3_driver_data->rdistif_num);
902 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
903
904 switch (type) {
905 case INTR_GROUP1S:
906 igroup = false;
907 grpmod = true;
908 break;
909 case INTR_GROUP0:
910 igroup = false;
911 grpmod = false;
912 break;
913 case INTR_GROUP1NS:
914 igroup = true;
915 grpmod = false;
916 break;
917 default:
918 assert(false);
919 break;
920 }
921
922 if (id < MIN_SPI_ID) {
923 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
924 if (igroup)
925 gicr_set_igroupr0(gicr_base, id);
926 else
927 gicr_clr_igroupr0(gicr_base, id);
928
929 if (grpmod)
930 gicr_set_igrpmodr0(gicr_base, id);
931 else
932 gicr_clr_igrpmodr0(gicr_base, id);
933 } else {
934 /* Serialize read-modify-write to Distributor registers */
935 spin_lock(&gic_lock);
936 if (igroup)
937 gicd_set_igroupr(gicv3_driver_data->gicd_base, id);
938 else
939 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id);
940
941 if (grpmod)
942 gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id);
943 else
944 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id);
945 spin_unlock(&gic_lock);
946 }
947 }
948
949 /*******************************************************************************
950 * This function raises the specified Secure Group 0 SGI.
951 *
952 * The target parameter must be a valid MPIDR in the system.
953 ******************************************************************************/
954 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target)
955 {
956 unsigned int tgt, aff3, aff2, aff1, aff0;
957 uint64_t sgi_val;
958
959 /* Verify interrupt number is in the SGI range */
960 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID));
961
962 /* Extract affinity fields from target */
963 aff0 = MPIDR_AFFLVL0_VAL(target);
964 aff1 = MPIDR_AFFLVL1_VAL(target);
965 aff2 = MPIDR_AFFLVL2_VAL(target);
966 aff3 = MPIDR_AFFLVL3_VAL(target);
967
968 /*
969 * Make target list from affinity 0, and ensure GICv3 SGI can target
970 * this PE.
971 */
972 assert(aff0 < GICV3_MAX_SGI_TARGETS);
973 tgt = BIT_32(aff0);
974
975 /* Raise SGI to PE specified by its affinity */
976 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF,
977 tgt);
978
979 /*
980 * Ensure that any shared variable updates depending on out of band
981 * interrupt trigger are observed before raising SGI.
982 */
983 dsbishst();
984 write_icc_sgi0r_el1(sgi_val);
985 isb();
986 }
987
988 /*******************************************************************************
989 * This function sets the interrupt routing for the given SPI interrupt id.
990 * The interrupt routing is specified in routing mode and mpidr.
991 *
992 * The routing mode can be either of:
993 * - GICV3_IRM_ANY
994 * - GICV3_IRM_PE
995 *
996 * The mpidr is the affinity of the PE to which the interrupt will be routed,
997 * and is ignored for routing mode GICV3_IRM_ANY.
998 ******************************************************************************/
999 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr)
1000 {
1001 unsigned long long aff;
1002 uint64_t router;
1003
1004 assert(gicv3_driver_data != NULL);
1005 assert(gicv3_driver_data->gicd_base != 0U);
1006
1007 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE));
1008 assert((id >= MIN_SPI_ID) && (id <= MAX_SPI_ID));
1009
1010 aff = gicd_irouter_val_from_mpidr(mpidr, irm);
1011 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff);
1012
1013 /*
1014 * In implementations that do not require 1 of N distribution of SPIs,
1015 * IRM might be RAZ/WI. Read back and verify IRM bit.
1016 */
1017 if (irm == GICV3_IRM_ANY) {
1018 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id);
1019 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) {
1020 ERROR("GICv3 implementation doesn't support routing ANY\n");
1021 panic();
1022 }
1023 }
1024 }
1025
1026 /*******************************************************************************
1027 * This function clears the pending status of an interrupt identified by id.
1028 * The proc_num is used if the interrupt is SGI or PPI, and programs the
1029 * corresponding Redistributor interface.
1030 ******************************************************************************/
1031 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num)
1032 {
1033 assert(gicv3_driver_data != NULL);
1034 assert(gicv3_driver_data->gicd_base != 0U);
1035 assert(proc_num < gicv3_driver_data->rdistif_num);
1036 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1037
1038 /*
1039 * Clear pending interrupt, and ensure that any shared variable updates
1040 * depending on out of band interrupt trigger are observed afterwards.
1041 */
1042 if (id < MIN_SPI_ID) {
1043 /* For SGIs and PPIs */
1044 gicr_set_icpendr0(gicv3_driver_data->rdistif_base_addrs[proc_num],
1045 id);
1046 } else {
1047 gicd_set_icpendr(gicv3_driver_data->gicd_base, id);
1048 }
1049 dsbishst();
1050 }
1051
1052 /*******************************************************************************
1053 * This function sets the pending status of an interrupt identified by id.
1054 * The proc_num is used if the interrupt is SGI or PPI and programs the
1055 * corresponding Redistributor interface.
1056 ******************************************************************************/
1057 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num)
1058 {
1059 assert(gicv3_driver_data != NULL);
1060 assert(gicv3_driver_data->gicd_base != 0U);
1061 assert(proc_num < gicv3_driver_data->rdistif_num);
1062 assert(gicv3_driver_data->rdistif_base_addrs != NULL);
1063
1064 /*
1065 * Ensure that any shared variable updates depending on out of band
1066 * interrupt trigger are observed before setting interrupt pending.
1067 */
1068 dsbishst();
1069 if (id < MIN_SPI_ID) {
1070 /* For SGIs and PPIs */
1071 gicr_set_ispendr0(gicv3_driver_data->rdistif_base_addrs[proc_num],
1072 id);
1073 } else {
1074 gicd_set_ispendr(gicv3_driver_data->gicd_base, id);
1075 }
1076 }
1077
1078 /*******************************************************************************
1079 * This function sets the PMR register with the supplied value. Returns the
1080 * original PMR.
1081 ******************************************************************************/
1082 unsigned int gicv3_set_pmr(unsigned int mask)
1083 {
1084 unsigned int old_mask;
1085
1086 old_mask = (uint32_t) read_icc_pmr_el1();
1087
1088 /*
1089 * Order memory updates w.r.t. PMR write, and ensure they're visible
1090 * before potential out of band interrupt trigger because of PMR update.
1091 * PMR system register writes are self-synchronizing, so no ISB required
1092 * thereafter.
1093 */
1094 dsbishst();
1095 write_icc_pmr_el1(mask);
1096
1097 return old_mask;
1098 }
1099
1100 /*******************************************************************************
1101 * This function delegates the responsibility of discovering the corresponding
1102 * Redistributor frames to each CPU itself. It is a modified version of
1103 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
1104 * unlike the previous way in which only the Primary CPU did the discovery of
1105 * all the Redistributor frames for every CPU. It also handles the scenario in
1106 * which the frames of various CPUs are not contiguous in physical memory.
1107 ******************************************************************************/
1108 int gicv3_rdistif_probe(const uintptr_t gicr_frame)
1109 {
1110 u_register_t mpidr;
1111 unsigned int proc_num, proc_self;
1112 uint64_t typer_val;
1113 uintptr_t rdistif_base;
1114 bool gicr_frame_found = false;
1115
1116 assert(gicv3_driver_data->gicr_base == 0U);
1117
1118 /* Ensure this function is called with Data Cache enabled */
1119 #ifndef __aarch64__
1120 assert((read_sctlr() & SCTLR_C_BIT) != 0U);
1121 #else
1122 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
1123 #endif /* !__aarch64__ */
1124
1125 proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1());
1126 rdistif_base = gicr_frame;
1127 do {
1128 typer_val = gicr_read_typer(rdistif_base);
1129 if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
1130 mpidr = mpidr_from_gicr_typer(typer_val);
1131 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
1132 } else {
1133 proc_num = (unsigned int)(typer_val >> TYPER_PROC_NUM_SHIFT) &
1134 TYPER_PROC_NUM_MASK;
1135 }
1136 if (proc_num == proc_self) {
1137 /* The base address doesn't need to be initialized on
1138 * every warm boot.
1139 */
1140 if (gicv3_driver_data->rdistif_base_addrs[proc_num] != 0U)
1141 return 0;
1142 gicv3_driver_data->rdistif_base_addrs[proc_num] =
1143 rdistif_base;
1144 gicr_frame_found = true;
1145 break;
1146 }
1147 rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT);
1148 } while ((typer_val & TYPER_LAST_BIT) == 0U);
1149
1150 if (!gicr_frame_found)
1151 return -1;
1152
1153 /*
1154 * Flush the driver data to ensure coherency. This is
1155 * not required if platform has HW_ASSISTED_COHERENCY
1156 * enabled.
1157 */
1158 #if !HW_ASSISTED_COHERENCY
1159 /*
1160 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
1161 */
1162 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]),
1163 sizeof(*(gicv3_driver_data->rdistif_base_addrs)));
1164 #endif
1165 return 0; /* Found matching GICR frame */
1166 }
Broadcom-s Trusted Firmware A