2 * Copyright (C) 2018 Marvell International Ltd.
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
8 /* AP806 Marvell SoC driver */
10 #include <common/debug.h>
11 #include <drivers/marvell/ccu.h>
12 #include <drivers/marvell/cache_llc.h>
13 #include <drivers/marvell/io_win.h>
14 #include <drivers/marvell/mci.h>
15 #include <drivers/marvell/mochi/ap_setup.h>
18 #include <mvebu_def.h>
20 #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
21 #define SMMU_sACR_PG_64K (1 << 16)
23 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \
25 #define GSPMU_CPU_CONTROL (0x1 << 0)
27 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \
29 #define CCU_SET_POC_OFFSET 5
31 #define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \
34 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100)
35 #define DVM_48BIT_VA_ENABLE (1 << 21)
37 /* Secure MoChi incoming access */
38 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738)
39 #define SEC_MOCHI_IN_ACC_IHB0_EN (1)
40 #define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3)
41 #define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6)
42 #define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9)
43 #define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \
44 SEC_MOCHI_IN_ACC_IHB1_EN | \
45 SEC_MOCHI_IN_ACC_IHB2_EN | \
46 SEC_MOCHI_IN_ACC_PIDI_EN)
48 /* SYSRST_OUTn Config definitions */
49 #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4)
50 #define WD_MASK_SYS_RST_OUT (1 << 2)
52 /* Generic Timer System Controller */
53 #define MVEBU_MSS_GTCR_REG (MVEBU_REGS_BASE + 0x581000)
54 #define MVEBU_MSS_GTCR_ENABLE_BIT 0x1
60 /* Used for Units of AP-806 (e.g. SDIO and etc) */
61 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580)
62 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
71 static void apn_sec_masters_access_en(uint32_t enable
)
75 /* Open/Close incoming access for all masters.
76 * The access is disabled in trusted boot mode
77 * Could only be done in EL3
79 reg
= mmio_read_32(SEC_MOCHI_IN_ACC_REG
);
81 mmio_write_32(SEC_MOCHI_IN_ACC_REG
, reg
|
82 SEC_IN_ACCESS_ENA_ALL_MASTERS
);
84 mmio_write_32(SEC_MOCHI_IN_ACC_REG
, reg
&
85 ~SEC_IN_ACCESS_ENA_ALL_MASTERS
);
88 static void setup_smmu(void)
92 /* Set the SMMU page size to 64 KB */
93 reg
= mmio_read_32(SMMU_sACR
);
94 reg
|= SMMU_sACR_PG_64K
;
95 mmio_write_32(SMMU_sACR
, reg
);
98 static void apn806_errata_wa_init(void)
101 * ERRATA ID: RES-3033912 - Internal Address Space Init state causes
102 * a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
103 * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
104 * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
105 * [0x80_0000, 0xff_ffff] that cause accesses to the
106 * segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI.
108 mmio_write_32(CCU_RGF(4), 0x37f9b809);
109 mmio_write_32(CCU_RGF(5), 0x7ffa0009);
112 static void init_aurora2(void)
116 /* Enable GSPMU control by CPU */
117 reg
= mmio_read_32(CCU_GSPMU_CR
);
118 reg
|= GSPMU_CPU_CONTROL
;
119 mmio_write_32(CCU_GSPMU_CR
, reg
);
122 /* Enable LLC for AP806 in exclusive mode */
125 /* Set point of coherency to DDR.
126 * This is required by units which have
129 reg
= mmio_read_32(CCU_HTC_CR
);
130 reg
|= (0x1 << CCU_SET_POC_OFFSET
);
131 mmio_write_32(CCU_HTC_CR
, reg
);
132 #endif /* LLC_ENABLE */
134 apn806_errata_wa_init();
138 /* MCIx indirect access register are based by default at 0xf4000000/0xf6000000
139 * to avoid conflict of internal registers of units connected via MCIx, which
140 * can be based on the same address (i.e CP1 base is also 0xf4000000),
141 * the following routines remaps the MCIx indirect bases to another domain
143 static void mci_remap_indirect_access_base(void)
147 for (mci
= 0; mci
< MCI_MAX_UNIT_ID
; mci
++)
148 mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci
),
149 MVEBU_MCI_REG_BASE_REMAP(mci
) >>
150 MCI_REMAP_OFF_SHIFT
);
153 static void apn806_axi_attr_init(void)
155 uint32_t index
, data
;
157 /* Initialize AXI attributes for APN806 */
159 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */
160 for (index
= 0; index
< AXI_MAX_ATTR
; index
++) {
162 /* DFX works with no coherent only -
163 * there's no option to configure the Ax-Cache and Ax-Domain
168 /* Set Ax-Cache as cacheable, no allocate, modifiable,
170 * The values are different because Read & Write
171 * definition is different in Ax-Cache
173 data
= mmio_read_32(MVEBU_AXI_ATTR_REG(index
));
174 data
&= ~MVEBU_AXI_ATTR_ARCACHE_MASK
;
175 data
|= (CACHE_ATTR_WRITE_ALLOC
|
176 CACHE_ATTR_CACHEABLE
|
177 CACHE_ATTR_BUFFERABLE
) <<
178 MVEBU_AXI_ATTR_ARCACHE_OFFSET
;
179 data
&= ~MVEBU_AXI_ATTR_AWCACHE_MASK
;
180 data
|= (CACHE_ATTR_READ_ALLOC
|
181 CACHE_ATTR_CACHEABLE
|
182 CACHE_ATTR_BUFFERABLE
) <<
183 MVEBU_AXI_ATTR_AWCACHE_OFFSET
;
184 /* Set Ax-Domain as Outer domain */
185 data
&= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK
;
186 data
|= DOMAIN_OUTER_SHAREABLE
<<
187 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET
;
188 data
&= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK
;
189 data
|= DOMAIN_OUTER_SHAREABLE
<<
190 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET
;
191 mmio_write_32(MVEBU_AXI_ATTR_REG(index
), data
);
196 static void dss_setup(void)
198 /* Enable 48-bit VA */
199 mmio_setbits_32(DSS_CR0
, DVM_48BIT_VA_ENABLE
);
202 void misc_soc_configurations(void)
206 /* Un-mask Watchdog reset from influencing the SYSRST_OUTn.
207 * Otherwise, upon WD timeout, the WD reset signal won't trigger reset
209 reg
= mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG
);
210 reg
&= ~(WD_MASK_SYS_RST_OUT
);
211 mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG
, reg
);
219 /* configure MCI mapping */
220 mci_remap_indirect_access_base();
222 /* configure IO_WIN windows */
223 init_io_win(MVEBU_AP0
);
225 /* configure CCU windows */
231 /* configure the SMMU */
234 /* Open APN incoming access for all masters */
235 apn_sec_masters_access_en(1);
237 /* configure axi for APN*/
238 apn806_axi_attr_init();
240 /* misc configuration of the SoC */
241 misc_soc_configurations();
244 void ap_ble_init(void)
248 int ap_get_count(void)