projects / openwrt / staging / blogic.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge tag 'pnp-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[openwrt/staging/blogic.git] / drivers / mmc / host / atmel-mci.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Atmel MultiMedia Card Interface driver
4 *
5 * Copyright (C) 2004-2008 Atmel Corporation
6 */
7 #include <linux/blkdev.h>
8 #include <linux/clk.h>
9 #include <linux/debugfs.h>
10 #include <linux/device.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/gpio.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/ioport.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/platform_device.h>
24 #include <linux/scatterlist.h>
25 #include <linux/seq_file.h>
26 #include <linux/slab.h>
27 #include <linux/stat.h>
28 #include <linux/types.h>
29
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/sdio.h>
32
33 #include <linux/atmel-mci.h>
34 #include <linux/atmel_pdc.h>
35 #include <linux/pm.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <asm/cacheflush.h>
40 #include <asm/io.h>
41 #include <asm/unaligned.h>
42
43 /*
44 * Superset of MCI IP registers integrated in Atmel AT91 Processor
45 * Registers and bitfields marked with [2] are only available in MCI2
46 */
47
48 /* MCI Register Definitions */
49 #define ATMCI_CR 0x0000 /* Control */
50 #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
51 #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
52 #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
53 #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
54 #define ATMCI_CR_SWRST BIT(7) /* Software Reset */
55 #define ATMCI_MR 0x0004 /* Mode */
56 #define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
57 #define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
58 #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
59 #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
60 #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
61 #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
62 #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
63 #define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
64 #define ATMCI_DTOR 0x0008 /* Data Timeout */
65 #define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
66 #define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
67 #define ATMCI_SDCR 0x000c /* SD Card / SDIO */
68 #define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
69 #define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
70 #define ATMCI_SDCSEL_MASK (3 << 0)
71 #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
72 #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
73 #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
74 #define ATMCI_SDCBUS_MASK (3 << 6)
75 #define ATMCI_ARGR 0x0010 /* Command Argument */
76 #define ATMCI_CMDR 0x0014 /* Command */
77 #define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
78 #define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
79 #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
80 #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
81 #define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
82 #define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
83 #define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
84 #define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
85 #define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
86 #define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
87 #define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
88 #define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
89 #define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
90 #define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
91 #define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
92 #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
93 #define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
94 #define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
95 #define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
96 #define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
97 #define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
98 #define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
99 #define ATMCI_BLKR 0x0018 /* Block */
100 #define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
101 #define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
102 #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
103 #define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
104 #define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
105 #define ATMCI_RSPR 0x0020 /* Response 0 */
106 #define ATMCI_RSPR1 0x0024 /* Response 1 */
107 #define ATMCI_RSPR2 0x0028 /* Response 2 */
108 #define ATMCI_RSPR3 0x002c /* Response 3 */
109 #define ATMCI_RDR 0x0030 /* Receive Data */
110 #define ATMCI_TDR 0x0034 /* Transmit Data */
111 #define ATMCI_SR 0x0040 /* Status */
112 #define ATMCI_IER 0x0044 /* Interrupt Enable */
113 #define ATMCI_IDR 0x0048 /* Interrupt Disable */
114 #define ATMCI_IMR 0x004c /* Interrupt Mask */
115 #define ATMCI_CMDRDY BIT(0) /* Command Ready */
116 #define ATMCI_RXRDY BIT(1) /* Receiver Ready */
117 #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
118 #define ATMCI_BLKE BIT(3) /* Data Block Ended */
119 #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
120 #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
121 #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
122 #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
123 #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
124 #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
125 #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
126 #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
127 #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
128 #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
129 #define ATMCI_RINDE BIT(16) /* Response Index Error */
130 #define ATMCI_RDIRE BIT(17) /* Response Direction Error */
131 #define ATMCI_RCRCE BIT(18) /* Response CRC Error */
132 #define ATMCI_RENDE BIT(19) /* Response End Bit Error */
133 #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
134 #define ATMCI_DCRCE BIT(21) /* Data CRC Error */
135 #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
136 #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
137 #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
138 #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
139 #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
140 #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
141 #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
142 #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
143 #define ATMCI_OVRE BIT(30) /* RX Overrun Error */
144 #define ATMCI_UNRE BIT(31) /* TX Underrun Error */
145 #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
146 #define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
147 #define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
148 #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
149 #define ATMCI_CFG 0x0054 /* Configuration[2] */
150 #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
151 #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
152 #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
153 #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
154 #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
155 #define ATMCI_WP_EN BIT(0) /* WP Enable */
156 #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
157 #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
158 #define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
159 #define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
160 #define ATMCI_VERSION 0x00FC /* Version */
161 #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
162
163 /* This is not including the FIFO Aperture on MCI2 */
164 #define ATMCI_REGS_SIZE 0x100
165
166 /* Register access macros */
167 #define atmci_readl(port, reg) \
168 __raw_readl((port)->regs + reg)
169 #define atmci_writel(port, reg, value) \
170 __raw_writel((value), (port)->regs + reg)
171
172 #define ATMCI_CMD_TIMEOUT_MS 2000
173 #define AUTOSUSPEND_DELAY 50
174
175 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
176 #define ATMCI_DMA_THRESHOLD 16
177
178 enum {
179 EVENT_CMD_RDY = 0,
180 EVENT_XFER_COMPLETE,
181 EVENT_NOTBUSY,
182 EVENT_DATA_ERROR,
183 };
184
185 enum atmel_mci_state {
186 STATE_IDLE = 0,
187 STATE_SENDING_CMD,
188 STATE_DATA_XFER,
189 STATE_WAITING_NOTBUSY,
190 STATE_SENDING_STOP,
191 STATE_END_REQUEST,
192 };
193
194 enum atmci_xfer_dir {
195 XFER_RECEIVE = 0,
196 XFER_TRANSMIT,
197 };
198
199 enum atmci_pdc_buf {
200 PDC_FIRST_BUF = 0,
201 PDC_SECOND_BUF,
202 };
203
204 struct atmel_mci_caps {
205 bool has_dma_conf_reg;
206 bool has_pdc;
207 bool has_cfg_reg;
208 bool has_cstor_reg;
209 bool has_highspeed;
210 bool has_rwproof;
211 bool has_odd_clk_div;
212 bool has_bad_data_ordering;
213 bool need_reset_after_xfer;
214 bool need_blksz_mul_4;
215 bool need_notbusy_for_read_ops;
216 };
217
218 struct atmel_mci_dma {
219 struct dma_chan *chan;
220 struct dma_async_tx_descriptor *data_desc;
221 };
222
223 /**
224 * struct atmel_mci - MMC controller state shared between all slots
225 * @lock: Spinlock protecting the queue and associated data.
226 * @regs: Pointer to MMIO registers.
227 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
228 * @pio_offset: Offset into the current scatterlist entry.
229 * @buffer: Buffer used if we don't have the r/w proof capability. We
230 * don't have the time to switch pdc buffers so we have to use only
231 * one buffer for the full transaction.
232 * @buf_size: size of the buffer.
233 * @phys_buf_addr: buffer address needed for pdc.
234 * @cur_slot: The slot which is currently using the controller.
235 * @mrq: The request currently being processed on @cur_slot,
236 * or NULL if the controller is idle.
237 * @cmd: The command currently being sent to the card, or NULL.
238 * @data: The data currently being transferred, or NULL if no data
239 * transfer is in progress.
240 * @data_size: just data->blocks * data->blksz.
241 * @dma: DMA client state.
242 * @data_chan: DMA channel being used for the current data transfer.
243 * @cmd_status: Snapshot of SR taken upon completion of the current
244 * command. Only valid when EVENT_CMD_COMPLETE is pending.
245 * @data_status: Snapshot of SR taken upon completion of the current
246 * data transfer. Only valid when EVENT_DATA_COMPLETE or
247 * EVENT_DATA_ERROR is pending.
248 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
249 * to be sent.
250 * @tasklet: Tasklet running the request state machine.
251 * @pending_events: Bitmask of events flagged by the interrupt handler
252 * to be processed by the tasklet.
253 * @completed_events: Bitmask of events which the state machine has
254 * processed.
255 * @state: Tasklet state.
256 * @queue: List of slots waiting for access to the controller.
257 * @need_clock_update: Update the clock rate before the next request.
258 * @need_reset: Reset controller before next request.
259 * @timer: Timer to balance the data timeout error flag which cannot rise.
260 * @mode_reg: Value of the MR register.
261 * @cfg_reg: Value of the CFG register.
262 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
263 * rate and timeout calculations.
264 * @mapbase: Physical address of the MMIO registers.
265 * @mck: The peripheral bus clock hooked up to the MMC controller.
266 * @pdev: Platform device associated with the MMC controller.
267 * @slot: Slots sharing this MMC controller.
268 * @caps: MCI capabilities depending on MCI version.
269 * @prepare_data: function to setup MCI before data transfer which
270 * depends on MCI capabilities.
271 * @submit_data: function to start data transfer which depends on MCI
272 * capabilities.
273 * @stop_transfer: function to stop data transfer which depends on MCI
274 * capabilities.
275 *
276 * Locking
277 * =======
278 *
279 * @lock is a softirq-safe spinlock protecting @queue as well as
280 * @cur_slot, @mrq and @state. These must always be updated
281 * at the same time while holding @lock.
282 *
283 * @lock also protects mode_reg and need_clock_update since these are
284 * used to synchronize mode register updates with the queue
285 * processing.
286 *
287 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
288 * and must always be written at the same time as the slot is added to
289 * @queue.
290 *
291 * @pending_events and @completed_events are accessed using atomic bit
292 * operations, so they don't need any locking.
293 *
294 * None of the fields touched by the interrupt handler need any
295 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
296 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
297 * interrupts must be disabled and @data_status updated with a
298 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
299 * CMDRDY interrupt must be disabled and @cmd_status updated with a
300 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
301 * bytes_xfered field of @data must be written. This is ensured by
302 * using barriers.
303 */
304 struct atmel_mci {
305 spinlock_t lock;
306 void __iomem *regs;
307
308 struct scatterlist *sg;
309 unsigned int sg_len;
310 unsigned int pio_offset;
311 unsigned int *buffer;
312 unsigned int buf_size;
313 dma_addr_t buf_phys_addr;
314
315 struct atmel_mci_slot *cur_slot;
316 struct mmc_request *mrq;
317 struct mmc_command *cmd;
318 struct mmc_data *data;
319 unsigned int data_size;
320
321 struct atmel_mci_dma dma;
322 struct dma_chan *data_chan;
323 struct dma_slave_config dma_conf;
324
325 u32 cmd_status;
326 u32 data_status;
327 u32 stop_cmdr;
328
329 struct tasklet_struct tasklet;
330 unsigned long pending_events;
331 unsigned long completed_events;
332 enum atmel_mci_state state;
333 struct list_head queue;
334
335 bool need_clock_update;
336 bool need_reset;
337 struct timer_list timer;
338 u32 mode_reg;
339 u32 cfg_reg;
340 unsigned long bus_hz;
341 unsigned long mapbase;
342 struct clk *mck;
343 struct platform_device *pdev;
344
345 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
346
347 struct atmel_mci_caps caps;
348
349 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
350 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
351 void (*stop_transfer)(struct atmel_mci *host);
352 };
353
354 /**
355 * struct atmel_mci_slot - MMC slot state
356 * @mmc: The mmc_host representing this slot.
357 * @host: The MMC controller this slot is using.
358 * @sdc_reg: Value of SDCR to be written before using this slot.
359 * @sdio_irq: SDIO irq mask for this slot.
360 * @mrq: mmc_request currently being processed or waiting to be
361 * processed, or NULL when the slot is idle.
362 * @queue_node: List node for placing this node in the @queue list of
363 * &struct atmel_mci.
364 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
365 * @flags: Random state bits associated with the slot.
366 * @detect_pin: GPIO pin used for card detection, or negative if not
367 * available.
368 * @wp_pin: GPIO pin used for card write protect sending, or negative
369 * if not available.
370 * @detect_is_active_high: The state of the detect pin when it is active.
371 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
372 */
373 struct atmel_mci_slot {
374 struct mmc_host *mmc;
375 struct atmel_mci *host;
376
377 u32 sdc_reg;
378 u32 sdio_irq;
379
380 struct mmc_request *mrq;
381 struct list_head queue_node;
382
383 unsigned int clock;
384 unsigned long flags;
385 #define ATMCI_CARD_PRESENT 0
386 #define ATMCI_CARD_NEED_INIT 1
387 #define ATMCI_SHUTDOWN 2
388
389 int detect_pin;
390 int wp_pin;
391 bool detect_is_active_high;
392
393 struct timer_list detect_timer;
394 };
395
396 #define atmci_test_and_clear_pending(host, event) \
397 test_and_clear_bit(event, &host->pending_events)
398 #define atmci_set_completed(host, event) \
399 set_bit(event, &host->completed_events)
400 #define atmci_set_pending(host, event) \
401 set_bit(event, &host->pending_events)
402
403 /*
404 * The debugfs stuff below is mostly optimized away when
405 * CONFIG_DEBUG_FS is not set.
406 */
407 static int atmci_req_show(struct seq_file *s, void *v)
408 {
409 struct atmel_mci_slot *slot = s->private;
410 struct mmc_request *mrq;
411 struct mmc_command *cmd;
412 struct mmc_command *stop;
413 struct mmc_data *data;
414
415 /* Make sure we get a consistent snapshot */
416 spin_lock_bh(&slot->host->lock);
417 mrq = slot->mrq;
418
419 if (mrq) {
420 cmd = mrq->cmd;
421 data = mrq->data;
422 stop = mrq->stop;
423
424 if (cmd)
425 seq_printf(s,
426 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
427 cmd->opcode, cmd->arg, cmd->flags,
428 cmd->resp[0], cmd->resp[1], cmd->resp[2],
429 cmd->resp[3], cmd->error);
430 if (data)
431 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
432 data->bytes_xfered, data->blocks,
433 data->blksz, data->flags, data->error);
434 if (stop)
435 seq_printf(s,
436 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
437 stop->opcode, stop->arg, stop->flags,
438 stop->resp[0], stop->resp[1], stop->resp[2],
439 stop->resp[3], stop->error);
440 }
441
442 spin_unlock_bh(&slot->host->lock);
443
444 return 0;
445 }
446
447 DEFINE_SHOW_ATTRIBUTE(atmci_req);
448
449 static void atmci_show_status_reg(struct seq_file *s,
450 const char *regname, u32 value)
451 {
452 static const char *sr_bit[] = {
453 [0] = "CMDRDY",
454 [1] = "RXRDY",
455 [2] = "TXRDY",
456 [3] = "BLKE",
457 [4] = "DTIP",
458 [5] = "NOTBUSY",
459 [6] = "ENDRX",
460 [7] = "ENDTX",
461 [8] = "SDIOIRQA",
462 [9] = "SDIOIRQB",
463 [12] = "SDIOWAIT",
464 [14] = "RXBUFF",
465 [15] = "TXBUFE",
466 [16] = "RINDE",
467 [17] = "RDIRE",
468 [18] = "RCRCE",
469 [19] = "RENDE",
470 [20] = "RTOE",
471 [21] = "DCRCE",
472 [22] = "DTOE",
473 [23] = "CSTOE",
474 [24] = "BLKOVRE",
475 [25] = "DMADONE",
476 [26] = "FIFOEMPTY",
477 [27] = "XFRDONE",
478 [30] = "OVRE",
479 [31] = "UNRE",
480 };
481 unsigned int i;
482
483 seq_printf(s, "%s:\t0x%08x", regname, value);
484 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
485 if (value & (1 << i)) {
486 if (sr_bit[i])
487 seq_printf(s, " %s", sr_bit[i]);
488 else
489 seq_puts(s, " UNKNOWN");
490 }
491 }
492 seq_putc(s, '\n');
493 }
494
495 static int atmci_regs_show(struct seq_file *s, void *v)
496 {
497 struct atmel_mci *host = s->private;
498 u32 *buf;
499 int ret = 0;
500
501
502 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
503 if (!buf)
504 return -ENOMEM;
505
506 pm_runtime_get_sync(&host->pdev->dev);
507
508 /*
509 * Grab a more or less consistent snapshot. Note that we're
510 * not disabling interrupts, so IMR and SR may not be
511 * consistent.
512 */
513 spin_lock_bh(&host->lock);
514 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
515 spin_unlock_bh(&host->lock);
516
517 pm_runtime_mark_last_busy(&host->pdev->dev);
518 pm_runtime_put_autosuspend(&host->pdev->dev);
519
520 seq_printf(s, "MR:\t0x%08x%s%s ",
521 buf[ATMCI_MR / 4],
522 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
523 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
524 if (host->caps.has_odd_clk_div)
525 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
526 ((buf[ATMCI_MR / 4] & 0xff) << 1)
527 | ((buf[ATMCI_MR / 4] >> 16) & 1));
528 else
529 seq_printf(s, "CLKDIV=%u\n",
530 (buf[ATMCI_MR / 4] & 0xff));
531 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
532 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
533 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
534 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
535 buf[ATMCI_BLKR / 4],
536 buf[ATMCI_BLKR / 4] & 0xffff,
537 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
538 if (host->caps.has_cstor_reg)
539 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
540
541 /* Don't read RSPR and RDR; it will consume the data there */
542
543 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
544 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
545
546 if (host->caps.has_dma_conf_reg) {
547 u32 val;
548
549 val = buf[ATMCI_DMA / 4];
550 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
551 val, val & 3,
552 ((val >> 4) & 3) ?
553 1 << (((val >> 4) & 3) + 1) : 1,
554 val & ATMCI_DMAEN ? " DMAEN" : "");
555 }
556 if (host->caps.has_cfg_reg) {
557 u32 val;
558
559 val = buf[ATMCI_CFG / 4];
560 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
561 val,
562 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
563 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
564 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
565 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
566 }
567
568 kfree(buf);
569
570 return ret;
571 }
572
573 DEFINE_SHOW_ATTRIBUTE(atmci_regs);
574
575 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
576 {
577 struct mmc_host *mmc = slot->mmc;
578 struct atmel_mci *host = slot->host;
579 struct dentry *root;
580
581 root = mmc->debugfs_root;
582 if (!root)
583 return;
584
585 debugfs_create_file("regs", S_IRUSR, root, host, &atmci_regs_fops);
586 debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
587 debugfs_create_u32("state", S_IRUSR, root, &host->state);
588 debugfs_create_xul("pending_events", S_IRUSR, root,
589 &host->pending_events);
590 debugfs_create_xul("completed_events", S_IRUSR, root,
591 &host->completed_events);
592 }
593
594 #if defined(CONFIG_OF)
595 static const struct of_device_id atmci_dt_ids[] = {
596 { .compatible = "atmel,hsmci" },
597 { /* sentinel */ }
598 };
599
600 MODULE_DEVICE_TABLE(of, atmci_dt_ids);
601
602 static struct mci_platform_data*
603 atmci_of_init(struct platform_device *pdev)
604 {
605 struct device_node *np = pdev->dev.of_node;
606 struct device_node *cnp;
607 struct mci_platform_data *pdata;
608 u32 slot_id;
609
610 if (!np) {
611 dev_err(&pdev->dev, "device node not found\n");
612 return ERR_PTR(-EINVAL);
613 }
614
615 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
616 if (!pdata)
617 return ERR_PTR(-ENOMEM);
618
619 for_each_child_of_node(np, cnp) {
620 if (of_property_read_u32(cnp, "reg", &slot_id)) {
621 dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
622 cnp);
623 continue;
624 }
625
626 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
627 dev_warn(&pdev->dev, "can't have more than %d slots\n",
628 ATMCI_MAX_NR_SLOTS);
629 of_node_put(cnp);
630 break;
631 }
632
633 if (of_property_read_u32(cnp, "bus-width",
634 &pdata->slot[slot_id].bus_width))
635 pdata->slot[slot_id].bus_width = 1;
636
637 pdata->slot[slot_id].detect_pin =
638 of_get_named_gpio(cnp, "cd-gpios", 0);
639
640 pdata->slot[slot_id].detect_is_active_high =
641 of_property_read_bool(cnp, "cd-inverted");
642
643 pdata->slot[slot_id].non_removable =
644 of_property_read_bool(cnp, "non-removable");
645
646 pdata->slot[slot_id].wp_pin =
647 of_get_named_gpio(cnp, "wp-gpios", 0);
648 }
649
650 return pdata;
651 }
652 #else /* CONFIG_OF */
653 static inline struct mci_platform_data*
654 atmci_of_init(struct platform_device *dev)
655 {
656 return ERR_PTR(-EINVAL);
657 }
658 #endif
659
660 static inline unsigned int atmci_get_version(struct atmel_mci *host)
661 {
662 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
663 }
664
665 /*
666 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
667 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
668 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
669 * 8 -> 3, 16 -> 4.
670 *
671 * This can be done by finding most significant bit set.
672 */
673 static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
674 unsigned int maxburst)
675 {
676 unsigned int version = atmci_get_version(host);
677 unsigned int offset = 2;
678
679 if (version >= 0x600)
680 offset = 1;
681
682 if (maxburst > 1)
683 return fls(maxburst) - offset;
684 else
685 return 0;
686 }
687
688 static void atmci_timeout_timer(struct timer_list *t)
689 {
690 struct atmel_mci *host;
691
692 host = from_timer(host, t, timer);
693
694 dev_dbg(&host->pdev->dev, "software timeout\n");
695
696 if (host->mrq->cmd->data) {
697 host->mrq->cmd->data->error = -ETIMEDOUT;
698 host->data = NULL;
699 /*
700 * With some SDIO modules, sometimes DMA transfer hangs. If
701 * stop_transfer() is not called then the DMA request is not
702 * removed, following ones are queued and never computed.
703 */
704 if (host->state == STATE_DATA_XFER)
705 host->stop_transfer(host);
706 } else {
707 host->mrq->cmd->error = -ETIMEDOUT;
708 host->cmd = NULL;
709 }
710 host->need_reset = 1;
711 host->state = STATE_END_REQUEST;
712 smp_wmb();
713 tasklet_schedule(&host->tasklet);
714 }
715
716 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
717 unsigned int ns)
718 {
719 /*
720 * It is easier here to use us instead of ns for the timeout,
721 * it prevents from overflows during calculation.
722 */
723 unsigned int us = DIV_ROUND_UP(ns, 1000);
724
725 /* Maximum clock frequency is host->bus_hz/2 */
726 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
727 }
728
729 static void atmci_set_timeout(struct atmel_mci *host,
730 struct atmel_mci_slot *slot, struct mmc_data *data)
731 {
732 static unsigned dtomul_to_shift[] = {
733 0, 4, 7, 8, 10, 12, 16, 20
734 };
735 unsigned timeout;
736 unsigned dtocyc;
737 unsigned dtomul;
738
739 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
740 + data->timeout_clks;
741
742 for (dtomul = 0; dtomul < 8; dtomul++) {
743 unsigned shift = dtomul_to_shift[dtomul];
744 dtocyc = (timeout + (1 << shift) - 1) >> shift;
745 if (dtocyc < 15)
746 break;
747 }
748
749 if (dtomul >= 8) {
750 dtomul = 7;
751 dtocyc = 15;
752 }
753
754 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
755 dtocyc << dtomul_to_shift[dtomul]);
756 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
757 }
758
759 /*
760 * Return mask with command flags to be enabled for this command.
761 */
762 static u32 atmci_prepare_command(struct mmc_host *mmc,
763 struct mmc_command *cmd)
764 {
765 struct mmc_data *data;
766 u32 cmdr;
767
768 cmd->error = -EINPROGRESS;
769
770 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
771
772 if (cmd->flags & MMC_RSP_PRESENT) {
773 if (cmd->flags & MMC_RSP_136)
774 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
775 else
776 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
777 }
778
779 /*
780 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
781 * it's too difficult to determine whether this is an ACMD or
782 * not. Better make it 64.
783 */
784 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
785
786 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
787 cmdr |= ATMCI_CMDR_OPDCMD;
788
789 data = cmd->data;
790 if (data) {
791 cmdr |= ATMCI_CMDR_START_XFER;
792
793 if (cmd->opcode == SD_IO_RW_EXTENDED) {
794 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
795 } else {
796 if (data->blocks > 1)
797 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
798 else
799 cmdr |= ATMCI_CMDR_BLOCK;
800 }
801
802 if (data->flags & MMC_DATA_READ)
803 cmdr |= ATMCI_CMDR_TRDIR_READ;
804 }
805
806 return cmdr;
807 }
808
809 static void atmci_send_command(struct atmel_mci *host,
810 struct mmc_command *cmd, u32 cmd_flags)
811 {
812 unsigned int timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
813 ATMCI_CMD_TIMEOUT_MS;
814
815 WARN_ON(host->cmd);
816 host->cmd = cmd;
817
818 dev_vdbg(&host->pdev->dev,
819 "start command: ARGR=0x%08x CMDR=0x%08x\n",
820 cmd->arg, cmd_flags);
821
822 atmci_writel(host, ATMCI_ARGR, cmd->arg);
823 atmci_writel(host, ATMCI_CMDR, cmd_flags);
824
825 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
826 }
827
828 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
829 {
830 dev_dbg(&host->pdev->dev, "send stop command\n");
831 atmci_send_command(host, data->stop, host->stop_cmdr);
832 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
833 }
834
835 /*
836 * Configure given PDC buffer taking care of alignement issues.
837 * Update host->data_size and host->sg.
838 */
839 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
840 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
841 {
842 u32 pointer_reg, counter_reg;
843 unsigned int buf_size;
844
845 if (dir == XFER_RECEIVE) {
846 pointer_reg = ATMEL_PDC_RPR;
847 counter_reg = ATMEL_PDC_RCR;
848 } else {
849 pointer_reg = ATMEL_PDC_TPR;
850 counter_reg = ATMEL_PDC_TCR;
851 }
852
853 if (buf_nb == PDC_SECOND_BUF) {
854 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
855 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
856 }
857
858 if (!host->caps.has_rwproof) {
859 buf_size = host->buf_size;
860 atmci_writel(host, pointer_reg, host->buf_phys_addr);
861 } else {
862 buf_size = sg_dma_len(host->sg);
863 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
864 }
865
866 if (host->data_size <= buf_size) {
867 if (host->data_size & 0x3) {
868 /* If size is different from modulo 4, transfer bytes */
869 atmci_writel(host, counter_reg, host->data_size);
870 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
871 } else {
872 /* Else transfer 32-bits words */
873 atmci_writel(host, counter_reg, host->data_size / 4);
874 }
875 host->data_size = 0;
876 } else {
877 /* We assume the size of a page is 32-bits aligned */
878 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
879 host->data_size -= sg_dma_len(host->sg);
880 if (host->data_size)
881 host->sg = sg_next(host->sg);
882 }
883 }
884
885 /*
886 * Configure PDC buffer according to the data size ie configuring one or two
887 * buffers. Don't use this function if you want to configure only the second
888 * buffer. In this case, use atmci_pdc_set_single_buf.
889 */
890 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
891 {
892 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
893 if (host->data_size)
894 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
895 }
896
897 /*
898 * Unmap sg lists, called when transfer is finished.
899 */
900 static void atmci_pdc_cleanup(struct atmel_mci *host)
901 {
902 struct mmc_data *data = host->data;
903
904 if (data)
905 dma_unmap_sg(&host->pdev->dev,
906 data->sg, data->sg_len,
907 mmc_get_dma_dir(data));
908 }
909
910 /*
911 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
912 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
913 * interrupt needed for both transfer directions.
914 */
915 static void atmci_pdc_complete(struct atmel_mci *host)
916 {
917 int transfer_size = host->data->blocks * host->data->blksz;
918 int i;
919
920 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
921
922 if ((!host->caps.has_rwproof)
923 && (host->data->flags & MMC_DATA_READ)) {
924 if (host->caps.has_bad_data_ordering)
925 for (i = 0; i < transfer_size; i++)
926 host->buffer[i] = swab32(host->buffer[i]);
927 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
928 host->buffer, transfer_size);
929 }
930
931 atmci_pdc_cleanup(host);
932
933 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
934 atmci_set_pending(host, EVENT_XFER_COMPLETE);
935 tasklet_schedule(&host->tasklet);
936 }
937
938 static void atmci_dma_cleanup(struct atmel_mci *host)
939 {
940 struct mmc_data *data = host->data;
941
942 if (data)
943 dma_unmap_sg(host->dma.chan->device->dev,
944 data->sg, data->sg_len,
945 mmc_get_dma_dir(data));
946 }
947
948 /*
949 * This function is called by the DMA driver from tasklet context.
950 */
951 static void atmci_dma_complete(void *arg)
952 {
953 struct atmel_mci *host = arg;
954 struct mmc_data *data = host->data;
955
956 dev_vdbg(&host->pdev->dev, "DMA complete\n");
957
958 if (host->caps.has_dma_conf_reg)
959 /* Disable DMA hardware handshaking on MCI */
960 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
961
962 atmci_dma_cleanup(host);
963
964 /*
965 * If the card was removed, data will be NULL. No point trying
966 * to send the stop command or waiting for NBUSY in this case.
967 */
968 if (data) {
969 dev_dbg(&host->pdev->dev,
970 "(%s) set pending xfer complete\n", __func__);
971 atmci_set_pending(host, EVENT_XFER_COMPLETE);
972 tasklet_schedule(&host->tasklet);
973
974 /*
975 * Regardless of what the documentation says, we have
976 * to wait for NOTBUSY even after block read
977 * operations.
978 *
979 * When the DMA transfer is complete, the controller
980 * may still be reading the CRC from the card, i.e.
981 * the data transfer is still in progress and we
982 * haven't seen all the potential error bits yet.
983 *
984 * The interrupt handler will schedule a different
985 * tasklet to finish things up when the data transfer
986 * is completely done.
987 *
988 * We may not complete the mmc request here anyway
989 * because the mmc layer may call back and cause us to
990 * violate the "don't submit new operations from the
991 * completion callback" rule of the dma engine
992 * framework.
993 */
994 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
995 }
996 }
997
998 /*
999 * Returns a mask of interrupt flags to be enabled after the whole
1000 * request has been prepared.
1001 */
1002 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1003 {
1004 u32 iflags;
1005
1006 data->error = -EINPROGRESS;
1007
1008 host->sg = data->sg;
1009 host->sg_len = data->sg_len;
1010 host->data = data;
1011 host->data_chan = NULL;
1012
1013 iflags = ATMCI_DATA_ERROR_FLAGS;
1014
1015 /*
1016 * Errata: MMC data write operation with less than 12
1017 * bytes is impossible.
1018 *
1019 * Errata: MCI Transmit Data Register (TDR) FIFO
1020 * corruption when length is not multiple of 4.
1021 */
1022 if (data->blocks * data->blksz < 12
1023 || (data->blocks * data->blksz) & 3)
1024 host->need_reset = true;
1025
1026 host->pio_offset = 0;
1027 if (data->flags & MMC_DATA_READ)
1028 iflags |= ATMCI_RXRDY;
1029 else
1030 iflags |= ATMCI_TXRDY;
1031
1032 return iflags;
1033 }
1034
1035 /*
1036 * Set interrupt flags and set block length into the MCI mode register even
1037 * if this value is also accessible in the MCI block register. It seems to be
1038 * necessary before the High Speed MCI version. It also map sg and configure
1039 * PDC registers.
1040 */
1041 static u32
1042 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1043 {
1044 u32 iflags, tmp;
1045 int i;
1046
1047 data->error = -EINPROGRESS;
1048
1049 host->data = data;
1050 host->sg = data->sg;
1051 iflags = ATMCI_DATA_ERROR_FLAGS;
1052
1053 /* Enable pdc mode */
1054 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1055
1056 if (data->flags & MMC_DATA_READ)
1057 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1058 else
1059 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1060
1061 /* Set BLKLEN */
1062 tmp = atmci_readl(host, ATMCI_MR);
1063 tmp &= 0x0000ffff;
1064 tmp |= ATMCI_BLKLEN(data->blksz);
1065 atmci_writel(host, ATMCI_MR, tmp);
1066
1067 /* Configure PDC */
1068 host->data_size = data->blocks * data->blksz;
1069 dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1070 mmc_get_dma_dir(data));
1071
1072 if ((!host->caps.has_rwproof)
1073 && (host->data->flags & MMC_DATA_WRITE)) {
1074 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1075 host->buffer, host->data_size);
1076 if (host->caps.has_bad_data_ordering)
1077 for (i = 0; i < host->data_size; i++)
1078 host->buffer[i] = swab32(host->buffer[i]);
1079 }
1080
1081 if (host->data_size)
1082 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1083 XFER_RECEIVE : XFER_TRANSMIT);
1084 return iflags;
1085 }
1086
1087 static u32
1088 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1089 {
1090 struct dma_chan *chan;
1091 struct dma_async_tx_descriptor *desc;
1092 struct scatterlist *sg;
1093 unsigned int i;
1094 enum dma_transfer_direction slave_dirn;
1095 unsigned int sglen;
1096 u32 maxburst;
1097 u32 iflags;
1098
1099 data->error = -EINPROGRESS;
1100
1101 WARN_ON(host->data);
1102 host->sg = NULL;
1103 host->data = data;
1104
1105 iflags = ATMCI_DATA_ERROR_FLAGS;
1106
1107 /*
1108 * We don't do DMA on "complex" transfers, i.e. with
1109 * non-word-aligned buffers or lengths. Also, we don't bother
1110 * with all the DMA setup overhead for short transfers.
1111 */
1112 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1113 return atmci_prepare_data(host, data);
1114 if (data->blksz & 3)
1115 return atmci_prepare_data(host, data);
1116
1117 for_each_sg(data->sg, sg, data->sg_len, i) {
1118 if (sg->offset & 3 || sg->length & 3)
1119 return atmci_prepare_data(host, data);
1120 }
1121
1122 /* If we don't have a channel, we can't do DMA */
1123 chan = host->dma.chan;
1124 if (chan)
1125 host->data_chan = chan;
1126
1127 if (!chan)
1128 return -ENODEV;
1129
1130 if (data->flags & MMC_DATA_READ) {
1131 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1132 maxburst = atmci_convert_chksize(host,
1133 host->dma_conf.src_maxburst);
1134 } else {
1135 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1136 maxburst = atmci_convert_chksize(host,
1137 host->dma_conf.dst_maxburst);
1138 }
1139
1140 if (host->caps.has_dma_conf_reg)
1141 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1142 ATMCI_DMAEN);
1143
1144 sglen = dma_map_sg(chan->device->dev, data->sg,
1145 data->sg_len, mmc_get_dma_dir(data));
1146
1147 dmaengine_slave_config(chan, &host->dma_conf);
1148 desc = dmaengine_prep_slave_sg(chan,
1149 data->sg, sglen, slave_dirn,
1150 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1151 if (!desc)
1152 goto unmap_exit;
1153
1154 host->dma.data_desc = desc;
1155 desc->callback = atmci_dma_complete;
1156 desc->callback_param = host;
1157
1158 return iflags;
1159 unmap_exit:
1160 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1161 mmc_get_dma_dir(data));
1162 return -ENOMEM;
1163 }
1164
1165 static void
1166 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1167 {
1168 return;
1169 }
1170
1171 /*
1172 * Start PDC according to transfer direction.
1173 */
1174 static void
1175 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1176 {
1177 if (data->flags & MMC_DATA_READ)
1178 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1179 else
1180 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1181 }
1182
1183 static void
1184 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1185 {
1186 struct dma_chan *chan = host->data_chan;
1187 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1188
1189 if (chan) {
1190 dmaengine_submit(desc);
1191 dma_async_issue_pending(chan);
1192 }
1193 }
1194
1195 static void atmci_stop_transfer(struct atmel_mci *host)
1196 {
1197 dev_dbg(&host->pdev->dev,
1198 "(%s) set pending xfer complete\n", __func__);
1199 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1200 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1201 }
1202
1203 /*
1204 * Stop data transfer because error(s) occurred.
1205 */
1206 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1207 {
1208 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1209 }
1210
1211 static void atmci_stop_transfer_dma(struct atmel_mci *host)
1212 {
1213 struct dma_chan *chan = host->data_chan;
1214
1215 if (chan) {
1216 dmaengine_terminate_all(chan);
1217 atmci_dma_cleanup(host);
1218 } else {
1219 /* Data transfer was stopped by the interrupt handler */
1220 dev_dbg(&host->pdev->dev,
1221 "(%s) set pending xfer complete\n", __func__);
1222 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1223 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1224 }
1225 }
1226
1227 /*
1228 * Start a request: prepare data if needed, prepare the command and activate
1229 * interrupts.
1230 */
1231 static void atmci_start_request(struct atmel_mci *host,
1232 struct atmel_mci_slot *slot)
1233 {
1234 struct mmc_request *mrq;
1235 struct mmc_command *cmd;
1236 struct mmc_data *data;
1237 u32 iflags;
1238 u32 cmdflags;
1239
1240 mrq = slot->mrq;
1241 host->cur_slot = slot;
1242 host->mrq = mrq;
1243
1244 host->pending_events = 0;
1245 host->completed_events = 0;
1246 host->cmd_status = 0;
1247 host->data_status = 0;
1248
1249 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1250
1251 if (host->need_reset || host->caps.need_reset_after_xfer) {
1252 iflags = atmci_readl(host, ATMCI_IMR);
1253 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1254 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1255 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1256 atmci_writel(host, ATMCI_MR, host->mode_reg);
1257 if (host->caps.has_cfg_reg)
1258 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1259 atmci_writel(host, ATMCI_IER, iflags);
1260 host->need_reset = false;
1261 }
1262 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1263
1264 iflags = atmci_readl(host, ATMCI_IMR);
1265 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1266 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1267 iflags);
1268
1269 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1270 /* Send init sequence (74 clock cycles) */
1271 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1272 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1273 cpu_relax();
1274 }
1275 iflags = 0;
1276 data = mrq->data;
1277 if (data) {
1278 atmci_set_timeout(host, slot, data);
1279
1280 /* Must set block count/size before sending command */
1281 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1282 | ATMCI_BLKLEN(data->blksz));
1283 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1284 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1285
1286 iflags |= host->prepare_data(host, data);
1287 }
1288
1289 iflags |= ATMCI_CMDRDY;
1290 cmd = mrq->cmd;
1291 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1292
1293 /*
1294 * DMA transfer should be started before sending the command to avoid
1295 * unexpected errors especially for read operations in SDIO mode.
1296 * Unfortunately, in PDC mode, command has to be sent before starting
1297 * the transfer.
1298 */
1299 if (host->submit_data != &atmci_submit_data_dma)
1300 atmci_send_command(host, cmd, cmdflags);
1301
1302 if (data)
1303 host->submit_data(host, data);
1304
1305 if (host->submit_data == &atmci_submit_data_dma)
1306 atmci_send_command(host, cmd, cmdflags);
1307
1308 if (mrq->stop) {
1309 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1310 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1311 if (!(data->flags & MMC_DATA_WRITE))
1312 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1313 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1314 }
1315
1316 /*
1317 * We could have enabled interrupts earlier, but I suspect
1318 * that would open up a nice can of interesting race
1319 * conditions (e.g. command and data complete, but stop not
1320 * prepared yet.)
1321 */
1322 atmci_writel(host, ATMCI_IER, iflags);
1323 }
1324
1325 static void atmci_queue_request(struct atmel_mci *host,
1326 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1327 {
1328 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1329 host->state);
1330
1331 spin_lock_bh(&host->lock);
1332 slot->mrq = mrq;
1333 if (host->state == STATE_IDLE) {
1334 host->state = STATE_SENDING_CMD;
1335 atmci_start_request(host, slot);
1336 } else {
1337 dev_dbg(&host->pdev->dev, "queue request\n");
1338 list_add_tail(&slot->queue_node, &host->queue);
1339 }
1340 spin_unlock_bh(&host->lock);
1341 }
1342
1343 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1344 {
1345 struct atmel_mci_slot *slot = mmc_priv(mmc);
1346 struct atmel_mci *host = slot->host;
1347 struct mmc_data *data;
1348
1349 WARN_ON(slot->mrq);
1350 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1351
1352 /*
1353 * We may "know" the card is gone even though there's still an
1354 * electrical connection. If so, we really need to communicate
1355 * this to the MMC core since there won't be any more
1356 * interrupts as the card is completely removed. Otherwise,
1357 * the MMC core might believe the card is still there even
1358 * though the card was just removed very slowly.
1359 */
1360 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1361 mrq->cmd->error = -ENOMEDIUM;
1362 mmc_request_done(mmc, mrq);
1363 return;
1364 }
1365
1366 /* We don't support multiple blocks of weird lengths. */
1367 data = mrq->data;
1368 if (data && data->blocks > 1 && data->blksz & 3) {
1369 mrq->cmd->error = -EINVAL;
1370 mmc_request_done(mmc, mrq);
1371 }
1372
1373 atmci_queue_request(host, slot, mrq);
1374 }
1375
1376 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1377 {
1378 struct atmel_mci_slot *slot = mmc_priv(mmc);
1379 struct atmel_mci *host = slot->host;
1380 unsigned int i;
1381
1382 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1383 switch (ios->bus_width) {
1384 case MMC_BUS_WIDTH_1:
1385 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1386 break;
1387 case MMC_BUS_WIDTH_4:
1388 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1389 break;
1390 case MMC_BUS_WIDTH_8:
1391 slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1392 break;
1393 }
1394
1395 if (ios->clock) {
1396 unsigned int clock_min = ~0U;
1397 int clkdiv;
1398
1399 spin_lock_bh(&host->lock);
1400 if (!host->mode_reg) {
1401 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1402 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1403 if (host->caps.has_cfg_reg)
1404 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1405 }
1406
1407 /*
1408 * Use mirror of ios->clock to prevent race with mmc
1409 * core ios update when finding the minimum.
1410 */
1411 slot->clock = ios->clock;
1412 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1413 if (host->slot[i] && host->slot[i]->clock
1414 && host->slot[i]->clock < clock_min)
1415 clock_min = host->slot[i]->clock;
1416 }
1417
1418 /* Calculate clock divider */
1419 if (host->caps.has_odd_clk_div) {
1420 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1421 if (clkdiv < 0) {
1422 dev_warn(&mmc->class_dev,
1423 "clock %u too fast; using %lu\n",
1424 clock_min, host->bus_hz / 2);
1425 clkdiv = 0;
1426 } else if (clkdiv > 511) {
1427 dev_warn(&mmc->class_dev,
1428 "clock %u too slow; using %lu\n",
1429 clock_min, host->bus_hz / (511 + 2));
1430 clkdiv = 511;
1431 }
1432 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1433 | ATMCI_MR_CLKODD(clkdiv & 1);
1434 } else {
1435 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1436 if (clkdiv > 255) {
1437 dev_warn(&mmc->class_dev,
1438 "clock %u too slow; using %lu\n",
1439 clock_min, host->bus_hz / (2 * 256));
1440 clkdiv = 255;
1441 }
1442 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1443 }
1444
1445 /*
1446 * WRPROOF and RDPROOF prevent overruns/underruns by
1447 * stopping the clock when the FIFO is full/empty.
1448 * This state is not expected to last for long.
1449 */
1450 if (host->caps.has_rwproof)
1451 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1452
1453 if (host->caps.has_cfg_reg) {
1454 /* setup High Speed mode in relation with card capacity */
1455 if (ios->timing == MMC_TIMING_SD_HS)
1456 host->cfg_reg |= ATMCI_CFG_HSMODE;
1457 else
1458 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1459 }
1460
1461 if (list_empty(&host->queue)) {
1462 atmci_writel(host, ATMCI_MR, host->mode_reg);
1463 if (host->caps.has_cfg_reg)
1464 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1465 } else {
1466 host->need_clock_update = true;
1467 }
1468
1469 spin_unlock_bh(&host->lock);
1470 } else {
1471 bool any_slot_active = false;
1472
1473 spin_lock_bh(&host->lock);
1474 slot->clock = 0;
1475 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1476 if (host->slot[i] && host->slot[i]->clock) {
1477 any_slot_active = true;
1478 break;
1479 }
1480 }
1481 if (!any_slot_active) {
1482 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1483 if (host->mode_reg) {
1484 atmci_readl(host, ATMCI_MR);
1485 }
1486 host->mode_reg = 0;
1487 }
1488 spin_unlock_bh(&host->lock);
1489 }
1490
1491 switch (ios->power_mode) {
1492 case MMC_POWER_OFF:
1493 if (!IS_ERR(mmc->supply.vmmc))
1494 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1495 break;
1496 case MMC_POWER_UP:
1497 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1498 if (!IS_ERR(mmc->supply.vmmc))
1499 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1500 break;
1501 default:
1502 break;
1503 }
1504 }
1505
1506 static int atmci_get_ro(struct mmc_host *mmc)
1507 {
1508 int read_only = -ENOSYS;
1509 struct atmel_mci_slot *slot = mmc_priv(mmc);
1510
1511 if (gpio_is_valid(slot->wp_pin)) {
1512 read_only = gpio_get_value(slot->wp_pin);
1513 dev_dbg(&mmc->class_dev, "card is %s\n",
1514 read_only ? "read-only" : "read-write");
1515 }
1516
1517 return read_only;
1518 }
1519
1520 static int atmci_get_cd(struct mmc_host *mmc)
1521 {
1522 int present = -ENOSYS;
1523 struct atmel_mci_slot *slot = mmc_priv(mmc);
1524
1525 if (gpio_is_valid(slot->detect_pin)) {
1526 present = !(gpio_get_value(slot->detect_pin) ^
1527 slot->detect_is_active_high);
1528 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1529 present ? "" : "not ");
1530 }
1531
1532 return present;
1533 }
1534
1535 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1536 {
1537 struct atmel_mci_slot *slot = mmc_priv(mmc);
1538 struct atmel_mci *host = slot->host;
1539
1540 if (enable)
1541 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1542 else
1543 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1544 }
1545
1546 static const struct mmc_host_ops atmci_ops = {
1547 .request = atmci_request,
1548 .set_ios = atmci_set_ios,
1549 .get_ro = atmci_get_ro,
1550 .get_cd = atmci_get_cd,
1551 .enable_sdio_irq = atmci_enable_sdio_irq,
1552 };
1553
1554 /* Called with host->lock held */
1555 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1556 __releases(&host->lock)
1557 __acquires(&host->lock)
1558 {
1559 struct atmel_mci_slot *slot = NULL;
1560 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1561
1562 WARN_ON(host->cmd || host->data);
1563
1564 del_timer(&host->timer);
1565
1566 /*
1567 * Update the MMC clock rate if necessary. This may be
1568 * necessary if set_ios() is called when a different slot is
1569 * busy transferring data.
1570 */
1571 if (host->need_clock_update) {
1572 atmci_writel(host, ATMCI_MR, host->mode_reg);
1573 if (host->caps.has_cfg_reg)
1574 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1575 }
1576
1577 host->cur_slot->mrq = NULL;
1578 host->mrq = NULL;
1579 if (!list_empty(&host->queue)) {
1580 slot = list_entry(host->queue.next,
1581 struct atmel_mci_slot, queue_node);
1582 list_del(&slot->queue_node);
1583 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1584 mmc_hostname(slot->mmc));
1585 host->state = STATE_SENDING_CMD;
1586 atmci_start_request(host, slot);
1587 } else {
1588 dev_vdbg(&host->pdev->dev, "list empty\n");
1589 host->state = STATE_IDLE;
1590 }
1591
1592 spin_unlock(&host->lock);
1593 mmc_request_done(prev_mmc, mrq);
1594 spin_lock(&host->lock);
1595 }
1596
1597 static void atmci_command_complete(struct atmel_mci *host,
1598 struct mmc_command *cmd)
1599 {
1600 u32 status = host->cmd_status;
1601
1602 /* Read the response from the card (up to 16 bytes) */
1603 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1604 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1605 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1606 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1607
1608 if (status & ATMCI_RTOE)
1609 cmd->error = -ETIMEDOUT;
1610 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1611 cmd->error = -EILSEQ;
1612 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1613 cmd->error = -EIO;
1614 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1615 if (host->caps.need_blksz_mul_4) {
1616 cmd->error = -EINVAL;
1617 host->need_reset = 1;
1618 }
1619 } else
1620 cmd->error = 0;
1621 }
1622
1623 static void atmci_detect_change(struct timer_list *t)
1624 {
1625 struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer);
1626 bool present;
1627 bool present_old;
1628
1629 /*
1630 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1631 * freeing the interrupt. We must not re-enable the interrupt
1632 * if it has been freed, and if we're shutting down, it
1633 * doesn't really matter whether the card is present or not.
1634 */
1635 smp_rmb();
1636 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1637 return;
1638
1639 enable_irq(gpio_to_irq(slot->detect_pin));
1640 present = !(gpio_get_value(slot->detect_pin) ^
1641 slot->detect_is_active_high);
1642 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1643
1644 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1645 present, present_old);
1646
1647 if (present != present_old) {
1648 struct atmel_mci *host = slot->host;
1649 struct mmc_request *mrq;
1650
1651 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1652 present ? "inserted" : "removed");
1653
1654 spin_lock(&host->lock);
1655
1656 if (!present)
1657 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1658 else
1659 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1660
1661 /* Clean up queue if present */
1662 mrq = slot->mrq;
1663 if (mrq) {
1664 if (mrq == host->mrq) {
1665 /*
1666 * Reset controller to terminate any ongoing
1667 * commands or data transfers.
1668 */
1669 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1670 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1671 atmci_writel(host, ATMCI_MR, host->mode_reg);
1672 if (host->caps.has_cfg_reg)
1673 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1674
1675 host->data = NULL;
1676 host->cmd = NULL;
1677
1678 switch (host->state) {
1679 case STATE_IDLE:
1680 break;
1681 case STATE_SENDING_CMD:
1682 mrq->cmd->error = -ENOMEDIUM;
1683 if (mrq->data)
1684 host->stop_transfer(host);
1685 break;
1686 case STATE_DATA_XFER:
1687 mrq->data->error = -ENOMEDIUM;
1688 host->stop_transfer(host);
1689 break;
1690 case STATE_WAITING_NOTBUSY:
1691 mrq->data->error = -ENOMEDIUM;
1692 break;
1693 case STATE_SENDING_STOP:
1694 mrq->stop->error = -ENOMEDIUM;
1695 break;
1696 case STATE_END_REQUEST:
1697 break;
1698 }
1699
1700 atmci_request_end(host, mrq);
1701 } else {
1702 list_del(&slot->queue_node);
1703 mrq->cmd->error = -ENOMEDIUM;
1704 if (mrq->data)
1705 mrq->data->error = -ENOMEDIUM;
1706 if (mrq->stop)
1707 mrq->stop->error = -ENOMEDIUM;
1708
1709 spin_unlock(&host->lock);
1710 mmc_request_done(slot->mmc, mrq);
1711 spin_lock(&host->lock);
1712 }
1713 }
1714 spin_unlock(&host->lock);
1715
1716 mmc_detect_change(slot->mmc, 0);
1717 }
1718 }
1719
1720 static void atmci_tasklet_func(unsigned long priv)
1721 {
1722 struct atmel_mci *host = (struct atmel_mci *)priv;
1723 struct mmc_request *mrq = host->mrq;
1724 struct mmc_data *data = host->data;
1725 enum atmel_mci_state state = host->state;
1726 enum atmel_mci_state prev_state;
1727 u32 status;
1728
1729 spin_lock(&host->lock);
1730
1731 state = host->state;
1732
1733 dev_vdbg(&host->pdev->dev,
1734 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1735 state, host->pending_events, host->completed_events,
1736 atmci_readl(host, ATMCI_IMR));
1737
1738 do {
1739 prev_state = state;
1740 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1741
1742 switch (state) {
1743 case STATE_IDLE:
1744 break;
1745
1746 case STATE_SENDING_CMD:
1747 /*
1748 * Command has been sent, we are waiting for command
1749 * ready. Then we have three next states possible:
1750 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1751 * command needing it or DATA_XFER if there is data.
1752 */
1753 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1754 if (!atmci_test_and_clear_pending(host,
1755 EVENT_CMD_RDY))
1756 break;
1757
1758 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1759 host->cmd = NULL;
1760 atmci_set_completed(host, EVENT_CMD_RDY);
1761 atmci_command_complete(host, mrq->cmd);
1762 if (mrq->data) {
1763 dev_dbg(&host->pdev->dev,
1764 "command with data transfer");
1765 /*
1766 * If there is a command error don't start
1767 * data transfer.
1768 */
1769 if (mrq->cmd->error) {
1770 host->stop_transfer(host);
1771 host->data = NULL;
1772 atmci_writel(host, ATMCI_IDR,
1773 ATMCI_TXRDY | ATMCI_RXRDY
1774 | ATMCI_DATA_ERROR_FLAGS);
1775 state = STATE_END_REQUEST;
1776 } else
1777 state = STATE_DATA_XFER;
1778 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1779 dev_dbg(&host->pdev->dev,
1780 "command response need waiting notbusy");
1781 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1782 state = STATE_WAITING_NOTBUSY;
1783 } else
1784 state = STATE_END_REQUEST;
1785
1786 break;
1787
1788 case STATE_DATA_XFER:
1789 if (atmci_test_and_clear_pending(host,
1790 EVENT_DATA_ERROR)) {
1791 dev_dbg(&host->pdev->dev, "set completed data error\n");
1792 atmci_set_completed(host, EVENT_DATA_ERROR);
1793 state = STATE_END_REQUEST;
1794 break;
1795 }
1796
1797 /*
1798 * A data transfer is in progress. The event expected
1799 * to move to the next state depends of data transfer
1800 * type (PDC or DMA). Once transfer done we can move
1801 * to the next step which is WAITING_NOTBUSY in write
1802 * case and directly SENDING_STOP in read case.
1803 */
1804 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1805 if (!atmci_test_and_clear_pending(host,
1806 EVENT_XFER_COMPLETE))
1807 break;
1808
1809 dev_dbg(&host->pdev->dev,
1810 "(%s) set completed xfer complete\n",
1811 __func__);
1812 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1813
1814 if (host->caps.need_notbusy_for_read_ops ||
1815 (host->data->flags & MMC_DATA_WRITE)) {
1816 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1817 state = STATE_WAITING_NOTBUSY;
1818 } else if (host->mrq->stop) {
1819 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1820 atmci_send_stop_cmd(host, data);
1821 state = STATE_SENDING_STOP;
1822 } else {
1823 host->data = NULL;
1824 data->bytes_xfered = data->blocks * data->blksz;
1825 data->error = 0;
1826 state = STATE_END_REQUEST;
1827 }
1828 break;
1829
1830 case STATE_WAITING_NOTBUSY:
1831 /*
1832 * We can be in the state for two reasons: a command
1833 * requiring waiting not busy signal (stop command
1834 * included) or a write operation. In the latest case,
1835 * we need to send a stop command.
1836 */
1837 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1838 if (!atmci_test_and_clear_pending(host,
1839 EVENT_NOTBUSY))
1840 break;
1841
1842 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1843 atmci_set_completed(host, EVENT_NOTBUSY);
1844
1845 if (host->data) {
1846 /*
1847 * For some commands such as CMD53, even if
1848 * there is data transfer, there is no stop
1849 * command to send.
1850 */
1851 if (host->mrq->stop) {
1852 atmci_writel(host, ATMCI_IER,
1853 ATMCI_CMDRDY);
1854 atmci_send_stop_cmd(host, data);
1855 state = STATE_SENDING_STOP;
1856 } else {
1857 host->data = NULL;
1858 data->bytes_xfered = data->blocks
1859 * data->blksz;
1860 data->error = 0;
1861 state = STATE_END_REQUEST;
1862 }
1863 } else
1864 state = STATE_END_REQUEST;
1865 break;
1866
1867 case STATE_SENDING_STOP:
1868 /*
1869 * In this state, it is important to set host->data to
1870 * NULL (which is tested in the waiting notbusy state)
1871 * in order to go to the end request state instead of
1872 * sending stop again.
1873 */
1874 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1875 if (!atmci_test_and_clear_pending(host,
1876 EVENT_CMD_RDY))
1877 break;
1878
1879 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1880 host->cmd = NULL;
1881 data->bytes_xfered = data->blocks * data->blksz;
1882 data->error = 0;
1883 atmci_command_complete(host, mrq->stop);
1884 if (mrq->stop->error) {
1885 host->stop_transfer(host);
1886 atmci_writel(host, ATMCI_IDR,
1887 ATMCI_TXRDY | ATMCI_RXRDY
1888 | ATMCI_DATA_ERROR_FLAGS);
1889 state = STATE_END_REQUEST;
1890 } else {
1891 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1892 state = STATE_WAITING_NOTBUSY;
1893 }
1894 host->data = NULL;
1895 break;
1896
1897 case STATE_END_REQUEST:
1898 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1899 | ATMCI_DATA_ERROR_FLAGS);
1900 status = host->data_status;
1901 if (unlikely(status)) {
1902 host->stop_transfer(host);
1903 host->data = NULL;
1904 if (data) {
1905 if (status & ATMCI_DTOE) {
1906 data->error = -ETIMEDOUT;
1907 } else if (status & ATMCI_DCRCE) {
1908 data->error = -EILSEQ;
1909 } else {
1910 data->error = -EIO;
1911 }
1912 }
1913 }
1914
1915 atmci_request_end(host, host->mrq);
1916 goto unlock; /* atmci_request_end() sets host->state */
1917 break;
1918 }
1919 } while (state != prev_state);
1920
1921 host->state = state;
1922
1923 unlock:
1924 spin_unlock(&host->lock);
1925 }
1926
1927 static void atmci_read_data_pio(struct atmel_mci *host)
1928 {
1929 struct scatterlist *sg = host->sg;
1930 unsigned int offset = host->pio_offset;
1931 struct mmc_data *data = host->data;
1932 u32 value;
1933 u32 status;
1934 unsigned int nbytes = 0;
1935
1936 do {
1937 value = atmci_readl(host, ATMCI_RDR);
1938 if (likely(offset + 4 <= sg->length)) {
1939 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1940
1941 offset += 4;
1942 nbytes += 4;
1943
1944 if (offset == sg->length) {
1945 flush_dcache_page(sg_page(sg));
1946 host->sg = sg = sg_next(sg);
1947 host->sg_len--;
1948 if (!sg || !host->sg_len)
1949 goto done;
1950
1951 offset = 0;
1952 }
1953 } else {
1954 unsigned int remaining = sg->length - offset;
1955
1956 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1957 nbytes += remaining;
1958
1959 flush_dcache_page(sg_page(sg));
1960 host->sg = sg = sg_next(sg);
1961 host->sg_len--;
1962 if (!sg || !host->sg_len)
1963 goto done;
1964
1965 offset = 4 - remaining;
1966 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
1967 offset, 0);
1968 nbytes += offset;
1969 }
1970
1971 status = atmci_readl(host, ATMCI_SR);
1972 if (status & ATMCI_DATA_ERROR_FLAGS) {
1973 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1974 | ATMCI_DATA_ERROR_FLAGS));
1975 host->data_status = status;
1976 data->bytes_xfered += nbytes;
1977 return;
1978 }
1979 } while (status & ATMCI_RXRDY);
1980
1981 host->pio_offset = offset;
1982 data->bytes_xfered += nbytes;
1983
1984 return;
1985
1986 done:
1987 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1988 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1989 data->bytes_xfered += nbytes;
1990 smp_wmb();
1991 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1992 }
1993
1994 static void atmci_write_data_pio(struct atmel_mci *host)
1995 {
1996 struct scatterlist *sg = host->sg;
1997 unsigned int offset = host->pio_offset;
1998 struct mmc_data *data = host->data;
1999 u32 value;
2000 u32 status;
2001 unsigned int nbytes = 0;
2002
2003 do {
2004 if (likely(offset + 4 <= sg->length)) {
2005 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2006 atmci_writel(host, ATMCI_TDR, value);
2007
2008 offset += 4;
2009 nbytes += 4;
2010 if (offset == sg->length) {
2011 host->sg = sg = sg_next(sg);
2012 host->sg_len--;
2013 if (!sg || !host->sg_len)
2014 goto done;
2015
2016 offset = 0;
2017 }
2018 } else {
2019 unsigned int remaining = sg->length - offset;
2020
2021 value = 0;
2022 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2023 nbytes += remaining;
2024
2025 host->sg = sg = sg_next(sg);
2026 host->sg_len--;
2027 if (!sg || !host->sg_len) {
2028 atmci_writel(host, ATMCI_TDR, value);
2029 goto done;
2030 }
2031
2032 offset = 4 - remaining;
2033 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2034 offset, 0);
2035 atmci_writel(host, ATMCI_TDR, value);
2036 nbytes += offset;
2037 }
2038
2039 status = atmci_readl(host, ATMCI_SR);
2040 if (status & ATMCI_DATA_ERROR_FLAGS) {
2041 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2042 | ATMCI_DATA_ERROR_FLAGS));
2043 host->data_status = status;
2044 data->bytes_xfered += nbytes;
2045 return;
2046 }
2047 } while (status & ATMCI_TXRDY);
2048
2049 host->pio_offset = offset;
2050 data->bytes_xfered += nbytes;
2051
2052 return;
2053
2054 done:
2055 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2056 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2057 data->bytes_xfered += nbytes;
2058 smp_wmb();
2059 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2060 }
2061
2062 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2063 {
2064 int i;
2065
2066 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2067 struct atmel_mci_slot *slot = host->slot[i];
2068 if (slot && (status & slot->sdio_irq)) {
2069 mmc_signal_sdio_irq(slot->mmc);
2070 }
2071 }
2072 }
2073
2074
2075 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2076 {
2077 struct atmel_mci *host = dev_id;
2078 u32 status, mask, pending;
2079 unsigned int pass_count = 0;
2080
2081 do {
2082 status = atmci_readl(host, ATMCI_SR);
2083 mask = atmci_readl(host, ATMCI_IMR);
2084 pending = status & mask;
2085 if (!pending)
2086 break;
2087
2088 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2089 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2090 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2091 | ATMCI_RXRDY | ATMCI_TXRDY
2092 | ATMCI_ENDRX | ATMCI_ENDTX
2093 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2094
2095 host->data_status = status;
2096 dev_dbg(&host->pdev->dev, "set pending data error\n");
2097 smp_wmb();
2098 atmci_set_pending(host, EVENT_DATA_ERROR);
2099 tasklet_schedule(&host->tasklet);
2100 }
2101
2102 if (pending & ATMCI_TXBUFE) {
2103 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2104 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2105 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2106 /*
2107 * We can receive this interruption before having configured
2108 * the second pdc buffer, so we need to reconfigure first and
2109 * second buffers again
2110 */
2111 if (host->data_size) {
2112 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2113 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2114 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2115 } else {
2116 atmci_pdc_complete(host);
2117 }
2118 } else if (pending & ATMCI_ENDTX) {
2119 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2120 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2121
2122 if (host->data_size) {
2123 atmci_pdc_set_single_buf(host,
2124 XFER_TRANSMIT, PDC_SECOND_BUF);
2125 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2126 }
2127 }
2128
2129 if (pending & ATMCI_RXBUFF) {
2130 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2131 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2132 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2133 /*
2134 * We can receive this interruption before having configured
2135 * the second pdc buffer, so we need to reconfigure first and
2136 * second buffers again
2137 */
2138 if (host->data_size) {
2139 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2140 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2141 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2142 } else {
2143 atmci_pdc_complete(host);
2144 }
2145 } else if (pending & ATMCI_ENDRX) {
2146 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2147 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2148
2149 if (host->data_size) {
2150 atmci_pdc_set_single_buf(host,
2151 XFER_RECEIVE, PDC_SECOND_BUF);
2152 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2153 }
2154 }
2155
2156 /*
2157 * First mci IPs, so mainly the ones having pdc, have some
2158 * issues with the notbusy signal. You can't get it after
2159 * data transmission if you have not sent a stop command.
2160 * The appropriate workaround is to use the BLKE signal.
2161 */
2162 if (pending & ATMCI_BLKE) {
2163 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2164 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2165 smp_wmb();
2166 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2167 atmci_set_pending(host, EVENT_NOTBUSY);
2168 tasklet_schedule(&host->tasklet);
2169 }
2170
2171 if (pending & ATMCI_NOTBUSY) {
2172 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2173 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2174 smp_wmb();
2175 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2176 atmci_set_pending(host, EVENT_NOTBUSY);
2177 tasklet_schedule(&host->tasklet);
2178 }
2179
2180 if (pending & ATMCI_RXRDY)
2181 atmci_read_data_pio(host);
2182 if (pending & ATMCI_TXRDY)
2183 atmci_write_data_pio(host);
2184
2185 if (pending & ATMCI_CMDRDY) {
2186 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2187 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2188 host->cmd_status = status;
2189 smp_wmb();
2190 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2191 atmci_set_pending(host, EVENT_CMD_RDY);
2192 tasklet_schedule(&host->tasklet);
2193 }
2194
2195 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2196 atmci_sdio_interrupt(host, status);
2197
2198 } while (pass_count++ < 5);
2199
2200 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2201 }
2202
2203 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2204 {
2205 struct atmel_mci_slot *slot = dev_id;
2206
2207 /*
2208 * Disable interrupts until the pin has stabilized and check
2209 * the state then. Use mod_timer() since we may be in the
2210 * middle of the timer routine when this interrupt triggers.
2211 */
2212 disable_irq_nosync(irq);
2213 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2214
2215 return IRQ_HANDLED;
2216 }
2217
2218 static int atmci_init_slot(struct atmel_mci *host,
2219 struct mci_slot_pdata *slot_data, unsigned int id,
2220 u32 sdc_reg, u32 sdio_irq)
2221 {
2222 struct mmc_host *mmc;
2223 struct atmel_mci_slot *slot;
2224
2225 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2226 if (!mmc)
2227 return -ENOMEM;
2228
2229 slot = mmc_priv(mmc);
2230 slot->mmc = mmc;
2231 slot->host = host;
2232 slot->detect_pin = slot_data->detect_pin;
2233 slot->wp_pin = slot_data->wp_pin;
2234 slot->detect_is_active_high = slot_data->detect_is_active_high;
2235 slot->sdc_reg = sdc_reg;
2236 slot->sdio_irq = sdio_irq;
2237
2238 dev_dbg(&mmc->class_dev,
2239 "slot[%u]: bus_width=%u, detect_pin=%d, "
2240 "detect_is_active_high=%s, wp_pin=%d\n",
2241 id, slot_data->bus_width, slot_data->detect_pin,
2242 slot_data->detect_is_active_high ? "true" : "false",
2243 slot_data->wp_pin);
2244
2245 mmc->ops = &atmci_ops;
2246 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2247 mmc->f_max = host->bus_hz / 2;
2248 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2249 if (sdio_irq)
2250 mmc->caps |= MMC_CAP_SDIO_IRQ;
2251 if (host->caps.has_highspeed)
2252 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2253 /*
2254 * Without the read/write proof capability, it is strongly suggested to
2255 * use only one bit for data to prevent fifo underruns and overruns
2256 * which will corrupt data.
2257 */
2258 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2259 mmc->caps |= MMC_CAP_4_BIT_DATA;
2260 if (slot_data->bus_width >= 8)
2261 mmc->caps |= MMC_CAP_8_BIT_DATA;
2262 }
2263
2264 if (atmci_get_version(host) < 0x200) {
2265 mmc->max_segs = 256;
2266 mmc->max_blk_size = 4095;
2267 mmc->max_blk_count = 256;
2268 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2269 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2270 } else {
2271 mmc->max_segs = 64;
2272 mmc->max_req_size = 32768 * 512;
2273 mmc->max_blk_size = 32768;
2274 mmc->max_blk_count = 512;
2275 }
2276
2277 /* Assume card is present initially */
2278 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2279 if (gpio_is_valid(slot->detect_pin)) {
2280 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2281 "mmc_detect")) {
2282 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2283 slot->detect_pin = -EBUSY;
2284 } else if (gpio_get_value(slot->detect_pin) ^
2285 slot->detect_is_active_high) {
2286 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2287 }
2288 }
2289
2290 if (!gpio_is_valid(slot->detect_pin)) {
2291 if (slot_data->non_removable)
2292 mmc->caps |= MMC_CAP_NONREMOVABLE;
2293 else
2294 mmc->caps |= MMC_CAP_NEEDS_POLL;
2295 }
2296
2297 if (gpio_is_valid(slot->wp_pin)) {
2298 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2299 "mmc_wp")) {
2300 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2301 slot->wp_pin = -EBUSY;
2302 }
2303 }
2304
2305 host->slot[id] = slot;
2306 mmc_regulator_get_supply(mmc);
2307 mmc_add_host(mmc);
2308
2309 if (gpio_is_valid(slot->detect_pin)) {
2310 int ret;
2311
2312 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2313
2314 ret = request_irq(gpio_to_irq(slot->detect_pin),
2315 atmci_detect_interrupt,
2316 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2317 "mmc-detect", slot);
2318 if (ret) {
2319 dev_dbg(&mmc->class_dev,
2320 "could not request IRQ %d for detect pin\n",
2321 gpio_to_irq(slot->detect_pin));
2322 slot->detect_pin = -EBUSY;
2323 }
2324 }
2325
2326 atmci_init_debugfs(slot);
2327
2328 return 0;
2329 }
2330
2331 static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2332 unsigned int id)
2333 {
2334 /* Debugfs stuff is cleaned up by mmc core */
2335
2336 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2337 smp_wmb();
2338
2339 mmc_remove_host(slot->mmc);
2340
2341 if (gpio_is_valid(slot->detect_pin)) {
2342 int pin = slot->detect_pin;
2343
2344 free_irq(gpio_to_irq(pin), slot);
2345 del_timer_sync(&slot->detect_timer);
2346 }
2347
2348 slot->host->slot[id] = NULL;
2349 mmc_free_host(slot->mmc);
2350 }
2351
2352 static int atmci_configure_dma(struct atmel_mci *host)
2353 {
2354 host->dma.chan = dma_request_chan(&host->pdev->dev, "rxtx");
2355
2356 if (PTR_ERR(host->dma.chan) == -ENODEV) {
2357 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2358 dma_cap_mask_t mask;
2359
2360 if (!pdata || !pdata->dma_filter)
2361 return -ENODEV;
2362
2363 dma_cap_zero(mask);
2364 dma_cap_set(DMA_SLAVE, mask);
2365
2366 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2367 pdata->dma_slave);
2368 if (!host->dma.chan)
2369 host->dma.chan = ERR_PTR(-ENODEV);
2370 }
2371
2372 if (IS_ERR(host->dma.chan))
2373 return PTR_ERR(host->dma.chan);
2374
2375 dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2376 dma_chan_name(host->dma.chan));
2377
2378 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2379 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2380 host->dma_conf.src_maxburst = 1;
2381 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2382 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2383 host->dma_conf.dst_maxburst = 1;
2384 host->dma_conf.device_fc = false;
2385
2386 return 0;
2387 }
2388
2389 /*
2390 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2391 * HSMCI provides DMA support and a new config register but no more supports
2392 * PDC.
2393 */
2394 static void atmci_get_cap(struct atmel_mci *host)
2395 {
2396 unsigned int version;
2397
2398 version = atmci_get_version(host);
2399 dev_info(&host->pdev->dev,
2400 "version: 0x%x\n", version);
2401
2402 host->caps.has_dma_conf_reg = 0;
2403 host->caps.has_pdc = 1;
2404 host->caps.has_cfg_reg = 0;
2405 host->caps.has_cstor_reg = 0;
2406 host->caps.has_highspeed = 0;
2407 host->caps.has_rwproof = 0;
2408 host->caps.has_odd_clk_div = 0;
2409 host->caps.has_bad_data_ordering = 1;
2410 host->caps.need_reset_after_xfer = 1;
2411 host->caps.need_blksz_mul_4 = 1;
2412 host->caps.need_notbusy_for_read_ops = 0;
2413
2414 /* keep only major version number */
2415 switch (version & 0xf00) {
2416 case 0x600:
2417 case 0x500:
2418 host->caps.has_odd_clk_div = 1;
2419 /* Fall through */
2420 case 0x400:
2421 case 0x300:
2422 host->caps.has_dma_conf_reg = 1;
2423 host->caps.has_pdc = 0;
2424 host->caps.has_cfg_reg = 1;
2425 host->caps.has_cstor_reg = 1;
2426 host->caps.has_highspeed = 1;
2427 /* Fall through */
2428 case 0x200:
2429 host->caps.has_rwproof = 1;
2430 host->caps.need_blksz_mul_4 = 0;
2431 host->caps.need_notbusy_for_read_ops = 1;
2432 /* Fall through */
2433 case 0x100:
2434 host->caps.has_bad_data_ordering = 0;
2435 host->caps.need_reset_after_xfer = 0;
2436 /* Fall through */
2437 case 0x0:
2438 break;
2439 default:
2440 host->caps.has_pdc = 0;
2441 dev_warn(&host->pdev->dev,
2442 "Unmanaged mci version, set minimum capabilities\n");
2443 break;
2444 }
2445 }
2446
2447 static int atmci_probe(struct platform_device *pdev)
2448 {
2449 struct mci_platform_data *pdata;
2450 struct atmel_mci *host;
2451 struct resource *regs;
2452 unsigned int nr_slots;
2453 int irq;
2454 int ret, i;
2455
2456 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2457 if (!regs)
2458 return -ENXIO;
2459 pdata = pdev->dev.platform_data;
2460 if (!pdata) {
2461 pdata = atmci_of_init(pdev);
2462 if (IS_ERR(pdata)) {
2463 dev_err(&pdev->dev, "platform data not available\n");
2464 return PTR_ERR(pdata);
2465 }
2466 }
2467
2468 irq = platform_get_irq(pdev, 0);
2469 if (irq < 0)
2470 return irq;
2471
2472 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2473 if (!host)
2474 return -ENOMEM;
2475
2476 host->pdev = pdev;
2477 spin_lock_init(&host->lock);
2478 INIT_LIST_HEAD(&host->queue);
2479
2480 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2481 if (IS_ERR(host->mck))
2482 return PTR_ERR(host->mck);
2483
2484 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2485 if (!host->regs)
2486 return -ENOMEM;
2487
2488 ret = clk_prepare_enable(host->mck);
2489 if (ret)
2490 return ret;
2491
2492 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2493 host->bus_hz = clk_get_rate(host->mck);
2494
2495 host->mapbase = regs->start;
2496
2497 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2498
2499 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2500 if (ret) {
2501 clk_disable_unprepare(host->mck);
2502 return ret;
2503 }
2504
2505 /* Get MCI capabilities and set operations according to it */
2506 atmci_get_cap(host);
2507 ret = atmci_configure_dma(host);
2508 if (ret == -EPROBE_DEFER)
2509 goto err_dma_probe_defer;
2510 if (ret == 0) {
2511 host->prepare_data = &atmci_prepare_data_dma;
2512 host->submit_data = &atmci_submit_data_dma;
2513 host->stop_transfer = &atmci_stop_transfer_dma;
2514 } else if (host->caps.has_pdc) {
2515 dev_info(&pdev->dev, "using PDC\n");
2516 host->prepare_data = &atmci_prepare_data_pdc;
2517 host->submit_data = &atmci_submit_data_pdc;
2518 host->stop_transfer = &atmci_stop_transfer_pdc;
2519 } else {
2520 dev_info(&pdev->dev, "using PIO\n");
2521 host->prepare_data = &atmci_prepare_data;
2522 host->submit_data = &atmci_submit_data;
2523 host->stop_transfer = &atmci_stop_transfer;
2524 }
2525
2526 platform_set_drvdata(pdev, host);
2527
2528 timer_setup(&host->timer, atmci_timeout_timer, 0);
2529
2530 pm_runtime_get_noresume(&pdev->dev);
2531 pm_runtime_set_active(&pdev->dev);
2532 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2533 pm_runtime_use_autosuspend(&pdev->dev);
2534 pm_runtime_enable(&pdev->dev);
2535
2536 /* We need at least one slot to succeed */
2537 nr_slots = 0;
2538 ret = -ENODEV;
2539 if (pdata->slot[0].bus_width) {
2540 ret = atmci_init_slot(host, &pdata->slot[0],
2541 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2542 if (!ret) {
2543 nr_slots++;
2544 host->buf_size = host->slot[0]->mmc->max_req_size;
2545 }
2546 }
2547 if (pdata->slot[1].bus_width) {
2548 ret = atmci_init_slot(host, &pdata->slot[1],
2549 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2550 if (!ret) {
2551 nr_slots++;
2552 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2553 host->buf_size =
2554 host->slot[1]->mmc->max_req_size;
2555 }
2556 }
2557
2558 if (!nr_slots) {
2559 dev_err(&pdev->dev, "init failed: no slot defined\n");
2560 goto err_init_slot;
2561 }
2562
2563 if (!host->caps.has_rwproof) {
2564 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2565 &host->buf_phys_addr,
2566 GFP_KERNEL);
2567 if (!host->buffer) {
2568 ret = -ENOMEM;
2569 dev_err(&pdev->dev, "buffer allocation failed\n");
2570 goto err_dma_alloc;
2571 }
2572 }
2573
2574 dev_info(&pdev->dev,
2575 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2576 host->mapbase, irq, nr_slots);
2577
2578 pm_runtime_mark_last_busy(&host->pdev->dev);
2579 pm_runtime_put_autosuspend(&pdev->dev);
2580
2581 return 0;
2582
2583 err_dma_alloc:
2584 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2585 if (host->slot[i])
2586 atmci_cleanup_slot(host->slot[i], i);
2587 }
2588 err_init_slot:
2589 clk_disable_unprepare(host->mck);
2590
2591 pm_runtime_disable(&pdev->dev);
2592 pm_runtime_put_noidle(&pdev->dev);
2593
2594 del_timer_sync(&host->timer);
2595 if (!IS_ERR(host->dma.chan))
2596 dma_release_channel(host->dma.chan);
2597 err_dma_probe_defer:
2598 free_irq(irq, host);
2599 return ret;
2600 }
2601
2602 static int atmci_remove(struct platform_device *pdev)
2603 {
2604 struct atmel_mci *host = platform_get_drvdata(pdev);
2605 unsigned int i;
2606
2607 pm_runtime_get_sync(&pdev->dev);
2608
2609 if (host->buffer)
2610 dma_free_coherent(&pdev->dev, host->buf_size,
2611 host->buffer, host->buf_phys_addr);
2612
2613 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2614 if (host->slot[i])
2615 atmci_cleanup_slot(host->slot[i], i);
2616 }
2617
2618 atmci_writel(host, ATMCI_IDR, ~0UL);
2619 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2620 atmci_readl(host, ATMCI_SR);
2621
2622 del_timer_sync(&host->timer);
2623 if (!IS_ERR(host->dma.chan))
2624 dma_release_channel(host->dma.chan);
2625
2626 free_irq(platform_get_irq(pdev, 0), host);
2627
2628 clk_disable_unprepare(host->mck);
2629
2630 pm_runtime_disable(&pdev->dev);
2631 pm_runtime_put_noidle(&pdev->dev);
2632
2633 return 0;
2634 }
2635
2636 #ifdef CONFIG_PM
2637 static int atmci_runtime_suspend(struct device *dev)
2638 {
2639 struct atmel_mci *host = dev_get_drvdata(dev);
2640
2641 clk_disable_unprepare(host->mck);
2642
2643 pinctrl_pm_select_sleep_state(dev);
2644
2645 return 0;
2646 }
2647
2648 static int atmci_runtime_resume(struct device *dev)
2649 {
2650 struct atmel_mci *host = dev_get_drvdata(dev);
2651
2652 pinctrl_select_default_state(dev);
2653
2654 return clk_prepare_enable(host->mck);
2655 }
2656 #endif
2657
2658 static const struct dev_pm_ops atmci_dev_pm_ops = {
2659 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2660 pm_runtime_force_resume)
2661 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2662 };
2663
2664 static struct platform_driver atmci_driver = {
2665 .probe = atmci_probe,
2666 .remove = atmci_remove,
2667 .driver = {
2668 .name = "atmel_mci",
2669 .of_match_table = of_match_ptr(atmci_dt_ids),
2670 .pm = &atmci_dev_pm_ops,
2671 },
2672 };
2673 module_platform_driver(atmci_driver);
2674
2675 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2676 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2677 MODULE_LICENSE("GPL v2");
John Crispins staging tree