drivers/net/bcmbca/bcm_ethsw_phy_afe.c

   1 /* SPDX-License-Identifier: GPL-2.0+
   2 *  *
   3 *   *  Copyright 2019 Broadcom Ltd.
   4 *    */
   5
   6 #include <common.h>
   7
   8 void phy_adjust_afe(unsigned int phy_id_base, int is_quad)
   9 {
  10         unsigned int phy_id;
  11         unsigned int phy_id_end = is_quad ? (phy_id_base + 4) : (phy_id_base + 1);
  12
  13         for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
  14         {
  15                 //reset phy
  16                 bcm_ethsw_phy_write_reg(phy_id, 0x0, 0x9140);
  17         }
  18         udelay(100);
  19
  20         for( phy_id = phy_id_base; phy_id < phy_id_end; phy_id++ )
  21         {
  22                 //Turn off AOF
  23                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x39, 0x1, 0x0000 );//AFE_TX_CONFIG_0
  24
  25                 //1g AB symmetry Iq
  26                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x3a, 0x2, 0x0BCC );//AFE_TX_CONFIG_1
  27
  28                 //LPF BW
  29                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x39, 0x0, 0x233F );//AFE_TX_IQ_RX_LP
  30
  31                 //RCAL +6LSB to make impedance from 112 to 100ohm
  32                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x3b, 0x0, 0xAD40 );//AFE_TEMPSEN_OTHERS
  33
  34                 //since rcal make R smaller, make master current -4%
  35                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0a, 0x0, 0x091B );//DSP_TAP10
  36
  37                 //From EEE excel config file for Vitesse fix
  38                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0021, 0x0002, 0x87F6 );// rx_on_tune 8 -> 0xf
  39                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0022, 0x0002, 0x017D );// 100tx EEE bandwidth
  40                 bcm_ethsw_phy_write_misc_reg(  phy_id,  0x0026, 0x0002, 0x0015 );// enable ffe zero det for Vitesse interop
  41
  42         }
  43
  44         //Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
  45         bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x10);
  46         //Disable Reset R_CAL/RC_CAL Engine 'CORE_EXPB0
  47         bcm_ethsw_phy_write_exp_reg(phy_id_base, 0xb0, 0x0);
  48
  49         return;
  50
  51 }
  52