drivers/net/bcmbca/lport/ag/BCM6858_A0LPORT_MAB_AG.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3    Copyright (c) 2015 Broadcom Corporation
   4    All Rights Reserved
   5
   6
   7 */
   8
   9 #include "ru.h"
  10
  11 #if RU_INCLUDE_FIELD_DB
  12 /******************************************************************************
  13  * Field: LPORT_MAB_CNTRL_RESERVED0
  14  ******************************************************************************/
  15 const ru_field_rec LPORT_MAB_CNTRL_RESERVED0_FIELD =
  16 {
  17     "RESERVED0",
  18 #if RU_INCLUDE_DESC
  19     "",
  20     "",
  21 #endif
  22     LPORT_MAB_CNTRL_RESERVED0_FIELD_MASK,
  23     0,
  24     LPORT_MAB_CNTRL_RESERVED0_FIELD_WIDTH,
  25     LPORT_MAB_CNTRL_RESERVED0_FIELD_SHIFT,
  26 #if RU_INCLUDE_ACCESS
  27     ru_access_rw
  28 #endif
  29 };
  30
  31 /******************************************************************************
  32  * Field: LPORT_MAB_CNTRL_LINK_DOWN_RST_EN
  33  ******************************************************************************/
  34 const ru_field_rec LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD =
  35 {
  36     "LINK_DOWN_RST_EN",
  37 #if RU_INCLUDE_DESC
  38     "",
  39     "When this bit is set asynchronous RX and TX FIFOs are reset for a port when the link goes down "
  40     "that is when the local fault is detected.",
  41 #endif
  42     LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_MASK,
  43     0,
  44     LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_WIDTH,
  45     LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD_SHIFT,
  46 #if RU_INCLUDE_ACCESS
  47     ru_access_rw
  48 #endif
  49 };
  50
  51 /******************************************************************************
  52  * Field: LPORT_MAB_CNTRL_RESERVED1
  53  ******************************************************************************/
  54 const ru_field_rec LPORT_MAB_CNTRL_RESERVED1_FIELD =
  55 {
  56     "RESERVED1",
  57 #if RU_INCLUDE_DESC
  58     "",
  59     "",
  60 #endif
  61     LPORT_MAB_CNTRL_RESERVED1_FIELD_MASK,
  62     0,
  63     LPORT_MAB_CNTRL_RESERVED1_FIELD_WIDTH,
  64     LPORT_MAB_CNTRL_RESERVED1_FIELD_SHIFT,
  65 #if RU_INCLUDE_ACCESS
  66     ru_access_rw
  67 #endif
  68 };
  69
  70 /******************************************************************************
  71  * Field: LPORT_MAB_CNTRL_XGMII_TX_RST
  72  ******************************************************************************/
  73 const ru_field_rec LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD =
  74 {
  75     "XGMII_TX_RST",
  76 #if RU_INCLUDE_DESC
  77     "",
  78     "When set resets 10G Port 0 asynchronous TX FIFO and associated logic (such as credit logic).",
  79 #endif
  80     LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_MASK,
  81     0,
  82     LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_WIDTH,
  83     LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD_SHIFT,
  84 #if RU_INCLUDE_ACCESS
  85     ru_access_rw
  86 #endif
  87 };
  88
  89 /******************************************************************************
  90  * Field: LPORT_MAB_CNTRL_GMII_TX_RST
  91  ******************************************************************************/
  92 const ru_field_rec LPORT_MAB_CNTRL_GMII_TX_RST_FIELD =
  93 {
  94     "GMII_TX_RST",
  95 #if RU_INCLUDE_DESC
  96     "",
  97     "When a bit in this vector is set it resets corresponding port (Port 3-0) asynchronous TX FIFO "
  98     "and associated logic (such as credit logic and byte slicers).",
  99 #endif
 100     LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_MASK,
 101     0,
 102     LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_WIDTH,
 103     LPORT_MAB_CNTRL_GMII_TX_RST_FIELD_SHIFT,
 104 #if RU_INCLUDE_ACCESS
 105     ru_access_rw
 106 #endif
 107 };
 108
 109 /******************************************************************************
 110  * Field: LPORT_MAB_CNTRL_RESERVED2
 111  ******************************************************************************/
 112 const ru_field_rec LPORT_MAB_CNTRL_RESERVED2_FIELD =
 113 {
 114     "RESERVED2",
 115 #if RU_INCLUDE_DESC
 116     "",
 117     "",
 118 #endif
 119     LPORT_MAB_CNTRL_RESERVED2_FIELD_MASK,
 120     0,
 121     LPORT_MAB_CNTRL_RESERVED2_FIELD_WIDTH,
 122     LPORT_MAB_CNTRL_RESERVED2_FIELD_SHIFT,
 123 #if RU_INCLUDE_ACCESS
 124     ru_access_rw
 125 #endif
 126 };
 127
 128 /******************************************************************************
 129  * Field: LPORT_MAB_CNTRL_XGMII_RX_RST
 130  ******************************************************************************/
 131 const ru_field_rec LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD =
 132 {
 133     "XGMII_RX_RST",
 134 #if RU_INCLUDE_DESC
 135     "",
 136     "When set resets 10G Port 0 asynchronous RX FIFO and associated logic.",
 137 #endif
 138     LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_MASK,
 139     0,
 140     LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_WIDTH,
 141     LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD_SHIFT,
 142 #if RU_INCLUDE_ACCESS
 143     ru_access_rw
 144 #endif
 145 };
 146
 147 /******************************************************************************
 148  * Field: LPORT_MAB_CNTRL_GMII_RX_RST
 149  ******************************************************************************/
 150 const ru_field_rec LPORT_MAB_CNTRL_GMII_RX_RST_FIELD =
 151 {
 152     "GMII_RX_RST",
 153 #if RU_INCLUDE_DESC
 154     "",
 155     "When a bit in this vector is set it resets corresponding port (Port 3-0) asynchronous RX FIFO "
 156     "and associated logic (such as byte packers).",
 157 #endif
 158     LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_MASK,
 159     0,
 160     LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_WIDTH,
 161     LPORT_MAB_CNTRL_GMII_RX_RST_FIELD_SHIFT,
 162 #if RU_INCLUDE_ACCESS
 163     ru_access_rw
 164 #endif
 165 };
 166
 167 /******************************************************************************
 168  * Field: LPORT_MAB_TX_WRR_CTRL_RESERVED0
 169  ******************************************************************************/
 170 const ru_field_rec LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD =
 171 {
 172     "RESERVED0",
 173 #if RU_INCLUDE_DESC
 174     "",
 175     "",
 176 #endif
 177     LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_MASK,
 178     0,
 179     LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_WIDTH,
 180     LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD_SHIFT,
 181 #if RU_INCLUDE_ACCESS
 182     ru_access_rw
 183 #endif
 184 };
 185
 186 /******************************************************************************
 187  * Field: LPORT_MAB_TX_WRR_CTRL_ARB_MODE
 188  ******************************************************************************/
 189 const ru_field_rec LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD =
 190 {
 191     "ARB_MODE",
 192 #if RU_INCLUDE_DESC
 193     "",
 194     "Arbiter Mode\n"
 195     "1'b0 - Fixed Mode. TDM slots allocated regardless of the port activity.\n"
 196     "1'b1 - Work-Conserving Mode. TDM slots allocation is affected by the port activity.",
 197 #endif
 198     LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_MASK,
 199     0,
 200     LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_WIDTH,
 201     LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD_SHIFT,
 202 #if RU_INCLUDE_ACCESS
 203     ru_access_rw
 204 #endif
 205 };
 206
 207 /******************************************************************************
 208  * Field: LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT
 209  ******************************************************************************/
 210 const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD =
 211 {
 212     "P7_WEIGHT",
 213 #if RU_INCLUDE_DESC
 214     "",
 215     "P7 weight expressed in TDM time slots.",
 216 #endif
 217     LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_MASK,
 218     0,
 219     LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_WIDTH,
 220     LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD_SHIFT,
 221 #if RU_INCLUDE_ACCESS
 222     ru_access_rw
 223 #endif
 224 };
 225
 226 /******************************************************************************
 227  * Field: LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT
 228  ******************************************************************************/
 229 const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD =
 230 {
 231     "P6_WEIGHT",
 232 #if RU_INCLUDE_DESC
 233     "",
 234     "P6 weight expressed in TDM time slots.",
 235 #endif
 236     LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_MASK,
 237     0,
 238     LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_WIDTH,
 239     LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD_SHIFT,
 240 #if RU_INCLUDE_ACCESS
 241     ru_access_rw
 242 #endif
 243 };
 244
 245 /******************************************************************************
 246  * Field: LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT
 247  ******************************************************************************/
 248 const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD =
 249 {
 250     "P5_WEIGHT",
 251 #if RU_INCLUDE_DESC
 252     "",
 253     "P5 weight expressed in TDM time slots.",
 254 #endif
 255     LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_MASK,
 256     0,
 257     LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_WIDTH,
 258     LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD_SHIFT,
 259 #if RU_INCLUDE_ACCESS
 260     ru_access_rw
 261 #endif
 262 };
 263
 264 /******************************************************************************
 265  * Field: LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT
 266  ******************************************************************************/
 267 const ru_field_rec LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD =
 268 {
 269     "P4_WEIGHT",
 270 #if RU_INCLUDE_DESC
 271     "",
 272     "P4 weight expressed in TDM time slots.\n"
 273     "Allocated port bandwidth is equal to TOTAL_BW*(Px_WEIGHT/SUM(P4_WEIGHT,...,P7_WEIGHT) (where TOTAL_BW is 25.6Gb/as for 400MHz MSBUS clock).",
 274 #endif
 275     LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_MASK,
 276     0,
 277     LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_WIDTH,
 278     LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD_SHIFT,
 279 #if RU_INCLUDE_ACCESS
 280     ru_access_rw
 281 #endif
 282 };
 283
 284 /******************************************************************************
 285  * Field: LPORT_MAB_TX_THRESHOLD_RESERVED0
 286  ******************************************************************************/
 287 const ru_field_rec LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD =
 288 {
 289     "RESERVED0",
 290 #if RU_INCLUDE_DESC
 291     "",
 292     "",
 293 #endif
 294     LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_MASK,
 295     0,
 296     LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_WIDTH,
 297     LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD_SHIFT,
 298 #if RU_INCLUDE_ACCESS
 299     ru_access_rw
 300 #endif
 301 };
 302
 303 /******************************************************************************
 304  * Field: LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD
 305  ******************************************************************************/
 306 const ru_field_rec LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD =
 307 {
 308     "XGMII1_TX_THRESHOLD",
 309 #if RU_INCLUDE_DESC
 310     "",
 311     "XGMII1 (P4) asynchronous TX FIFO read depth at which packet dequeue starts.",
 312 #endif
 313     LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_MASK,
 314     0,
 315     LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_WIDTH,
 316     LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD_SHIFT,
 317 #if RU_INCLUDE_ACCESS
 318     ru_access_rw
 319 #endif
 320 };
 321
 322 /******************************************************************************
 323  * Field: LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD
 324  ******************************************************************************/
 325 const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD =
 326 {
 327     "GMII7_TX_THRESHOLD",
 328 #if RU_INCLUDE_DESC
 329     "",
 330     "GMII P7 asynchronous TX FIFO read depth at which packet dequeue starts.",
 331 #endif
 332     LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_MASK,
 333     0,
 334     LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_WIDTH,
 335     LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD_SHIFT,
 336 #if RU_INCLUDE_ACCESS
 337     ru_access_rw
 338 #endif
 339 };
 340
 341 /******************************************************************************
 342  * Field: LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD
 343  ******************************************************************************/
 344 const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD =
 345 {
 346     "GMII6_TX_THRESHOLD",
 347 #if RU_INCLUDE_DESC
 348     "",
 349     "GMII P6 asynchronous TX FIFO read depth at which packet dequeue starts.",
 350 #endif
 351     LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_MASK,
 352     0,
 353     LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_WIDTH,
 354     LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD_SHIFT,
 355 #if RU_INCLUDE_ACCESS
 356     ru_access_rw
 357 #endif
 358 };
 359
 360 /******************************************************************************
 361  * Field: LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD
 362  ******************************************************************************/
 363 const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD =
 364 {
 365     "GMII5_TX_THRESHOLD",
 366 #if RU_INCLUDE_DESC
 367     "",
 368     "GMII P5 asynchronous TX FIFO read depth at which packet dequeue starts.",
 369 #endif
 370     LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_MASK,
 371     0,
 372     LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_WIDTH,
 373     LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD_SHIFT,
 374 #if RU_INCLUDE_ACCESS
 375     ru_access_rw
 376 #endif
 377 };
 378
 379 /******************************************************************************
 380  * Field: LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD
 381  ******************************************************************************/
 382 const ru_field_rec LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD =
 383 {
 384     "GMII4_TX_THRESHOLD",
 385 #if RU_INCLUDE_DESC
 386     "",
 387     "GMII P4 asynchronous TX FIFO read depth at which packet dequeue starts.",
 388 #endif
 389     LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_MASK,
 390     0,
 391     LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_WIDTH,
 392     LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD_SHIFT,
 393 #if RU_INCLUDE_ACCESS
 394     ru_access_rw
 395 #endif
 396 };
 397
 398 /******************************************************************************
 399  * Field: LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0
 400  ******************************************************************************/
 401 const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD =
 402 {
 403     "RESERVED0",
 404 #if RU_INCLUDE_DESC
 405     "",
 406     "",
 407 #endif
 408     LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_MASK,
 409     0,
 410     LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_WIDTH,
 411     LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD_SHIFT,
 412 #if RU_INCLUDE_ACCESS
 413     ru_access_rw
 414 #endif
 415 };
 416
 417 /******************************************************************************
 418  * Field: LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL
 419  ******************************************************************************/
 420 const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD =
 421 {
 422     "TXCTL",
 423 #if RU_INCLUDE_DESC
 424     "",
 425     "When LINK_DOWN_RST_EN = 1 and link is down content of this register is sent to serdes over XGMII interface. "
 426     " In GMII mode 0 is sent.",
 427 #endif
 428     LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_MASK,
 429     0,
 430     LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_WIDTH,
 431     LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD_SHIFT,
 432 #if RU_INCLUDE_ACCESS
 433     ru_access_rw
 434 #endif
 435 };
 436
 437 /******************************************************************************
 438  * Field: LPORT_MAB_LINK_DOWN_TX_DATA_TXD
 439  ******************************************************************************/
 440 const ru_field_rec LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD =
 441 {
 442     "TXD",
 443 #if RU_INCLUDE_DESC
 444     "",
 445     "When LINK_DOWN_RST_EN = 1 and link is down content of this register is sent to serdes over XGMII interface. "
 446     "In GMII mode 0's are sent.",
 447 #endif
 448     LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_MASK,
 449     0,
 450     LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_WIDTH,
 451     LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD_SHIFT,
 452 #if RU_INCLUDE_ACCESS
 453     ru_access_rw
 454 #endif
 455 };
 456
 457 /******************************************************************************
 458  * Field: LPORT_MAB_STATUS_RESERVED0
 459  ******************************************************************************/
 460 const ru_field_rec LPORT_MAB_STATUS_RESERVED0_FIELD =
 461 {
 462     "RESERVED0",
 463 #if RU_INCLUDE_DESC
 464     "",
 465     "",
 466 #endif
 467     LPORT_MAB_STATUS_RESERVED0_FIELD_MASK,
 468     0,
 469     LPORT_MAB_STATUS_RESERVED0_FIELD_WIDTH,
 470     LPORT_MAB_STATUS_RESERVED0_FIELD_SHIFT,
 471 #if RU_INCLUDE_ACCESS
 472     ru_access_read
 473 #endif
 474 };
 475
 476 /******************************************************************************
 477  * Field: LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN
 478  ******************************************************************************/
 479 const ru_field_rec LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD =
 480 {
 481     "XGMII_RX_AFIFO_OVERRUN",
 482 #if RU_INCLUDE_DESC
 483     "",
 484     "10G Port 0 asynchronous RX FIFO over-run status.",
 485 #endif
 486     LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_MASK,
 487     0,
 488     LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_WIDTH,
 489     LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD_SHIFT,
 490 #if RU_INCLUDE_ACCESS
 491     ru_access_read
 492 #endif
 493 };
 494
 495 /******************************************************************************
 496  * Field: LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT
 497  ******************************************************************************/
 498 const ru_field_rec LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD =
 499 {
 500     "GMII_RX_AFIFO_OVERRUN_VECT",
 501 #if RU_INCLUDE_DESC
 502     "",
 503     "Port 3-0 asynchronous RX FIFO over-run status.",
 504 #endif
 505     LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_MASK,
 506     0,
 507     LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_WIDTH,
 508     LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD_SHIFT,
 509 #if RU_INCLUDE_ACCESS
 510     ru_access_read
 511 #endif
 512 };
 513
 514 /******************************************************************************
 515  * Field: LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN
 516  ******************************************************************************/
 517 const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD =
 518 {
 519     "XGMII_TX_FRM_UNDERRUN",
 520 #if RU_INCLUDE_DESC
 521     "",
 522     "10G Port 0 TX frame under-run status.",
 523 #endif
 524     LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_MASK,
 525     0,
 526     LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_WIDTH,
 527     LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD_SHIFT,
 528 #if RU_INCLUDE_ACCESS
 529     ru_access_read
 530 #endif
 531 };
 532
 533 /******************************************************************************
 534  * Field: LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN
 535  ******************************************************************************/
 536 const ru_field_rec LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD =
 537 {
 538     "XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN",
 539 #if RU_INCLUDE_DESC
 540     "",
 541     "10G Port 0 TX credits under-run status.",
 542 #endif
 543     LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_MASK,
 544     0,
 545     LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_WIDTH,
 546     LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD_SHIFT,
 547 #if RU_INCLUDE_ACCESS
 548     ru_access_read
 549 #endif
 550 };
 551
 552 /******************************************************************************
 553  * Field: LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT
 554  ******************************************************************************/
 555 const ru_field_rec LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD =
 556 {
 557     "GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT",
 558 #if RU_INCLUDE_DESC
 559     "",
 560     "Port 3-0 TX credits under-run status.",
 561 #endif
 562     LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_MASK,
 563     0,
 564     LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_WIDTH,
 565     LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD_SHIFT,
 566 #if RU_INCLUDE_ACCESS
 567     ru_access_read
 568 #endif
 569 };
 570
 571 /******************************************************************************
 572  * Field: LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN
 573  ******************************************************************************/
 574 const ru_field_rec LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD =
 575 {
 576     "XGMII_TX_AFIFO_OVERRUN",
 577 #if RU_INCLUDE_DESC
 578     "",
 579     "10G Port 0 asynchronous TX FIFO over-run status.",
 580 #endif
 581     LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_MASK,
 582     0,
 583     LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_WIDTH,
 584     LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD_SHIFT,
 585 #if RU_INCLUDE_ACCESS
 586     ru_access_read
 587 #endif
 588 };
 589
 590 /******************************************************************************
 591  * Field: LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT
 592  ******************************************************************************/
 593 const ru_field_rec LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD =
 594 {
 595     "GMII_TX_AFIFO_OVERRUN_VECT",
 596 #if RU_INCLUDE_DESC
 597     "",
 598     "Port 3-0 asynchronous TX FIFO over-run status.",
 599 #endif
 600     LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_MASK,
 601     0,
 602     LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_WIDTH,
 603     LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD_SHIFT,
 604 #if RU_INCLUDE_ACCESS
 605     ru_access_read
 606 #endif
 607 };
 608
 609 #endif /* RU_INCLUDE_FIELD_DB */
 610
 611 /******************************************************************************
 612  * Register: LPORT_MAB_CNTRL
 613  ******************************************************************************/
 614 #if RU_INCLUDE_FIELD_DB
 615 static const ru_field_rec *LPORT_MAB_CNTRL_FIELDS[] =
 616 {
 617     &LPORT_MAB_CNTRL_RESERVED0_FIELD,
 618     &LPORT_MAB_CNTRL_LINK_DOWN_RST_EN_FIELD,
 619     &LPORT_MAB_CNTRL_RESERVED1_FIELD,
 620     &LPORT_MAB_CNTRL_XGMII_TX_RST_FIELD,
 621     &LPORT_MAB_CNTRL_GMII_TX_RST_FIELD,
 622     &LPORT_MAB_CNTRL_RESERVED2_FIELD,
 623     &LPORT_MAB_CNTRL_XGMII_RX_RST_FIELD,
 624     &LPORT_MAB_CNTRL_GMII_RX_RST_FIELD,
 625 };
 626
 627 #endif /* RU_INCLUDE_FIELD_DB */
 628
 629 const ru_reg_rec LPORT_MAB_CNTRL_REG =
 630 {
 631     "CNTRL",
 632 #if RU_INCLUDE_DESC
 633     "MSBUS 1 Adaptation Control Register",
 634     "",
 635 #endif
 636     LPORT_MAB_CNTRL_REG_OFFSET,
 637     0,
 638     0,
 639     295,
 640 #if RU_INCLUDE_ACCESS
 641     ru_access_rw,
 642 #endif
 643 #if RU_INCLUDE_FIELD_DB
 644     8,
 645     LPORT_MAB_CNTRL_FIELDS,
 646 #endif /* RU_INCLUDE_FIELD_DB */
 647     ru_reg_size_32
 648 };
 649
 650 /******************************************************************************
 651  * Register: LPORT_MAB_TX_WRR_CTRL
 652  ******************************************************************************/
 653 #if RU_INCLUDE_FIELD_DB
 654 static const ru_field_rec *LPORT_MAB_TX_WRR_CTRL_FIELDS[] =
 655 {
 656     &LPORT_MAB_TX_WRR_CTRL_RESERVED0_FIELD,
 657     &LPORT_MAB_TX_WRR_CTRL_ARB_MODE_FIELD,
 658     &LPORT_MAB_TX_WRR_CTRL_P7_WEIGHT_FIELD,
 659     &LPORT_MAB_TX_WRR_CTRL_P6_WEIGHT_FIELD,
 660     &LPORT_MAB_TX_WRR_CTRL_P5_WEIGHT_FIELD,
 661     &LPORT_MAB_TX_WRR_CTRL_P4_WEIGHT_FIELD,
 662 };
 663
 664 #endif /* RU_INCLUDE_FIELD_DB */
 665
 666 const ru_reg_rec LPORT_MAB_TX_WRR_CTRL_REG =
 667 {
 668     "TX_WRR_CTRL",
 669 #if RU_INCLUDE_DESC
 670     "MSBUS 1 Adaptation TX WRR Control Register",
 671     "",
 672 #endif
 673     LPORT_MAB_TX_WRR_CTRL_REG_OFFSET,
 674     0,
 675     0,
 676     296,
 677 #if RU_INCLUDE_ACCESS
 678     ru_access_rw,
 679 #endif
 680 #if RU_INCLUDE_FIELD_DB
 681     6,
 682     LPORT_MAB_TX_WRR_CTRL_FIELDS,
 683 #endif /* RU_INCLUDE_FIELD_DB */
 684     ru_reg_size_32
 685 };
 686
 687 /******************************************************************************
 688  * Register: LPORT_MAB_TX_THRESHOLD
 689  ******************************************************************************/
 690 #if RU_INCLUDE_FIELD_DB
 691 static const ru_field_rec *LPORT_MAB_TX_THRESHOLD_FIELDS[] =
 692 {
 693     &LPORT_MAB_TX_THRESHOLD_RESERVED0_FIELD,
 694     &LPORT_MAB_TX_THRESHOLD_XGMII1_TX_THRESHOLD_FIELD,
 695     &LPORT_MAB_TX_THRESHOLD_GMII7_TX_THRESHOLD_FIELD,
 696     &LPORT_MAB_TX_THRESHOLD_GMII6_TX_THRESHOLD_FIELD,
 697     &LPORT_MAB_TX_THRESHOLD_GMII5_TX_THRESHOLD_FIELD,
 698     &LPORT_MAB_TX_THRESHOLD_GMII4_TX_THRESHOLD_FIELD,
 699 };
 700
 701 #endif /* RU_INCLUDE_FIELD_DB */
 702
 703 const ru_reg_rec LPORT_MAB_TX_THRESHOLD_REG =
 704 {
 705     "TX_THRESHOLD",
 706 #if RU_INCLUDE_DESC
 707     "MSBUS 1 Adaptation TX Threshold Register",
 708     "",
 709 #endif
 710     LPORT_MAB_TX_THRESHOLD_REG_OFFSET,
 711     0,
 712     0,
 713     297,
 714 #if RU_INCLUDE_ACCESS
 715     ru_access_rw,
 716 #endif
 717 #if RU_INCLUDE_FIELD_DB
 718     6,
 719     LPORT_MAB_TX_THRESHOLD_FIELDS,
 720 #endif /* RU_INCLUDE_FIELD_DB */
 721     ru_reg_size_32
 722 };
 723
 724 /******************************************************************************
 725  * Register: LPORT_MAB_LINK_DOWN_TX_DATA
 726  ******************************************************************************/
 727 #if RU_INCLUDE_FIELD_DB
 728 static const ru_field_rec *LPORT_MAB_LINK_DOWN_TX_DATA_FIELDS[] =
 729 {
 730     &LPORT_MAB_LINK_DOWN_TX_DATA_RESERVED0_FIELD,
 731     &LPORT_MAB_LINK_DOWN_TX_DATA_TXCTL_FIELD,
 732     &LPORT_MAB_LINK_DOWN_TX_DATA_TXD_FIELD,
 733 };
 734
 735 #endif /* RU_INCLUDE_FIELD_DB */
 736
 737 const ru_reg_rec LPORT_MAB_LINK_DOWN_TX_DATA_REG =
 738 {
 739     "LINK_DOWN_TX_DATA",
 740 #if RU_INCLUDE_DESC
 741     "MSBUS 1 Adaptation Link down TX Data Register",
 742     "",
 743 #endif
 744     LPORT_MAB_LINK_DOWN_TX_DATA_REG_OFFSET,
 745     0,
 746     0,
 747     298,
 748 #if RU_INCLUDE_ACCESS
 749     ru_access_rw,
 750 #endif
 751 #if RU_INCLUDE_FIELD_DB
 752     3,
 753     LPORT_MAB_LINK_DOWN_TX_DATA_FIELDS,
 754 #endif /* RU_INCLUDE_FIELD_DB */
 755     ru_reg_size_32
 756 };
 757
 758 /******************************************************************************
 759  * Register: LPORT_MAB_STATUS
 760  ******************************************************************************/
 761 #if RU_INCLUDE_FIELD_DB
 762 static const ru_field_rec *LPORT_MAB_STATUS_FIELDS[] =
 763 {
 764     &LPORT_MAB_STATUS_RESERVED0_FIELD,
 765     &LPORT_MAB_STATUS_XGMII_RX_AFIFO_OVERRUN_FIELD,
 766     &LPORT_MAB_STATUS_GMII_RX_AFIFO_OVERRUN_VECT_FIELD,
 767     &LPORT_MAB_STATUS_XGMII_TX_FRM_UNDERRUN_FIELD,
 768     &LPORT_MAB_STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_FIELD,
 769     &LPORT_MAB_STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_FIELD,
 770     &LPORT_MAB_STATUS_XGMII_TX_AFIFO_OVERRUN_FIELD,
 771     &LPORT_MAB_STATUS_GMII_TX_AFIFO_OVERRUN_VECT_FIELD,
 772 };
 773
 774 #endif /* RU_INCLUDE_FIELD_DB */
 775
 776 const ru_reg_rec LPORT_MAB_STATUS_REG =
 777 {
 778     "STATUS",
 779 #if RU_INCLUDE_DESC
 780     "MSBUS 1 Adaptation Status Register",
 781     "",
 782 #endif
 783     LPORT_MAB_STATUS_REG_OFFSET,
 784     0,
 785     0,
 786     299,
 787 #if RU_INCLUDE_ACCESS
 788     ru_access_read,
 789 #endif
 790 #if RU_INCLUDE_FIELD_DB
 791     8,
 792     LPORT_MAB_STATUS_FIELDS,
 793 #endif /* RU_INCLUDE_FIELD_DB */
 794     ru_reg_size_32
 795 };
 796
 797 /******************************************************************************
 798  * Block: LPORT_MAB
 799  ******************************************************************************/
 800 static const ru_reg_rec *LPORT_MAB_REGS[] =
 801 {
 802     &LPORT_MAB_CNTRL_REG,
 803     &LPORT_MAB_TX_WRR_CTRL_REG,
 804     &LPORT_MAB_TX_THRESHOLD_REG,
 805     &LPORT_MAB_LINK_DOWN_TX_DATA_REG,
 806     &LPORT_MAB_STATUS_REG,
 807 };
 808
 809 unsigned long LPORT_MAB_ADDRS[] =
 810 {
 811     0x8013d700,
 812     0x8013d800,
 813 };
 814
 815 const ru_block_rec LPORT_MAB_BLOCK =
 816 {
 817     "LPORT_MAB",
 818     LPORT_MAB_ADDRS,
 819     2,
 820     5,
 821     LPORT_MAB_REGS
 822 };
 823
 824 /* End of file BCM6858_A0LPORT_MAB.c */