1 // SPDX-License-Identifier: GPL-2.0+
3 Copyright (c) 2015 Broadcom Corporation
9 #ifndef _BCM6858_LPORT_RGMII_AG_H_
10 #define _BCM6858_LPORT_RGMII_AG_H_
12 #include "access_macros.h"
19 uint8_t tx_clk_stop_en
;
22 uint8_t rvmii_ref_sel
;
25 uint8_t rgmii_mode_en
;
37 } lport_rgmii_rx_clock_delay_cntrl
;
42 uint8_t pkt_count_rst
;
44 uint16_t expected_data_1
;
45 uint16_t expected_data_0
;
46 } lport_rgmii_ate_rx_cntrl_exp_data
;
51 uint16_t payload_length
;
55 uint8_t start_stop_ovrd
;
56 } lport_rgmii_ate_tx_cntrl
;
60 uint8_t txd3_del_ovrd_en
;
62 uint8_t txd2_del_ovrd_en
;
64 uint8_t txd1_del_ovrd_en
;
66 uint8_t txd0_del_ovrd_en
;
68 } lport_rgmii_tx_delay_cntrl_0
;
72 uint8_t txclk_id_del_ovrd_en
;
73 uint8_t txclk_id_del_sel
;
74 uint8_t txclk_del_ovrd_en
;
75 uint8_t txclk_del_sel
;
76 uint8_t txctl_del_ovrd_en
;
77 uint8_t txctl_del_sel
;
78 } lport_rgmii_tx_delay_cntrl_1
;
82 uint8_t rxd3_del_ovrd_en
;
84 uint8_t rxd2_del_ovrd_en
;
86 uint8_t rxd1_del_ovrd_en
;
88 uint8_t rxd0_del_ovrd_en
;
90 } lport_rgmii_rx_delay_cntrl_0
;
94 uint8_t rxd7_del_ovrd_en
;
96 uint8_t rxd6_del_ovrd_en
;
98 uint8_t rxd5_del_ovrd_en
;
100 uint8_t rxd4_del_ovrd_en
;
101 uint8_t rxd4_del_sel
;
102 } lport_rgmii_rx_delay_cntrl_1
;
106 uint8_t rxclk_del_ovrd_en
;
107 uint8_t rxclk_del_sel
;
108 uint8_t rxctl_neg_del_ovrd_en
;
109 uint8_t rxctl_neg_del_sel
;
110 uint8_t rxctl_pos_del_ovrd_en
;
111 uint8_t rxctl_pos_del_sel
;
112 } lport_rgmii_rx_delay_cntrl_2
;
114 int ag_drv_lport_rgmii_cntrl_set(uint8_t rgmii_id
, const lport_rgmii_cntrl
*cntrl
);
115 int ag_drv_lport_rgmii_cntrl_get(uint8_t rgmii_id
, lport_rgmii_cntrl
*cntrl
);
116 int ag_drv_lport_rgmii_ib_status_set(uint8_t rgmii_id
, uint8_t ib_status_ovrd
, uint8_t link_decode
, uint8_t duplex_decode
, uint8_t speed_decode
);
117 int ag_drv_lport_rgmii_ib_status_get(uint8_t rgmii_id
, uint8_t *ib_status_ovrd
, uint8_t *link_decode
, uint8_t *duplex_decode
, uint8_t *speed_decode
);
118 int ag_drv_lport_rgmii_rx_clock_delay_cntrl_set(uint8_t rgmii_id
, const lport_rgmii_rx_clock_delay_cntrl
*rx_clock_delay_cntrl
);
119 int ag_drv_lport_rgmii_rx_clock_delay_cntrl_get(uint8_t rgmii_id
, lport_rgmii_rx_clock_delay_cntrl
*rx_clock_delay_cntrl
);
120 int ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_set(uint8_t rgmii_id
, const lport_rgmii_ate_rx_cntrl_exp_data
*ate_rx_cntrl_exp_data
);
121 int ag_drv_lport_rgmii_ate_rx_cntrl_exp_data_get(uint8_t rgmii_id
, lport_rgmii_ate_rx_cntrl_exp_data
*ate_rx_cntrl_exp_data
);
122 int ag_drv_lport_rgmii_ate_rx_exp_data_1_set(uint8_t rgmii_id
, uint16_t expected_data_3
, uint16_t expected_data_2
);
123 int ag_drv_lport_rgmii_ate_rx_exp_data_1_get(uint8_t rgmii_id
, uint16_t *expected_data_3
, uint16_t *expected_data_2
);
124 int ag_drv_lport_rgmii_ate_rx_status_0_get(uint8_t rgmii_id
, uint8_t *rx_ok
, uint16_t *received_data_1
, uint16_t *received_data_0
);
125 int ag_drv_lport_rgmii_ate_rx_status_1_get(uint8_t rgmii_id
, uint16_t *received_data_3
, uint16_t *received_data_2
);
126 int ag_drv_lport_rgmii_ate_tx_cntrl_set(uint8_t rgmii_id
, const lport_rgmii_ate_tx_cntrl
*ate_tx_cntrl
);
127 int ag_drv_lport_rgmii_ate_tx_cntrl_get(uint8_t rgmii_id
, lport_rgmii_ate_tx_cntrl
*ate_tx_cntrl
);
128 int ag_drv_lport_rgmii_ate_tx_data_0_set(uint8_t rgmii_id
, uint16_t tx_data_1
, uint16_t tx_data_0
);
129 int ag_drv_lport_rgmii_ate_tx_data_0_get(uint8_t rgmii_id
, uint16_t *tx_data_1
, uint16_t *tx_data_0
);
130 int ag_drv_lport_rgmii_ate_tx_data_1_set(uint8_t rgmii_id
, uint16_t tx_data_3
, uint16_t tx_data_2
);
131 int ag_drv_lport_rgmii_ate_tx_data_1_get(uint8_t rgmii_id
, uint16_t *tx_data_3
, uint16_t *tx_data_2
);
132 int ag_drv_lport_rgmii_ate_tx_data_2_set(uint8_t rgmii_id
, uint16_t ether_type
, uint8_t tx_data_5
, uint8_t tx_data_4
);
133 int ag_drv_lport_rgmii_ate_tx_data_2_get(uint8_t rgmii_id
, uint16_t *ether_type
, uint8_t *tx_data_5
, uint8_t *tx_data_4
);
134 int ag_drv_lport_rgmii_tx_delay_cntrl_0_set(uint8_t rgmii_id
, const lport_rgmii_tx_delay_cntrl_0
*tx_delay_cntrl_0
);
135 int ag_drv_lport_rgmii_tx_delay_cntrl_0_get(uint8_t rgmii_id
, lport_rgmii_tx_delay_cntrl_0
*tx_delay_cntrl_0
);
136 int ag_drv_lport_rgmii_tx_delay_cntrl_1_set(uint8_t rgmii_id
, const lport_rgmii_tx_delay_cntrl_1
*tx_delay_cntrl_1
);
137 int ag_drv_lport_rgmii_tx_delay_cntrl_1_get(uint8_t rgmii_id
, lport_rgmii_tx_delay_cntrl_1
*tx_delay_cntrl_1
);
138 int ag_drv_lport_rgmii_rx_delay_cntrl_0_set(uint8_t rgmii_id
, const lport_rgmii_rx_delay_cntrl_0
*rx_delay_cntrl_0
);
139 int ag_drv_lport_rgmii_rx_delay_cntrl_0_get(uint8_t rgmii_id
, lport_rgmii_rx_delay_cntrl_0
*rx_delay_cntrl_0
);
140 int ag_drv_lport_rgmii_rx_delay_cntrl_1_set(uint8_t rgmii_id
, const lport_rgmii_rx_delay_cntrl_1
*rx_delay_cntrl_1
);
141 int ag_drv_lport_rgmii_rx_delay_cntrl_1_get(uint8_t rgmii_id
, lport_rgmii_rx_delay_cntrl_1
*rx_delay_cntrl_1
);
142 int ag_drv_lport_rgmii_rx_delay_cntrl_2_set(uint8_t rgmii_id
, const lport_rgmii_rx_delay_cntrl_2
*rx_delay_cntrl_2
);
143 int ag_drv_lport_rgmii_rx_delay_cntrl_2_get(uint8_t rgmii_id
, lport_rgmii_rx_delay_cntrl_2
*rx_delay_cntrl_2
);
145 #ifdef USE_BDMF_SHELL
146 bdmfmon_handle_t
ag_drv_lport_rgmii_cli_init(bdmfmon_handle_t driver_dir
);