2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights
5 * SPDX-License-Identifier: BSD-3-Clause
12 #include "emmc_config.h"
15 #include "emmc_registers.h"
19 static EMMC_ERROR_CODE
emmc_trans_sector(uint32_t *buff_address_virtual
);
21 uint32_t emmc_interrupt(void)
23 EMMC_ERROR_CODE result
;
28 prr_data
= mmio_read_32((uintptr_t) RCAR_PRR
);
29 cut_ver
= prr_data
& RCAR_CUT_MASK
;
30 if ((prr_data
& RCAR_PRODUCT_MASK
) == RCAR_PRODUCT_H3
) {
31 if (cut_ver
== RCAR_CUT_VER10
) {
33 } else if (cut_ver
== RCAR_CUT_VER11
) {
38 } else if ((prr_data
& RCAR_PRODUCT_MASK
) == RCAR_PRODUCT_M3
) {
39 if (cut_ver
== RCAR_CUT_VER10
) {
49 mmc_drv_obj
.error_info
.info1
= GETR_32(SD_INFO1
);
50 mmc_drv_obj
.error_info
.info2
= GETR_32(SD_INFO2
);
53 mmc_drv_obj
.int_event1
=
54 mmc_drv_obj
.error_info
.info1
& GETR_32(SD_INFO1_MASK
);
55 mmc_drv_obj
.int_event2
=
56 mmc_drv_obj
.error_info
.info2
& GETR_32(SD_INFO2_MASK
);
59 mmc_drv_obj
.error_info
.status1
= GETR_32(SD_ERR_STS1
);
60 mmc_drv_obj
.error_info
.status2
= GETR_32(SD_ERR_STS2
);
63 mmc_drv_obj
.error_info
.dm_info1
= GETR_32(DM_CM_INFO1
);
64 mmc_drv_obj
.error_info
.dm_info2
= GETR_32(DM_CM_INFO2
);
66 /* DM_CM_INFO EVENT */
67 mmc_drv_obj
.dm_event1
=
68 mmc_drv_obj
.error_info
.dm_info1
& GETR_32(DM_CM_INFO1_MASK
);
69 mmc_drv_obj
.dm_event2
=
70 mmc_drv_obj
.error_info
.dm_info2
& GETR_32(DM_CM_INFO2_MASK
);
73 if ((SD_INFO2_ALL_ERR
& mmc_drv_obj
.int_event2
) != 0) {
74 SETR_32(SD_INFO1_MASK
, 0x00000000U
); /* interrupt disable */
75 SETR_32(SD_INFO2_MASK
, SD_INFO2_CLEAR
); /* interrupt disable */
76 SETR_32(SD_INFO1
, 0x00000000U
); /* interrupt clear */
77 SETR_32(SD_INFO2
, SD_INFO2_CLEAR
); /* interrupt clear */
78 mmc_drv_obj
.state_machine_blocking
= FALSE
;
83 else if (((SD_INFO2_BWE
| SD_INFO2_BRE
) & mmc_drv_obj
.int_event2
)) {
85 if (SD_INFO2_BWE
& mmc_drv_obj
.int_event2
) {
86 SETR_32(SD_INFO2
, (GETR_32(SD_INFO2
) & ~SD_INFO2_BWE
));
90 SETR_32(SD_INFO2
, (GETR_32(SD_INFO2
) & ~SD_INFO2_BRE
));
93 result
= emmc_trans_sector(mmc_drv_obj
.buff_address_virtual
);
94 mmc_drv_obj
.buff_address_virtual
+= EMMC_BLOCK_LENGTH
;
95 mmc_drv_obj
.remain_size
-= EMMC_BLOCK_LENGTH
;
97 if (result
!= EMMC_SUCCESS
) {
98 /* data transfer error */
99 emmc_write_error_info(EMMC_FUNCNO_NONE
, result
);
102 SETR_32(SD_INFO1_MASK
, 0x00000000U
);
103 SETR_32(SD_INFO2_MASK
, SD_INFO2_CLEAR
);
104 SETR_32(SD_INFO1
, 0x00000000U
);
105 /* interrupt clear */
106 SETR_32(SD_INFO2
, SD_INFO2_CLEAR
);
107 mmc_drv_obj
.force_terminate
= TRUE
;
109 mmc_drv_obj
.during_transfer
= FALSE
;
111 mmc_drv_obj
.state_machine_blocking
= FALSE
;
115 /* DM_CM_INFO1: DMA-ch0 transfer complete or error occurred */
116 else if ((BIT16
& mmc_drv_obj
.dm_event1
) != 0) {
117 SETR_32(DM_CM_INFO1
, 0x00000000U
);
118 SETR_32(DM_CM_INFO2
, 0x00000000U
);
119 /* interrupt clear */
120 SETR_32(SD_INFO2
, (GETR_32(SD_INFO2
) & ~SD_INFO2_BWE
));
121 /* DM_CM_INFO2: DMA-ch0 error occured */
122 if ((BIT16
& mmc_drv_obj
.dm_event2
) != 0) {
123 mmc_drv_obj
.dma_error_flag
= TRUE
;
125 mmc_drv_obj
.during_dma_transfer
= FALSE
;
126 mmc_drv_obj
.during_transfer
= FALSE
;
128 /* wait next interrupt */
129 mmc_drv_obj
.state_machine_blocking
= FALSE
;
131 /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
132 else if ((end_bit
& mmc_drv_obj
.dm_event1
) != 0U) {
133 SETR_32(DM_CM_INFO1
, 0x00000000U
);
134 SETR_32(DM_CM_INFO2
, 0x00000000U
);
135 /* interrupt clear */
136 SETR_32(SD_INFO2
, (GETR_32(SD_INFO2
) & ~SD_INFO2_BRE
));
137 /* DM_CM_INFO2: DMA-ch1 error occured */
138 if ((BIT17
& mmc_drv_obj
.dm_event2
) != 0) {
139 mmc_drv_obj
.dma_error_flag
= TRUE
;
141 mmc_drv_obj
.during_dma_transfer
= FALSE
;
142 mmc_drv_obj
.during_transfer
= FALSE
;
144 /* wait next interrupt */
145 mmc_drv_obj
.state_machine_blocking
= FALSE
;
149 else if ((SD_INFO1_INFO0
& mmc_drv_obj
.int_event1
) != 0) {
150 /* interrupt clear */
151 SETR_32(SD_INFO1
, (GETR_32(SD_INFO1
) & ~SD_INFO1_INFO0
));
152 mmc_drv_obj
.state_machine_blocking
= FALSE
;
155 else if ((SD_INFO1_INFO2
& mmc_drv_obj
.int_event1
) != 0) {
156 /* interrupt clear */
157 SETR_32(SD_INFO1
, (GETR_32(SD_INFO1
) & ~SD_INFO1_INFO2
));
158 mmc_drv_obj
.state_machine_blocking
= FALSE
;
166 static EMMC_ERROR_CODE
emmc_trans_sector(uint32_t *buff_address_virtual
)
171 if (buff_address_virtual
== NULL
) {
172 return EMMC_ERR_PARAM
;
175 if ((mmc_drv_obj
.during_transfer
!= TRUE
)
176 || (mmc_drv_obj
.remain_size
== 0)) {
177 return EMMC_ERR_STATE
;
180 bufPtrLL
= (uint64_t *) buff_address_virtual
;
181 length
= mmc_drv_obj
.remain_size
;
184 for (i
= 0; i
< (length
>> 3); i
++) {
186 if (mmc_drv_obj
.cmd_info
.dir
== HAL_MEMCARD_WRITE
) {
187 SETR_64(SD_BUF0
, *bufPtrLL
); /* buffer --> FIFO */
191 /* Checks when the read data reaches SD_SIZE. */
192 /* The BRE bit is cleared at emmc_interrupt function. */
194 (uint32_t) (EMMC_BLOCK_LENGTH
>>
195 EMMC_BUF_SIZE_SHIFT
)) == 0U)
198 while (((GETR_32(SD_INFO2
)) & SD_INFO2_BRE
) ==
201 if (((GETR_32(SD_INFO2
)) &
202 SD_INFO2_ALL_ERR
) != 0U) {
203 return EMMC_ERR_TRANSFER
;
208 (uint32_t) (GETR_32(SD_INFO2
) &
211 *bufPtrLL
= GETR_64(SD_BUF0
); /* FIFO --> buffer */