drivers/renesas/rcar/iic_dvfs/iic_dvfs.c

   1 /*
   2  * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <common/debug.h>
   8 #include <lib/mmio.h>
   9
  10 #include "rcar_def.h"
  11 #include "cpg_registers.h"
  12 #include "iic_dvfs.h"
  13 #include "rcar_private.h"
  14
  15 #define DVFS_RETRY_MAX                          (2U)
  16
  17 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0          (0x07)
  18 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1          (0x09)
  19 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2          (0x0B)
  20 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3          (0x0E)
  21 #define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E          (0x15)
  22
  23 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0          (0x01)
  24 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1          (0x02)
  25 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2          (0x03)
  26 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3          (0x05)
  27 #define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E          (0x07)
  28
  29 #define CPG_BIT_SMSTPCR9_DVFS                   (0x04000000)
  30
  31 #define IIC_DVFS_REG_BASE                       (0xE60B0000)
  32 #define IIC_DVFS_REG_ICDR                       (IIC_DVFS_REG_BASE + 0x0000)
  33 #define IIC_DVFS_REG_ICCR                       (IIC_DVFS_REG_BASE + 0x0004)
  34 #define IIC_DVFS_REG_ICSR                       (IIC_DVFS_REG_BASE + 0x0008)
  35 #define IIC_DVFS_REG_ICIC                       (IIC_DVFS_REG_BASE + 0x000C)
  36 #define IIC_DVFS_REG_ICCL                       (IIC_DVFS_REG_BASE + 0x0010)
  37 #define IIC_DVFS_REG_ICCH                       (IIC_DVFS_REG_BASE + 0x0014)
  38
  39 #define IIC_DVFS_BIT_ICSR_BUSY                  (0x10)
  40 #define IIC_DVFS_BIT_ICSR_AL                    (0x08)
  41 #define IIC_DVFS_BIT_ICSR_TACK                  (0x04)
  42 #define IIC_DVFS_BIT_ICSR_WAIT                  (0x02)
  43 #define IIC_DVFS_BIT_ICSR_DTE                   (0x01)
  44
  45 #define IIC_DVFS_BIT_ICCR_ENABLE                (0x80)
  46 #define IIC_DVFS_SET_ICCR_START                 (0x94)
  47 #define IIC_DVFS_SET_ICCR_STOP                  (0x90)
  48 #define IIC_DVFS_SET_ICCR_RETRANSMISSION        (0x94)
  49 #define IIC_DVFS_SET_ICCR_CHANGE                (0x81)
  50 #define IIC_DVFS_SET_ICCR_STOP_READ             (0xC0)
  51
  52 #define IIC_DVFS_BIT_ICIC_TACKE                 (0x04)
  53 #define IIC_DVFS_BIT_ICIC_WAITE                 (0x02)
  54 #define IIC_DVFS_BIT_ICIC_DTEE                  (0x01)
  55
  56 #define DVFS_READ_MODE                          (0x01)
  57 #define DVFS_WRITE_MODE                         (0x00)
  58
  59 #define IIC_DVFS_SET_DUMMY                      (0x52)
  60 #define IIC_DVFS_SET_BUSY_LOOP                  (500000000U)
  61
  62 typedef enum {
  63         DVFS_START = 0,
  64         DVFS_STOP,
  65         DVFS_RETRANSMIT,
  66         DVFS_READ,
  67         DVFS_STOP_READ,
  68         DVFS_SET_SLAVE_READ,
  69         DVFS_SET_SLAVE,
  70         DVFS_WRITE_ADDR,
  71         DVFS_WRITE_DATA,
  72         DVFS_CHANGE_SEND_TO_RECIEVE,
  73         DVFS_DONE,
  74 } DVFS_STATE_T;
  75
  76 #define DVFS_PROCESS                    (1)
  77 #define DVFS_COMPLETE                   (0)
  78 #define DVFS_ERROR                      (-1)
  79
  80 #if IMAGE_BL31
  81 #define IIC_DVFS_FUNC(__name, ...)                                      \
  82 static int32_t  __attribute__ ((section (".system_ram")))               \
  83 dvfs_ ##__name(__VA_ARGS__)
  84
  85 #define RCAR_DVFS_API(__name, ...)                                      \
  86 int32_t __attribute__ ((section (".system_ram")))                       \
  87 rcar_iic_dvfs_ ##__name(__VA_ARGS__)
  88
  89 #else
  90 #define IIC_DVFS_FUNC(__name, ...)                                      \
  91 static int32_t dvfs_ ##__name(__VA_ARGS__)
  92
  93 #define RCAR_DVFS_API(__name, ...)                                      \
  94 int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
  95 #endif
  96
  97 IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
  98 {
  99         uint8_t icsr_al = 0, icsr_tack = 0;
 100         uint8_t reg, stop;
 101         uint32_t i = 0;
 102
 103         stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
 104             IIC_DVFS_SET_ICCR_STOP;
 105
 106         reg = mmio_read_8(IIC_DVFS_REG_ICSR);
 107         icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
 108         icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
 109
 110         if (icsr_al == 0 && icsr_tack == 0)
 111                 return DVFS_PROCESS;
 112
 113         if (icsr_al) {
 114                 reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
 115                 mmio_write_8(IIC_DVFS_REG_ICSR, reg);
 116
 117                 if (*state == DVFS_SET_SLAVE)
 118                         mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
 119
 120                 do {
 121                         reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
 122                             IIC_DVFS_BIT_ICSR_WAIT;
 123                 } while (reg == 0);
 124
 125                 mmio_write_8(IIC_DVFS_REG_ICCR, stop);
 126
 127                 reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 128                 mmio_write_8(IIC_DVFS_REG_ICSR, reg);
 129
 130                 i = 0;
 131                 do {
 132                         reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
 133                             IIC_DVFS_BIT_ICSR_BUSY;
 134                         if (reg == 0)
 135                                 break;
 136
 137                         if (i++ > IIC_DVFS_SET_BUSY_LOOP)
 138                                 panic();
 139
 140                 } while (1);
 141
 142                 mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
 143
 144                 (*err)++;
 145                 if (*err > DVFS_RETRY_MAX)
 146                         return DVFS_ERROR;
 147
 148                 *state = DVFS_START;
 149
 150                 return DVFS_PROCESS;
 151
 152         }
 153
 154         /* icsr_tack */
 155         mmio_write_8(IIC_DVFS_REG_ICCR, stop);
 156
 157         reg = mmio_read_8(IIC_DVFS_REG_ICIC);
 158         reg &= ~(IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE);
 159         mmio_write_8(IIC_DVFS_REG_ICIC, reg);
 160
 161         reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
 162         mmio_write_8(IIC_DVFS_REG_ICSR, reg);
 163
 164         i = 0;
 165         while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0) {
 166                 if (i++ > IIC_DVFS_SET_BUSY_LOOP)
 167                         panic();
 168         }
 169
 170         mmio_write_8(IIC_DVFS_REG_ICCR, 0);
 171         (*err)++;
 172
 173         if (*err > DVFS_RETRY_MAX)
 174                 return DVFS_ERROR;
 175
 176         *state = DVFS_START;
 177
 178         return DVFS_PROCESS;
 179 }
 180
 181 IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
 182 {
 183         uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
 184         uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
 185         int32_t result = DVFS_PROCESS;
 186         uint32_t reg, lsi_product;
 187         uint8_t mode;
 188
 189         mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
 190         mmio_write_8(IIC_DVFS_REG_ICCR, mode);
 191
 192         lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
 193         if (lsi_product == RCAR_PRODUCT_E3)
 194                 goto start;
 195
 196         reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
 197         switch (reg) {
 198         case MD14_MD13_TYPE_0:
 199                 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_0;
 200                 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_0;
 201                 break;
 202         case MD14_MD13_TYPE_1:
 203                 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_1;
 204                 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_1;
 205                 break;
 206         case MD14_MD13_TYPE_2:
 207                 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_2;
 208                 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_2;
 209                 break;
 210         default:
 211                 iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_3;
 212                 icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_3;
 213                 break;
 214         }
 215 start:
 216         mmio_write_8(IIC_DVFS_REG_ICCL, iccl);
 217         mmio_write_8(IIC_DVFS_REG_ICCH, icch);
 218
 219         mode = mmio_read_8(IIC_DVFS_REG_ICIC)
 220             | IIC_DVFS_BIT_ICIC_TACKE
 221             | IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE;
 222
 223         mmio_write_8(IIC_DVFS_REG_ICIC, mode);
 224         mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_START);
 225
 226         *state = DVFS_SET_SLAVE;
 227
 228         return result;
 229 }
 230
 231 IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
 232 {
 233         uint8_t mode;
 234         int32_t result;
 235         uint8_t address;
 236
 237         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 238         if (result == DVFS_ERROR)
 239                 return result;
 240
 241         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
 242         if (mode != IIC_DVFS_BIT_ICSR_DTE)
 243                 return result;
 244
 245         mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
 246         mmio_write_8(IIC_DVFS_REG_ICIC, mode);
 247
 248         address = slave << 1;
 249         mmio_write_8(IIC_DVFS_REG_ICDR, address);
 250
 251         *state = DVFS_WRITE_ADDR;
 252
 253         return result;
 254 }
 255
 256 IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
 257 {
 258         uint8_t mode;
 259         int32_t result;
 260
 261         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 262         if (result == DVFS_ERROR)
 263                 return result;
 264
 265         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
 266         if (mode != IIC_DVFS_BIT_ICSR_WAIT)
 267                 return result;
 268
 269         mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
 270
 271         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 272         mmio_write_8(IIC_DVFS_REG_ICSR, mode);
 273
 274         *state = DVFS_WRITE_DATA;
 275
 276         return result;
 277 }
 278
 279 IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
 280 {
 281         int32_t result;
 282         uint8_t mode;
 283
 284         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 285         if (result == DVFS_ERROR)
 286                 return result;
 287
 288         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
 289         if (mode != IIC_DVFS_BIT_ICSR_WAIT)
 290                 return result;
 291
 292         mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
 293
 294         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 295         mmio_write_8(IIC_DVFS_REG_ICSR, mode);
 296
 297         *state = DVFS_STOP;
 298
 299         return result;
 300 }
 301
 302 IIC_DVFS_FUNC(stop, DVFS_STATE_T *state, uint32_t *err)
 303 {
 304         int32_t result;
 305         uint8_t mode;
 306
 307         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 308         if (result == DVFS_ERROR)
 309                 return result;
 310
 311         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
 312         if (mode != IIC_DVFS_BIT_ICSR_WAIT)
 313                 return result;
 314
 315         mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
 316
 317         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 318         mmio_write_8(IIC_DVFS_REG_ICSR, mode);
 319
 320         *state = DVFS_DONE;
 321
 322         return result;
 323 }
 324
 325 IIC_DVFS_FUNC(done, void)
 326 {
 327         uint32_t i;
 328
 329         for (i = 0; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
 330                 if (mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY)
 331                         continue;
 332                 goto done;
 333         }
 334
 335         panic();
 336 done:
 337         mmio_write_8(IIC_DVFS_REG_ICCR, 0);
 338
 339         return DVFS_COMPLETE;
 340 }
 341
 342 IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
 343         uint8_t reg_addr)
 344 {
 345         int32_t result;
 346         uint8_t mode;
 347
 348         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 349         if (result == DVFS_ERROR)
 350                 return result;
 351
 352         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
 353         if (mode != IIC_DVFS_BIT_ICSR_WAIT)
 354                 return result;
 355
 356         mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
 357
 358         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 359         mmio_write_8(IIC_DVFS_REG_ICSR, mode);
 360
 361         *state = DVFS_RETRANSMIT;
 362
 363         return result;
 364 }
 365
 366 IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
 367 {
 368         int32_t result;
 369         uint8_t mode;
 370
 371         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 372         if (result == DVFS_ERROR)
 373                 return result;
 374
 375         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
 376         if (mode != IIC_DVFS_BIT_ICSR_WAIT)
 377                 return result;
 378
 379         mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
 380
 381         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 382         mmio_write_8(IIC_DVFS_REG_ICSR, mode);
 383
 384         mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
 385         mmio_write_8(IIC_DVFS_REG_ICIC, mode);
 386
 387         *state = DVFS_SET_SLAVE_READ;
 388
 389         return result;
 390 }
 391
 392 IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
 393                 uint8_t slave)
 394 {
 395         uint8_t address;
 396         int32_t result;
 397         uint8_t mode;
 398
 399         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 400         if (result == DVFS_ERROR)
 401                 return result;
 402
 403         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
 404         if (mode != IIC_DVFS_BIT_ICSR_DTE)
 405                 return result;
 406
 407         mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
 408         mmio_write_8(IIC_DVFS_REG_ICIC, mode);
 409
 410         address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
 411         mmio_write_8(IIC_DVFS_REG_ICDR, address);
 412
 413         *state = DVFS_CHANGE_SEND_TO_RECIEVE;
 414
 415         return result;
 416 }
 417
 418 IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
 419 {
 420         int32_t result;
 421         uint8_t mode;
 422
 423         result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
 424         if (result == DVFS_ERROR)
 425                 return result;
 426
 427         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
 428         if (mode != IIC_DVFS_BIT_ICSR_WAIT)
 429                 return result;
 430
 431         mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
 432
 433         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 434         mmio_write_8(IIC_DVFS_REG_ICSR, mode);
 435
 436         *state = DVFS_STOP_READ;
 437
 438         return result;
 439 }
 440
 441 IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
 442 {
 443         int32_t result;
 444         uint8_t mode;
 445
 446         result = dvfs_check_error(state, err, DVFS_READ_MODE);
 447         if (result == DVFS_ERROR)
 448                 return result;
 449
 450         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
 451         if (mode != IIC_DVFS_BIT_ICSR_WAIT)
 452                 return result;
 453
 454         mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
 455
 456         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
 457         mmio_write_8(IIC_DVFS_REG_ICSR, mode);
 458
 459         mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
 460         mmio_write_8(IIC_DVFS_REG_ICIC, mode);
 461
 462         *state = DVFS_READ;
 463
 464         return result;
 465 }
 466
 467 IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
 468 {
 469         uint8_t mode;
 470
 471         mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
 472         if (mode != IIC_DVFS_BIT_ICSR_DTE)
 473                 return DVFS_PROCESS;
 474
 475         mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
 476         mmio_write_8(IIC_DVFS_REG_ICIC, mode);
 477
 478         *reg_data = mmio_read_8(IIC_DVFS_REG_ICDR);
 479         *state = DVFS_DONE;
 480
 481         return DVFS_PROCESS;
 482 }
 483
 484 RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
 485 {
 486         DVFS_STATE_T state = DVFS_START;
 487         int32_t result = DVFS_PROCESS;
 488         uint32_t err = 0;
 489
 490         mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
 491         mmio_write_8(IIC_DVFS_REG_ICCR, 0);
 492 again:
 493         switch (state) {
 494         case DVFS_START:
 495                 result = dvfs_start(&state);
 496                 break;
 497         case DVFS_SET_SLAVE:
 498                 result = dvfs_set_slave(&state, &err, slave);
 499                 break;
 500         case DVFS_WRITE_ADDR:
 501                 result = dvfs_write_addr(&state, &err, reg_addr);
 502                 break;
 503         case DVFS_WRITE_DATA:
 504                 result = dvfs_write_data(&state, &err, reg_data);
 505                 break;
 506         case DVFS_STOP:
 507                 result = dvfs_stop(&state, &err);
 508                 break;
 509         case DVFS_DONE:
 510                 result = dvfs_done();
 511                 break;
 512         default:
 513                 panic();
 514                 break;
 515         }
 516
 517         if (result == DVFS_PROCESS)
 518                 goto again;
 519
 520         return result;
 521 }
 522
 523 RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
 524 {
 525         DVFS_STATE_T state = DVFS_START;
 526         int32_t result = DVFS_PROCESS;
 527         uint32_t err = 0;
 528
 529         mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
 530         mmio_write_8(IIC_DVFS_REG_ICCR, 0);
 531 again:
 532         switch (state) {
 533         case DVFS_START:
 534                 result = dvfs_start(&state);
 535                 break;
 536         case DVFS_SET_SLAVE:
 537                 result = dvfs_set_slave(&state, &err, slave);
 538                 break;
 539         case DVFS_WRITE_ADDR:
 540                 result = dvfs_write_reg_addr_read(&state, &err, reg);
 541                 break;
 542         case DVFS_RETRANSMIT:
 543                 result = dvfs_retransmit(&state, &err);
 544                 break;
 545         case DVFS_SET_SLAVE_READ:
 546                 result = dvfs_set_slave_read(&state, &err, slave);
 547                 break;
 548         case DVFS_CHANGE_SEND_TO_RECIEVE:
 549                 result = dvfs_change_send_to_recieve(&state, &err);
 550                 break;
 551         case DVFS_STOP_READ:
 552                 result = dvfs_stop_read(&state, &err);
 553                 break;
 554         case DVFS_READ:
 555                 result = dvfs_read(&state, data);
 556                 break;
 557         case DVFS_DONE:
 558                 result = dvfs_done();
 559                 break;
 560         default:
 561                 panic();
 562                 break;
 563         }
 564
 565         if (result == DVFS_PROCESS)
 566                 goto again;
 567
 568         return result;
 569 }