drivers/renesas/rcar/watchdog/swdt.c

   1 /*
   2  * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch_helpers.h>
   8 #include <debug.h>
   9 #include <gicv2.h>
  10 #include <mmio.h>
  11 #include "rcar_def.h"
  12
  13 extern void gicd_set_icenabler(uintptr_t base, unsigned int id);
  14
  15 #define RST_BASE                        (0xE6160000U)
  16 #define RST_WDTRSTCR                    (RST_BASE + 0x0054U)
  17 #define SWDT_BASE                       (0xE6030000U)
  18 #define SWDT_WTCNT                      (SWDT_BASE + 0x0000U)
  19 #define SWDT_WTCSRA                     (SWDT_BASE + 0x0004U)
  20 #define SWDT_WTCSRB                     (SWDT_BASE + 0x0008U)
  21 #define SWDT_GICD_BASE                  (0xF1010000U)
  22 #define SWDT_GICC_BASE                  (0xF1020000U)
  23 #define SWDT_GICD_CTLR                  (SWDT_GICD_BASE + 0x0000U)
  24 #define SWDT_GICD_IGROUPR               (SWDT_GICD_BASE + 0x0080U)
  25 #define SWDT_GICD_ISPRIORITYR           (SWDT_GICD_BASE + 0x0400U)
  26 #define SWDT_GICC_CTLR                  (SWDT_GICC_BASE + 0x0000U)
  27 #define SWDT_GICC_PMR                   (SWDT_GICC_BASE + 0x0004U)
  28 #define SWDT_GICD_ITARGETSR             (SWDT_GICD_BASE + 0x0800U)
  29 #define IGROUPR_NUM                     (16U)
  30 #define ISPRIORITY_NUM                  (128U)
  31 #define ITARGET_MASK                    (0x03U)
  32
  33 #define WDTRSTCR_UPPER_BYTE             (0xA55A0000U)
  34 #define WTCSRA_UPPER_BYTE               (0xA5A5A500U)
  35 #define WTCSRB_UPPER_BYTE               (0xA5A5A500U)
  36 #define WTCNT_UPPER_BYTE                (0x5A5A0000U)
  37 #define WTCNT_RESET_VALUE               (0xF488U)
  38 #define WTCSRA_BIT_CKS                  (0x0007U)
  39 #define WTCSRB_BIT_CKS                  (0x003FU)
  40 #define SWDT_RSTMSK                     (1U << 1U)
  41 #define WTCSRA_WOVFE                    (1U << 3U)
  42 #define WTCSRA_WRFLG                    (1U << 5U)
  43 #define SWDT_ENABLE                     (1U << 7U)
  44
  45 #define WDTRSTCR_MASK_ALL               (0x0000FFFFU)
  46 #define WTCSRA_MASK_ALL                 (0x000000FFU)
  47 #define WTCNT_INIT_DATA                 (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE)
  48 #define WTCSRA_INIT_DATA                (WTCSRA_UPPER_BYTE + 0x0FU)
  49 #define WTCSRB_INIT_DATA                (WTCSRB_UPPER_BYTE + 0x21U)
  50
  51 #define WTCNT_COUNT_8p13k               (0x10000U - 40687U)
  52 #define WTCNT_COUNT_8p13k_H3VER10       (0x10000U - 20343U)
  53 #define WTCNT_COUNT_8p22k               (0x10000U - 41115U)
  54 #define WTCNT_COUNT_7p81k               (0x10000U - 39062U)
  55 #define WTCSRA_CKS_DIV16                (0x00000002U)
  56
  57 static void swdt_disable(void)
  58 {
  59         uint32_t rmsk;
  60
  61         rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
  62         rmsk |= SWDT_RSTMSK;
  63         mmio_write_32(RST_WDTRSTCR, WDTRSTCR_UPPER_BYTE | rmsk);
  64
  65         mmio_write_32(SWDT_WTCNT, WTCNT_INIT_DATA);
  66         mmio_write_32(SWDT_WTCSRA, WTCSRA_INIT_DATA);
  67         mmio_write_32(SWDT_WTCSRB, WTCSRB_INIT_DATA);
  68
  69         /* Set the interrupt clear enable register */
  70         gicd_set_icenabler(RCAR_GICD_BASE, ARM_IRQ_SEC_WDT);
  71 }
  72
  73 void rcar_swdt_init(void)
  74 {
  75         uint32_t rmsk, sr;
  76 #if (RCAR_LSI != RCAR_E3)
  77         uint32_t reg, val, product_cut, chk_data;
  78
  79         reg = mmio_read_32(RCAR_PRR);
  80         product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
  81
  82         reg = mmio_read_32(RCAR_MODEMR);
  83         chk_data = reg & CHECK_MD13_MD14;
  84 #endif
  85         /* stop watchdog */
  86         if (mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE)
  87                 mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE);
  88
  89         mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
  90                       WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
  91
  92 #if (RCAR_LSI == RCAR_E3)
  93         mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
  94 #else
  95         val = WTCNT_UPPER_BYTE;
  96
  97         switch (chk_data) {
  98         case MD14_MD13_TYPE_0:
  99         case MD14_MD13_TYPE_2:
 100                 val |= WTCNT_COUNT_8p13k;
 101                 break;
 102         case MD14_MD13_TYPE_1:
 103                 val |= WTCNT_COUNT_8p22k;
 104                 break;
 105         case MD14_MD13_TYPE_3:
 106                 val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ?
 107                     WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
 108                 break;
 109         default:
 110                 ERROR("MODEMR ERROR value = %x\n", chk_data);
 111                 panic();
 112                 break;
 113         }
 114
 115         mmio_write_32(SWDT_WTCNT, val);
 116 #endif
 117         rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL;
 118         rmsk |= SWDT_RSTMSK | WDTRSTCR_UPPER_BYTE;
 119         mmio_write_32(RST_WDTRSTCR, rmsk);
 120
 121         while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U)
 122                 ;
 123
 124         /* Start the System WatchDog Timer */
 125         sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL;
 126         mmio_write_32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE));
 127 }
 128
 129 void rcar_swdt_release(void)
 130 {
 131         uintptr_t itarget = SWDT_GICD_ITARGETSR +
 132             (ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
 133         uint32_t i;
 134
 135         write_daifset(DAIF_FIQ_BIT);
 136         swdt_disable();
 137         gicv2_cpuif_disable();
 138
 139         for (i = 0; i < IGROUPR_NUM; i++)
 140                 mmio_write_32(SWDT_GICD_IGROUPR + i * 4, 0U);
 141
 142         for (i = 0; i < ISPRIORITY_NUM; i++)
 143                 mmio_write_32(SWDT_GICD_ISPRIORITYR + i * 4, 0U);
 144
 145         mmio_write_32(itarget, 0U);
 146         mmio_write_32(SWDT_GICD_CTLR, 0U);
 147         mmio_write_32(SWDT_GICC_CTLR, 0U);
 148         mmio_write_32(SWDT_GICC_PMR, 0U);
 149 }
 150
 151 void rcar_swdt_exec(uint64_t p)
 152 {
 153         gicv2_end_of_interrupt(ARM_IRQ_SEC_WDT);
 154         rcar_swdt_release();
 155         ERROR("\n");
 156         ERROR("System WDT overflow, occured address is %p\n", (void *)p);
 157         panic();
 158 }