drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c

   1 /*
   2  * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <stdint.h>
   8 #include <lib/mmio.h>
   9 #include <common/debug.h>
  10
  11 #include "boot_init_dram_regdef_d3.h"
  12
  13 #define RCAR_DDR_VERSION    "rev.0.01"
  14
  15 #if RCAR_LSI != RCAR_D3
  16 #error "Don't have DDR initialize routine."
  17 #endif
  18
  19 static void    WriteReg_32(uint32_t a, uint32_t v)
  20 {
  21         (*(volatile uint32_t*)(uintptr_t)a) = v;
  22 }
  23
  24 static uint32_t ReadReg_32(uint32_t a)
  25 {
  26         uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
  27         return w;
  28 }
  29
  30 static void init_ddr_d3_1866(void)
  31 {
  32         uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
  33
  34    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
  35    WriteReg_32(DBSC_D3_DBKIND,0x00000007);
  36    WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
  37    WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
  38    WriteReg_32(DBSC_D3_DBTR0,0x0000000D);
  39    WriteReg_32(DBSC_D3_DBTR1,0x00000009);
  40    WriteReg_32(DBSC_D3_DBTR2,0x00000000);
  41    WriteReg_32(DBSC_D3_DBTR3,0x0000000D);
  42    WriteReg_32(DBSC_D3_DBTR4,0x000D000D);
  43    WriteReg_32(DBSC_D3_DBTR5,0x0000002D);
  44    WriteReg_32(DBSC_D3_DBTR6,0x00000020);
  45    WriteReg_32(DBSC_D3_DBTR7,0x00060006);
  46    WriteReg_32(DBSC_D3_DBTR8,0x00000021);
  47    WriteReg_32(DBSC_D3_DBTR9,0x00000007);
  48    WriteReg_32(DBSC_D3_DBTR10,0x0000000E);
  49    WriteReg_32(DBSC_D3_DBTR11,0x0000000C);
  50    WriteReg_32(DBSC_D3_DBTR12,0x00140014);
  51    WriteReg_32(DBSC_D3_DBTR13,0x000000F2);
  52    WriteReg_32(DBSC_D3_DBTR14,0x00170006);
  53    WriteReg_32(DBSC_D3_DBTR15,0x00060005);
  54    WriteReg_32(DBSC_D3_DBTR16,0x09210507);
  55    WriteReg_32(DBSC_D3_DBTR17,0x040E0000);
  56    WriteReg_32(DBSC_D3_DBTR18,0x00000200);
  57    WriteReg_32(DBSC_D3_DBTR19,0x012B004B);
  58    WriteReg_32(DBSC_D3_DBTR20,0x020000FB);
  59    WriteReg_32(DBSC_D3_DBTR21,0x00040004);
  60    WriteReg_32(DBSC_D3_DBBL,0x00000000);
  61    WriteReg_32(DBSC_D3_DBODT0,0x00000001);
  62    WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
  63    WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
  64    WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
  65    WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
  66    WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
  67    WriteReg_32(DBSC_D3_SCFCTST0,0x0D020D04);
  68    WriteReg_32(DBSC_D3_SCFCTST1,0x0306040C);
  69
  70    WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
  71    WriteReg_32(DBSC_D3_DBCMD,0x01000001);
  72    WriteReg_32(DBSC_D3_DBCMD,0x08000000);
  73    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
  74    WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
  75    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
  76    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
  77
  78    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
  79    WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
  80    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
  81    WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A04);
  82    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
  83    WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
  84    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
  85    WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
  86    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
  87    WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
  88    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
  89    WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
  90    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
  91    WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
  92    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
  93    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
  94    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
  95    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
  96
  97    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
  98    WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058A00);
  99    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
 100    WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00);
 101    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 102    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 103
 104    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
 105    WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
 106    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
 107    while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 108
 109    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
 110    WriteReg_32(DBSC_D3_DBPDRGD0,0x0A206F89);
 111    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
 112    WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
 113    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
 114    WriteReg_32(DBSC_D3_DBPDRGD0,0x35A00D77);
 115    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
 116    WriteReg_32(DBSC_D3_DBPDRGD0,0x2A8A2C28);
 117    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
 118    WriteReg_32(DBSC_D3_DBPDRGD0,0x30005E00);
 119    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
 120    WriteReg_32(DBSC_D3_DBPDRGD0,0x0014CB49);
 121    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
 122    WriteReg_32(DBSC_D3_DBPDRGD0,0x00000F14);
 123    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
 124    WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
 125    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
 126    WriteReg_32(DBSC_D3_DBPDRGD0,0x000000A0);
 127    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
 128    WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
 129    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
 130    WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
 131    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
 132    WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
 133    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 134    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 135
 136    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
 137    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 138    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
 139    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 140    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
 141    WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
 142    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
 143    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 144    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
 145    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 146    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
 147    WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
 148
 149    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
 150    RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
 151    RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
 152    RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
 153    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
 154    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
 155    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
 156    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
 157    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
 158    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 159    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
 160    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 161    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
 162    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 163    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
 164    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 165
 166    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 167    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
 168    WriteReg_32(DBSC_D3_DBCMD,0x08000001);
 169    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 170    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 171
 172    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 173    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
 174    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 175    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 176
 177    for (uint32_t i = 0; i<2; i++)
 178    {
 179       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
 180       RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
 181       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
 182       RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
 183       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
 184       RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
 185       if ( RegVal_R6 > 0 )
 186       {
 187          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 188          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 189
 190          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 191          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
 192          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 193          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 194          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 195          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
 196       } else
 197       {
 198          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 199          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 200          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 201          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
 202
 203          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 204          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 205          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 206          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
 207       }
 208    }
 209
 210    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
 211    WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
 212    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
 213    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 214    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
 215    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 216    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 217    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
 218    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 219    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 220
 221    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
 222    WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
 223    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 224    WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
 225    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 226    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 227
 228    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
 229    RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
 230    WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
 231    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
 232    RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
 233    WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
 234
 235    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
 236    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
 237    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
 238    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
 239    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
 240    WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
 241    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 242    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
 243    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 244    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 245
 246    for (uint32_t i = 0; i < 2; i++)
 247    {
 248       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
 249       RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
 250       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
 251       RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
 252
 253       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
 254       RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
 255       RegVal_R12 = (RegVal_R5 >> 0x2);
 256       if ( RegVal_R12 < RegVal_R6 )
 257       {
 258          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 259          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 260
 261          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 262          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
 263          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 264          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 265
 266          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 267          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
 268       }
 269       else
 270       {
 271          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 272          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 273          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 274          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
 275          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 276          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 277          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 278          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
 279       }
 280    }
 281
 282    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
 283    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 284    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
 285    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 286    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 287    WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
 288    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 289    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 290
 291    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
 292    WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
 293    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
 294    while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
 295    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
 296    WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
 297
 298    WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
 299    WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
 300    WriteReg_32(DBSC_D3_DBRFCNF1,0x00080E23);
 301    WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
 302    WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
 303    WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
 304    WriteReg_32(DBSC_D3_DBACEN,0x00000001);
 305    WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
 306    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
 307
 308 #ifdef ddr_qos_init_setting // only for non qos_init
 309    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
 310    WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
 311    WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
 312    WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
 313    WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
 314    WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
 315    WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
 316    WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
 317    WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
 318    WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
 319    WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
 320    WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
 321    WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
 322    WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
 323    WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
 324    WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
 325    WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
 326    WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
 327    WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
 328    WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
 329    WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
 330    WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
 331    WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
 332    WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
 333    WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
 334    WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
 335    WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
 336    WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
 337    WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
 338    WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
 339    WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
 340    WriteReg_32(0xE67F0018,0x00000001);
 341    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
 342 #endif
 343 }
 344
 345 static void init_ddr_d3_1600(void)
 346 {
 347         uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
 348
 349    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
 350    WriteReg_32(DBSC_D3_DBKIND,0x00000007);
 351    WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01);
 352    WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001);
 353    WriteReg_32(DBSC_D3_DBTR0,0x0000000B);
 354    WriteReg_32(DBSC_D3_DBTR1,0x00000008);
 355    WriteReg_32(DBSC_D3_DBTR2,0x00000000);
 356    WriteReg_32(DBSC_D3_DBTR3,0x0000000B);
 357    WriteReg_32(DBSC_D3_DBTR4,0x000B000B);
 358    WriteReg_32(DBSC_D3_DBTR5,0x00000027);
 359    WriteReg_32(DBSC_D3_DBTR6,0x0000001C);
 360    WriteReg_32(DBSC_D3_DBTR7,0x00060006);
 361    WriteReg_32(DBSC_D3_DBTR8,0x00000020);
 362    WriteReg_32(DBSC_D3_DBTR9,0x00000006);
 363    WriteReg_32(DBSC_D3_DBTR10,0x0000000C);
 364    WriteReg_32(DBSC_D3_DBTR11,0x0000000A);
 365    WriteReg_32(DBSC_D3_DBTR12,0x00120012);
 366    WriteReg_32(DBSC_D3_DBTR13,0x000000D0);
 367    WriteReg_32(DBSC_D3_DBTR14,0x00140005);
 368    WriteReg_32(DBSC_D3_DBTR15,0x00050004);
 369    WriteReg_32(DBSC_D3_DBTR16,0x071F0305);
 370    WriteReg_32(DBSC_D3_DBTR17,0x040C0000);
 371    WriteReg_32(DBSC_D3_DBTR18,0x00000200);
 372    WriteReg_32(DBSC_D3_DBTR19,0x01000040);
 373    WriteReg_32(DBSC_D3_DBTR20,0x020000D8);
 374    WriteReg_32(DBSC_D3_DBTR21,0x00040004);
 375    WriteReg_32(DBSC_D3_DBBL,0x00000000);
 376    WriteReg_32(DBSC_D3_DBODT0,0x00000001);
 377    WriteReg_32(DBSC_D3_DBADJ0,0x00000001);
 378    WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002);
 379    WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010);
 380    WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001);
 381    WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046);
 382    WriteReg_32(DBSC_D3_SCFCTST0,0x0D020C04);
 383    WriteReg_32(DBSC_D3_SCFCTST1,0x0305040C);
 384
 385    WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A);
 386    WriteReg_32(DBSC_D3_DBCMD,0x01000001);
 387    WriteReg_32(DBSC_D3_DBCMD,0x08000000);
 388    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 389    WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000);
 390    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 391    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 392
 393    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008);
 394    WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000);
 395    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
 396    WriteReg_32(DBSC_D3_DBPDRGD0,0x04058904);
 397    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091);
 398    WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
 399    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095);
 400    WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD);
 401    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099);
 402    WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B);
 403    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
 404    WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
 405    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
 406    WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E);
 407    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 408    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073);
 409    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 410    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 411
 412    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
 413    WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058900);
 414    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090);
 415    WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900);
 416    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 417    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 418
 419    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
 420    WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700);
 421    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
 422    while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 423
 424    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004);
 425    WriteReg_32(DBSC_D3_DBPDRGD0,0x08C05FF0);
 426    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022);
 427    WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B);
 428    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023);
 429    WriteReg_32(DBSC_D3_DBPDRGD0,0x2D9C0B66);
 430    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024);
 431    WriteReg_32(DBSC_D3_DBPDRGD0,0x2A88C400);
 432    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025);
 433    WriteReg_32(DBSC_D3_DBPDRGD0,0x30005200);
 434    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026);
 435    WriteReg_32(DBSC_D3_DBPDRGD0,0x0014A9C9);
 436    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027);
 437    WriteReg_32(DBSC_D3_DBPDRGD0,0x00000D70);
 438    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028);
 439    WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046);
 440    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029);
 441    WriteReg_32(DBSC_D3_DBPDRGD0,0x00000098);
 442    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
 443    WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047);
 444    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020);
 445    WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884);
 446    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A);
 447    WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10);
 448    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 449    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 450
 451    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7);
 452    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 453    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8);
 454    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 455    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9);
 456    WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
 457    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7);
 458    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 459    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8);
 460    WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D);
 461    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9);
 462    WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D);
 463
 464    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E);
 465    RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1;
 466    RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
 467    RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2;
 468    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011);
 469    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
 470    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012);
 471    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3);
 472    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016);
 473    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 474    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017);
 475    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 476    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018);
 477    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 478    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019);
 479    WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6);
 480
 481    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 482    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181);
 483    WriteReg_32(DBSC_D3_DBCMD,0x08000001);
 484    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 485    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 486
 487    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 488    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601);
 489    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 490    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 491
 492    for (uint32_t i = 0; i<2; i++)
 493    {
 494       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
 495       RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8;
 496       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
 497       RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
 498       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
 499       RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
 500       if ( RegVal_R6 > 0 )
 501       {
 502          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 503          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 504
 505          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 506          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
 507          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 508          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 509          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 510          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6);
 511       } else
 512       {
 513          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 514          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 515          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 516          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7);
 517
 518          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 519          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 520          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 521          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
 522       }
 523    }
 524
 525    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
 526    WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0);
 527    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
 528    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 529    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
 530    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 531    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 532    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801);
 533    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 534    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 535
 536    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005);
 537    WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8);
 538    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 539    WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001);
 540    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 541    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 542
 543    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF);
 544    RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
 545    WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
 546    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF);
 547    RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0);
 548    WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00)));
 549
 550    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
 551    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
 552    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
 553    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285);
 554    WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C);
 555    WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087);
 556    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 557    WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401);
 558    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 559    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 560
 561    for (uint32_t i = 0; i < 2; i++)
 562    {
 563       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20);
 564       RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8);
 565       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20);
 566       RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF);
 567
 568       WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20);
 569       RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007);
 570       RegVal_R12 = (RegVal_R5 >> 0x2);
 571       if ( RegVal_R12 < RegVal_R6 )
 572       {
 573          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 574          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 575
 576          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 577          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
 578          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 579          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 580
 581          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 582          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
 583       }
 584       else
 585       {
 586          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 587          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8);
 588          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20);
 589          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
 590          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 591          RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00);
 592          WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20);
 593          WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
 594       }
 595    }
 596    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0);
 597    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 598    WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0);
 599    WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5);
 600    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001);
 601    WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001);
 602    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006);
 603    while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 );
 604
 605    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003);
 606    WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700);
 607    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007);
 608    while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 );
 609    WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021);
 610    WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E);
 611
 612    WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010);
 613    WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B);
 614    WriteReg_32(DBSC_D3_DBRFCNF1,0x00080C30);
 615    WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000);
 616    WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001);
 617    WriteReg_32(DBSC_D3_DBRFEN,0x00000001);
 618    WriteReg_32(DBSC_D3_DBACEN,0x00000001);
 619    WriteReg_32(DBSC_D3_DBPDLK0,0x00000000);
 620    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
 621
 622 #ifdef ddr_qos_init_setting // only for non qos_init
 623    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234);
 624    WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218);
 625    WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4);
 626    WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037);
 627    WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001);
 628    WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111);
 629    WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123);
 630    WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00);
 631    WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00);
 632    WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000);
 633    WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000);
 634    WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300);
 635    WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0);
 636    WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200);
 637    WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100);
 638    WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300);
 639    WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0);
 640    WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200);
 641    WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100);
 642    WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100);
 643    WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0);
 644    WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0);
 645    WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040);
 646    WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0);
 647    WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0);
 648    WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080);
 649    WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040);
 650    WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040);
 651    WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030);
 652    WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020);
 653    WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010);
 654    WriteReg_32(0xE67F0018,0x00000001);
 655    WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000);
 656 #endif
 657 }
 658
 659 #define PRR                     (0xFFF00044U)
 660 #define PRR_PRODUCT_MASK        (0x00007F00U)
 661 #define PRR_PRODUCT_D3          (0x00005800U)
 662
 663 #define RST_MODEMR              (0xE6160060)
 664 #define MODEMR_MD19             (0x00080000U)
 665
 666 int32_t rcar_dram_init(void)
 667 {
 668         uint32_t reg;
 669         uint32_t ddr_mbps;
 670
 671         reg = mmio_read_32(PRR);
 672
 673         if (PRR_PRODUCT_D3 != (reg & PRR_PRODUCT_MASK)) {
 674                 ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n",
 675                       reg);
 676                 panic();
 677         }
 678
 679         reg = mmio_read_32(RST_MODEMR);
 680         if (MODEMR_MD19 == (reg & MODEMR_MD19)) {
 681                 init_ddr_d3_1866();
 682                 ddr_mbps = 1866;
 683         } else {
 684                 init_ddr_d3_1600();
 685                 ddr_mbps = 1600;
 686         }
 687
 688         NOTICE("BL2: DDR%d\n", ddr_mbps);
 689
 690         return 0;
 691 }